== Series Details ==
Series: Panel replay selective update support (rev8)
URL : https://patchwork.freedesktop.org/series/128193/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14621 -> Patchwork_128193v8
Summary
---
*
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3b30353dbc09..5289cc651c8b 100644
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubra
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
ro
From: Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only
which to trigger once to avoid flooding dmesg.
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++
1 file changed, 3
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate
to it.
Bspec: 67066
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/inte
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt
From: José Roberto de Souza
No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL
register. Restrict the programming only to Xe_LPD+.
BSpec: 49213
CC: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/
From: Matt Roper
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/soc/intel_pch.c |
From: Anusha Srivatsa
Add step 9 from initialize display sequence.
v2: Commit subject improved
Bpsec: 49189
Signed-off-by: Anusha Srivatsa
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/
From: Matt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different
maximum memory bandwidths, but uses a much simpler algorithm than igpu
platforms use.
Bspec: 64631
CC: Jani Nikula
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Radhakrishna
From: Ravi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform
v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables
Bspec: 74165
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/gpu/dr
From: Lucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpdp, but with no
PORT_B.
v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES
Bspec: 67066
CC: Matt Roper
Signed-off-by: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
-
Tables for eDP PHY PLL configuration for different link rates added for
Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
Xe2_HPD has C20 PHY.
v2: Updated with a more appropriate Bspec number.
Bspec: 74165
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by:
Xe2_HPD has different offsets for C20 PHY SRAM configuration context
location. Use the display version to select the right address.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make
From: José Roberto de Souza
Xe2_HPD has a different value to power down port A.
BSpec: 65450
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
1 file changed, 14 inse
From: Radhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Balasubramani
From: Clint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs.
Bspec: 65243
CC: Lucas De Marchi
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
1 file changed, 11 insertion
Display code uses IS_BATTLEMAGE macro but the platform support doesn't
exist in i915. So fake IS_BATTLEMAGE macro defined to enable building
i915 code. We should make sure the macro parameter is used in the
always-false expression so that we don't run into "unused variable"
warnings from i915 buil
From: Clint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
Bspec: 64539
CC: Jani Nikula
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
1 file
Adds display support for Battlemage.
v4:
* Dropped patch "drm/i915/xe2hpd: Skip CCS modifiers" as there is
already a patch merged taking care of this fix.
* Dropped patch "drm/i915/display: Enable RM timeout detection" as it
is not really a BMG enablement patch. Will be posted as a separate
== Series Details ==
Series: Panel replay selective update support (rev8)
URL : https://patchwork.freedesktop.org/series/128193/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Panel replay selective update support (rev8)
URL : https://patchwork.freedesktop.org/series/128193/
State : warning
== Summary ==
Error: dim checkpatch failed
593e3471f223 drm/i915/psr: Rename has_psr2 as has_sel_update
-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment
On 19.04.2024 14:26, Jonathan Cavitt wrote:
> In the case where lmem_size < dsm_base, hardware is reporting that
> stolen lmem is unusable. In this case, instead of throwing a warning,
> we can continue execution as normal by disabling stolen LMEM support.
> For example, this change will allow the
From: Gareth Yu
Re-train the main link when the sink asserts a HPD for the main lnk
lost.
Cc : Tejas Upadhyay
Cc : Matt Roper
Cc : Ville Syrjälä
Signed-off-by: Gareth Yu
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/dr
== Series Details ==
Series: Enable Aux Based EDP HDR (rev4)
URL : https://patchwork.freedesktop.org/series/132009/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14620 -> Patchwork_132009v4
Summary
---
**SUCCESS**
== Series Details ==
Series: Enable Aux Based EDP HDR (rev4)
URL : https://patchwork.freedesktop.org/series/132009/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: war
Write panel override luminance values which helps the TCON decide
if tone mapping needs to be enabled or not.
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_dp_aux_backlight.c | 25 +++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel
Drop comments for EDP HDR DPCD registers as the code and
conditions will tell us what can be written where.
--v2
-Drop the comments altogether instead of just renaming them
[Sebastian]
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
1 file change
As of now whenerver HDR is switched on we use the PWM to change the
backlight as opposed to AUX based backlight changes in terms of nits.
This patch writes to the appropriate DPCD registers to enable aux
based backlight using values in nits.
--v2
-Fix max_cll and max_fall assignment [Jani]
-Fix th
Make has_gamut_metadata_dip() non static so it can also be used to
at other places eg in intel_dp_aux_backlight. So that we can check
if HW is capable of sending SDP which helps us decide if we use
AUX based HDR control or via SDP.
--v2
-State reason the function is needed [Arun]
Signed-off-by: S
Add checks to see the HDR capability of TCON panel.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display_types.h| 5 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/displ
Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to
INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit is tells TCON to
ignore DPCD colorimetry values and take the one's sent through
SDP.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
1 file changed,
This series enables Aux based EDP HDR and backlight controls.
The DPCD written to are intel proprietary and are filled
based on the specs that were provided to TCON vendors.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (6):
drm/i915/dp: Make has_gamut_metadata_dip() non static
drm/i915/dp: Add
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