> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, November 7, 2023 9:48 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 4/4] drm/i915/dp: Ignore max_requested_bpc if its
> too low for DSC
>
> At the moment,
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, November 7, 2023 9:48 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Use helpers to get dsc
> min/max input bpc
>
> Use helpers for so
== Series Details ==
Series: drm/ttm: replace busy placement with flags v2
URL : https://patchwork.freedesktop.org/series/126164/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13852 -> Patchwork_126164v1
Summary
---
== Series Details ==
Series: drm/ttm: replace busy placement with flags v2
URL : https://patchwork.freedesktop.org/series/126164/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/ttm: replace busy placement with flags v2
URL : https://patchwork.freedesktop.org/series/126164/
State : warning
== Summary ==
Error: dim checkpatch failed
c56bdb99b8b9 drm/ttm: replace busy placement with flags v2
-:275: WARNING:UNSPECIFIED_INT: Prefer 'unsign
Instead of a list of separate busy placement add flags which indicate
that a placement should only be used when there is room or if we need to
evict.
v2: add missing TTM_PL_FLAG_IDLE for i915
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
drivers/gpu/drm/
== Series Details ==
Series: drm/i915/xe2lpd: WA for underruns during FBC enable (rev2)
URL : https://patchwork.freedesktop.org/series/126143/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13852 -> Patchwork_126143v2
Summar
FIFO underruns are observed when FBC is enabled on plane 2 or 3.
This is root caused to a HW bug and the recommended WA is to
update the FBC enabling sequence. The plane binding register
bits need to be updated separately before programming the FBC
enable bit.
HSD: 16021232047
Signed-off-by: Vinod
Update the FBC enabling sequence. The plane binding register bits
need to programmed before fbe enable bit.
v2: update the patch subject and description as this underrun is not
tied to PSR. FIFO underruns are observed when FBC is enabled on
planes 2 or 3.
v2: Updated the comments and remo
== Series Details ==
Series: drm/i915/vma: Fix potential UAF on multi-tile platforms (rev2)
URL : https://patchwork.freedesktop.org/series/126012/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13852 -> Patchwork_126012v2
Su
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev4)
URL : https://patchwork.freedesktop.org/series/126064/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13852 -> Patchwork_126064v4
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev4)
URL : https://patchwork.freedesktop.org/series/126064/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't
On Wed, 08 Nov 2023, Ville Syrjälä wrote:
> On Wed, Nov 08, 2023 at 06:59:18PM +0200, Ville Syrjälä wrote:
>> On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
>> > Display driver shall read DPCD 00071h[3:1] during configuration
>> > to get PSR setup time. This register provides the set
On Wed, Nov 08, 2023 at 06:59:18PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
> > Display driver shall read DPCD 00071h[3:1] during configuration
> > to get PSR setup time. This register provides the setup time
> > requirement on the VSC SDP entry pac
[Public]
> -Original Message-
> From: Wentland, Harry
> Sent: Wednesday, November 8, 2023 9:40 AM
> To: Imre Deak ; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Manasi Navare
> ; Lyude Paul ; Francis,
> David ; Mikita Lipski ;
> Deucher, Alexander
> Subject: Re: [PATCH v4 02/30]
On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
> Display driver shall read DPCD 00071h[3:1] during configuration
> to get PSR setup time. This register provides the setup time
> requirement on the VSC SDP entry packet. If setup time cannot be
> met with the current timings
> (e.g., PS
Object debugging tools were sporadically reporting illegal attempts to
free a still active i915 VMA object from when parking a GPU tile believed
to be idle.
[161.359441] ODEBUG: free active (active state 0) object: 88811643b958
object type: i915_active hint: __i915_vma_active+0x0/0x50 [i915]
On Tue, Nov 07, 2023 at 09:50:23AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Improve BW management on MST links (rev16)
> URL : https://patchwork.freedesktop.org/series/125490/
> State : success
Patchset pushed to drm-intel-next, thanks for the reviews, acks.
>
> ==
== Series Details ==
Series: drm/i915/xe2lpd: WA for underruns during FBC enable
URL : https://patchwork.freedesktop.org/series/126143/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13849 -> Patchwork_126143v1
Summary
-
In helper intel_dp_dsc_max_src_input_bpc it is assumed that platforms
earlier to ICL do not support DSC, and the function returns 0 for
those platforms.
Use HAS_DSC macro instead and return 0 for platforms that do not support
DSC.
v2: Updated commit message with clarification. (Jani)
Signed-off-
On Thu, Sep 07, 2023 at 03:25:40PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Split intel_update_crtc() into two parts such that the first
> part performs all the non-vblank evasion preparatory stuff,
> and the second part just does the vblank evasion stuff.
>
> For now we just call t
On 2023-10-30 11:58, Imre Deak wrote:
> From: Ville Syrjälä
>
> The current code does '(bpp << 4) / 16' in the MST PBN
> calculation, but that is just the same as 'bpp' so the
> DSC codepath achieves absolutely nothing. Fix it up so that
> the fractional part of the bpp value is actually used
Because of HW bug, the FBC enabling sequence need to be updated.
The plane binding registrer need to be updated before programming
the FBC enable bit.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-
Update the FBC enabling sequence. The plane binding register bits
need to programmed before fbe enable bit.
v2: update the patch subject and description as this underrun is not
tied to PSR. FIFO underruns are observed when FBC is enabled on
plane other than the primary.
Vinod Govindapilla
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev3)
URL : https://patchwork.freedesktop.org/series/126064/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13849 -> Patchwork_126064v3
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev3)
URL : https://patchwork.freedesktop.org/series/126064/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't
Hi Dave & Daniel -
I see Dave already sent the pull request for v6.7-rc1 fixes, but here's
some more.
drm-intel-next-fixes-2023-11-08:
drm/i915 fixes for v6.7-rc1:
- Fix null dereference when perf interface is not available
- Fix a -Wstringop-overflow warning
- Fix a -Wformat-truncation warning
Hi Dave, Daniel,
drm-misc-next-fixes is empty, have a pull request for drm-misc-fixes.
Cheers,
~Maarten
drm-misc-fixes-2023-11-08:
drm-misc-fixes for v6.7-rc1:
- drm-misc-fixes from 2023-11-02 + a single qxl memory leak fix.
The following changes since commit 8f5ad367e8b884772945c6c9fb622ac94b
== Series Details ==
Series: drm/i915: Use drm_atomic_helper_wait_for_fences helper.
URL : https://patchwork.freedesktop.org/series/126130/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13848 -> Patchwork_126130v1
Summary
-
== Series Details ==
Series: drm: i915: Adapt to -Walloc-size
URL : https://patchwork.freedesktop.org/series/126127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13848 -> Patchwork_126127v1
Summary
---
**SUCCESS**
== Series Details ==
Series: drm: i915: Adapt to -Walloc-size
URL : https://patchwork.freedesktop.org/series/126127/
State : warning
== Summary ==
Error: dim checkpatch failed
bec993afd2d0 drm: i915: Adapt to -Walloc-size
-:19: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev2)
URL : https://patchwork.freedesktop.org/series/126064/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13848 -> Patchwork_126064v2
From: Maarten Lankhorst
The fence api specifies you should wait for fence to completion, not
give up after whatever timeout was originally configured. The fences
themselves should prevent the timeout from being indefinite.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_ato
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add ability for tracking buffer
objects per client (rev2)
URL : https://patchwork.freedesktop.org/series/126064/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't
GCC 14 introduces a new -Walloc-size included in -Wextra which errors out
like:
```
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c: In function
‘eb_copy_relocations’:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1681:24: error: allocation of
insufficient size ‘1’ for type ‘struct drm_i915_gem_r
On Tue, 07 Nov 2023, Sam James wrote:
> GCC 14 introduces a new -Walloc-size included in -Wextra which errors out
> like:
> ```
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c: In function
> ‘eb_copy_relocations’:
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1681:24: error: allocation of
>
On Wed, 2023-11-08 at 12:53 +0530, Animesh Manna wrote:
> Add debugfs support which will print source and sink status
> per connector basis. Existing i915_psr_status and
> i915_psr_sink_status will be used to get the source and
> sink status of panel replay.
>
> v1: Initial version. [rb-ed by Arun
== Series Details ==
Series: Panel replay phase1 implementation (rev11)
URL : https://patchwork.freedesktop.org/series/94470/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13848 -> Patchwork_94470v11
Summary
---
**SU
== Series Details ==
Series: Panel replay phase1 implementation (rev11)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Panel replay phase1 implementation (rev11)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim checkpatch failed
2b22edb04a4f drm/panelreplay: dpcd register definition for panelreplay
28d040b55117 drm/i915/psr: Move psr sp
On Tue, Nov 07, 2023 at 02:15:03AM +0200, Imre Deak wrote:
> Enable DSC decompression for all streams. In particular atm if a sink is
> connected to a last branch device that is downstream of the first branch
> device connected to the source, decompression is not enabled for it.
> Similarly it's no
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