[Intel-gfx] ✗ Fi.CI.BAT: failure for Cleanup a few functions in C10/C20 handling

2023-10-18 Thread Patchwork
== Series Details == Series: Cleanup a few functions in C10/C20 handling URL : https://patchwork.freedesktop.org/series/125323/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13774 -> Patchwork_125323v1 Summary --- **

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Cleanup a few functions in C10/C20 handling

2023-10-18 Thread Patchwork
== Series Details == Series: Cleanup a few functions in C10/C20 handling URL : https://patchwork.freedesktop.org/series/125323/ State : warning == Summary == Error: dim checkpatch failed 8ddc8e558b4d drm/i915/display: Abstract C10/C20 pll hw readout ca3f8c7416f8 drm/i915/display: Abstract C10/

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/lnl: Assign correct phys

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/lnl: Assign correct phys URL : https://patchwork.freedesktop.org/series/125322/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13774 -> Patchwork_125322v1 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/lnl: Assign correct phys

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/lnl: Assign correct phys URL : https://patchwork.freedesktop.org/series/125322/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for fix DRM_USE_DYNAMIC_DEBUG=y regression (rev4)

2023-10-18 Thread Patchwork
== Series Details == Series: fix DRM_USE_DYNAMIC_DEBUG=y regression (rev4) URL : https://patchwork.freedesktop.org/series/125063/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for fix DRM_USE_DYNAMIC_DEBUG=y regression (rev4)

2023-10-18 Thread Patchwork
== Series Details == Series: fix DRM_USE_DYNAMIC_DEBUG=y regression (rev4) URL : https://patchwork.freedesktop.org/series/125063/ State : warning == Summary == Error: dim checkpatch failed de473fa889bf test-dyndbg: fixup CLASSMAP usage error 6120b244541c dyndbg: reword "class unknown, " to "cl

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mst: MST modeset sequence fixes

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/mst: MST modeset sequence fixes URL : https://patchwork.freedesktop.org/series/125307/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_125307v1 Summary --- **FAI

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mst: MST modeset sequence fixes

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/mst: MST modeset sequence fixes URL : https://patchwork.freedesktop.org/series/125307/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add bigjoiner force enable option to debugfs (rev4)

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915: Add bigjoiner force enable option to debugfs (rev4) URL : https://patchwork.freedesktop.org/series/124730/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_124730v4 Sum

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL URL : https://patchwork.freedesktop.org/series/125293/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_125293v1 Summa

[Intel-gfx] [PATCH 2/2] drm/i915/display: Abstract C10/C20 pll calculation

2023-10-18 Thread Lucas De Marchi
As done with the hw readout, properly abstract the C10/C20 phy details inside intel_cx0_phy.c. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 drivers/gpu/drm/i915/display/intel_cx0_phy.h | 6 ++ drivers/gpu/drm/i915/display/intel_d

[Intel-gfx] [PATCH 1/2] drm/i915/display: Abstract C10/C20 pll hw readout

2023-10-18 Thread Lucas De Marchi
intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking it to the rest of the driver. Start abstracting this by exporting a single PLL hw readout that handles the differences between C20 and C10 internally to that compilation unit. Signed-off-by: Lucas De Marchi --- drivers/gpu/

[Intel-gfx] [PATCH 0/2] Cleanup a few functions in C10/C20 handling

2023-10-18 Thread Lucas De Marchi
I started a cleanup on the c10/c20 while adding LNL, but had to stop due to other priorities, so this is not a complete cleanup. More details and ask for feedback at https://patchwork.freedesktop.org/series/125322/ Maybe it's worth getting these in regardless. Lucas De Marchi (2): drm/i915/dis

[Intel-gfx] [PATCH 0/2] drm/i915/lnl: Assign correct phys

2023-10-18 Thread Lucas De Marchi
For this series to work, we still need a separate patch on the xe side so it defines the LNL platform macro to be used by display. One thing missing for LNL during the previous patches was the port <-> phy assignment. With the bspec now clarified, this is the minimum changes needed for LNL. As th

[Intel-gfx] [PATCH 2/2] drm/i915/lnl: Fix check for TC phy

2023-10-18 Thread Lucas De Marchi
With MTL adding PICA between the port and the real phy, the path add for DG2 stopped being followed and newer platforms are simply using the older path for TC phys. LNL is no different than MTL in this aspect, so just add it to the mess. In future the phy and port designation and deciding if it's T

[Intel-gfx] [PATCH 1/2] drm/i915/lnl: Extend C10/C20 phy

2023-10-18 Thread Lucas De Marchi
For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() accordingly. This reverts the change in commit e388ae97e225 ("drm/i915/display: Eliminate IS_METEORLAKE checks") that turned that into a display engine

[Intel-gfx] ✓ Fi.CI.BAT: success for display device info as a separate debugfs entry (rev6)

2023-10-18 Thread Patchwork
== Series Details == Series: display device info as a separate debugfs entry (rev6) URL : https://patchwork.freedesktop.org/series/125222/ State : success == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_125222v6 Summary --

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_14019821291

2023-10-18 Thread Matt Roper
On Wed, Oct 18, 2023 at 01:34:43PM +0530, Dnyaneshwar Bhadane wrote: > This workaround is primarily implemented by the BIOS. However if the > BIOS applies the workaround it will reserve a small piece of our DSM > (which should be at the top, right below the WOPCM); we just need to > keep that regi

[Intel-gfx] ✗ Fi.CI.BUILD: warning for display device info as a separate debugfs entry (rev6)

2023-10-18 Thread Patchwork
== Series Details == Series: display device info as a separate debugfs entry (rev6) URL : https://patchwork.freedesktop.org/series/125222/ State : warning == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/125222/revisions/6/mbox/ not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for display device info as a separate debugfs entry (rev6)

2023-10-18 Thread Patchwork
== Series Details == Series: display device info as a separate debugfs entry (rev6) URL : https://patchwork.freedesktop.org/series/125222/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Flush WC GGTT only on required platforms (rev9)

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915: Flush WC GGTT only on required platforms (rev9) URL : https://patchwork.freedesktop.org/series/125111/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_125111v9 Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Reset message bus after each read/write operation (rev5)

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/display: Reset message bus after each read/write operation (rev5) URL : https://patchwork.freedesktop.org/series/124602/ State : success == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_124602v5 ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add Wa_14019821291

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/mtl: Add Wa_14019821291 URL : https://patchwork.freedesktop.org/series/125282/ State : success == Summary == CI Bug Log - changes from CI_DRM_13773 -> Patchwork_125282v1 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Wa_14019821291

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/mtl: Add Wa_14019821291 URL : https://patchwork.freedesktop.org/series/125282/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/i915/intel_uncore.h:346

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: An attempt to get rid of IOSF GPIO on VLV

2023-10-18 Thread Patchwork
== Series Details == Series: drm/i915/dsi: An attempt to get rid of IOSF GPIO on VLV URL : https://patchwork.freedesktop.org/series/125268/ State : success == Summary == CI Bug Log - changes from CI_DRM_13772 -> Patchwork_125268v1 Summary -

Re: [Intel-gfx] [CI] PR for new GuC v70.13.1

2023-10-18 Thread John Harrison
Apologies, I sent this with the wrong subject. Please ignore. Will resend with the correct subject. John. On 10/18/2023 12:07, john.c.harri...@intel.com wrote: The following changes since commit 7727f7e3b3358713c7c91c64a835e80c331a6b8b: Merge branch 'patch-1696561325' into 'main' (2023-10

[Intel-gfx] PR for new GuC v70.13.1

2023-10-18 Thread John . C . Harrison
The following changes since commit 7727f7e3b3358713c7c91c64a835e80c331a6b8b: Merge branch 'patch-1696561325' into 'main' (2023-10-06 03:04:57 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_70.13.1 for you to fetch changes up to 44a9510c94ac

[Intel-gfx] [CI] PR for new GuC v70.13.1

2023-10-18 Thread John . C . Harrison
The following changes since commit 7727f7e3b3358713c7c91c64a835e80c331a6b8b: Merge branch 'patch-1696561325' into 'main' (2023-10-06 03:04:57 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_70.13.1 for you to fetch changes up to 44a9510c94ac

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Ville Syrjälä
On Wed, Oct 18, 2023 at 07:13:12PM +0200, Maarten Lankhorst wrote: > > > On 2023-10-18 17:38, Ville Syrjälä wrote: > > On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: > >> We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence > >> implementation. Lets drop i915_sw_f

Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

2023-10-18 Thread Andi Shyti
Hi Vinay, On Tue, Oct 17, 2023 at 12:53:09PM -0700, Vinay Belgaumkar wrote: > This bit does not cause an explicit L3 flush. We already use > PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose. > > v2: Use FLUSH_L3 only pre-MTL since spec will likely remain > the same going forward. > > Cc: Nirmoy Das

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Maarten Lankhorst
On 2023-10-18 17:38, Ville Syrjälä wrote: On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence implementation. Lets drop i915_sw_fence usage from display code and use dma_fence interfaces directly. For this purpo

[Intel-gfx] [PATCH v7c 20/24] dyndbg: refactor *dynamic_emit_prefix

2023-10-18 Thread Jim Cromie
Refactor the split of duties between outer & inner fns. The outer fn was previously just an inline unlikely forward to inner, which did all the work. Now, outer handles +t and +l flags itself, and calls inner only when _DPRINTK_FLAGS_INCL_LOOKUP is needed. No functional change. But it does make

[Intel-gfx] [PATCH v7c 24/24] drm: restore CONFIG_DRM_USE_DYNAMIC_DEBUG un-BROKEN

2023-10-18 Thread Jim Cromie
Lots of burn-in testing needed before signing, upstreaming. NOTE: I set default Y to maximize testing by default. Is there a better way to do this ? Signed-off-by: Jim Cromie --- drivers/gpu/drm/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/Kconfi

[Intel-gfx] [PATCH v7c 23/24] drm-drivers: DRM_CLASSMAP_USE in 2nd batch of drivers, helpers

2023-10-18 Thread Jim Cromie
Add a DRM_CLASSMAP_USE declaration to 2nd batch of helpers and *_drv.c files. For drivers, add the decl just above the module's PARAMs, since it identifies the "inherited" drm.debug param. Note: with CONFIG_DRM_USE_DYNAMIC_DEBUG=y, a module not also declaring DRM_CLASSMAP_USE will have its class'

[Intel-gfx] [PATCH v7c 21/24] dyndbg: change WARN_ON to WARN_ON_ONCE

2023-10-18 Thread Jim Cromie
This shouldn't ever happen, and 1st 2 conditions never have. The 3rd condition did happen, due to corrupt linkage due to a missing align(8) in DYNDBG_CLASSMAP_USE, on the static struct allocation into the __dyndbg_class_users section. Not sure whether changing to _ONCE is appropriate - this is a

[Intel-gfx] [PATCH v7c 17/24] dyndbg-doc: add classmap info to howto

2023-10-18 Thread Jim Cromie
Add some basic info on classmap usage and api cc: linux-...@vger.kernel.org Signed-off-by: Jim Cromie --- v5- adjustments per Randy Dunlap, me v7b- checkpatch fixes --- .../admin-guide/dynamic-debug-howto.rst | 60 ++- 1 file changed, 59 insertions(+), 1 deletion(-) diff -

[Intel-gfx] [PATCH v7c 22/24] drm: use correct ccflags-y spelling

2023-10-18 Thread Jim Cromie
Incorrectly spelled CFLAGS- failed to add -DDYNAMIC_DEBUG_MODULE, which broke builds with: CONFIG_DRM_USE_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_DYNAMIC_DEBUG=n Also add subdir-ccflags so that all drivers pick up the addition. Fixes: 84ec67288c10 ("drm_print: wrap drm_*_dbg in dyndbg

[Intel-gfx] [PATCH v7c 18/24] dyndbg: reserve flag bit _DPRINTK_FLAGS_PREFIX_CACHED

2023-10-18 Thread Jim Cromie
Reserve bit 7 to remember that a pr-debug callsite is/was: - enabled, with +p - wants a dynamic-prefix, with one+ of module:function:sourcfile - was previously called - was thus saved in the cache. NOT YET. Its unclear whether any cache fetch would be faster than 2-3 field fetches, but theres anot

[Intel-gfx] [PATCH v7c 07/24] dyndbg: drop NUM_TYPE_ARRAY

2023-10-18 Thread Jim Cromie
ARRAY_SIZE works here, since array decl is complete. no functional change Signed-off-by: Jim Cromie --- include/linux/dynamic_debug.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h index b53217e4b711..8116d0a0

[Intel-gfx] [PATCH v7c 14/24] dyndbg-API: fix CONFIG_DRM_USE_DYNAMIC_DEBUG regression

2023-10-18 Thread Jim Cromie
DECLARE_DYNDBG_CLASSMAP() has a design error; it fails a basic K&R rule: "define once, refer many times". When DRM_USE_DYNAMIC_DEBUG=y, DECLARE_DYNDBG_CLASSMAP() is used across DRM core & drivers; they all repeat the same classmap-defn args, which must match for the modules to respond together whe

[Intel-gfx] [PATCH v7c 11/24] dyndbg: tighten fn-sig of ddebug_apply_class_bitmap

2023-10-18 Thread Jim Cromie
old_bits arg is currently a pointer to the input bits, but this could allow inadvertent changes to the input by the fn. Disallow this. And constify new_bits while here. Signed-off-by: Jim Cromie --- lib/dynamic_debug.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-

[Intel-gfx] [PATCH v7c 15/24] dyndbg: refactor ddebug_classparam_clamp_input

2023-10-18 Thread Jim Cromie
Extract input validation code, from param_set_dyndbg_module_classes() (the sys-node >handler) to new: ddebug_classparam_clamp_input(kp), call it from former. It takes kernel-param arg, so it can complain about "foo: bad input". Reuse ddparam_clamp_input(kp) in ddebug_sync_classbits(), to validate

[Intel-gfx] [PATCH v7c 19/24] dyndbg: add _DPRINTK_FLAGS_INCL_LOOKUP

2023-10-18 Thread Jim Cromie
dyndbg's dynamic prefixing (by +tmfsl flags) is needlessly expensive. When an enabled (with +p) pr_debug is called, _DPRINTK_FLAGS_INCL_ANY prefix decorations are sprintf'd into stack-mem for every call. This string (or part of it) could be cached once its 1st generated, and retrieved thereafter,

[Intel-gfx] [PATCH v7c 16/24] dyndbg-API: promote DYNDBG_CLASSMAP_PARAM to API

2023-10-18 Thread Jim Cromie
move the DYNDBG_CLASSMAP_PARAM macro from test-dynamic-debug.c into the header, and refine it, by distinguishing the 2 use cases: 1.DYNDBG_CLASSMAP_PARAM_REF for DRM, to pass in extern __drm_debug by name. dyndbg keeps bits in it, so drm can still use it as before 2.DYNDBG_CLASSMAP_PARAM

[Intel-gfx] [PATCH v7c 13/24] dyndbg-API: remove DD_CLASS_TYPE_(DISJOINT|LEVEL)_NAMES and code

2023-10-18 Thread Jim Cromie
Remove the NAMED class types; these 2 classmap types accept class names at the PARAM interface, for example: echo +DRM_UT_CORE,-DRM_UT_KMS > /sys/module/drm/parameters/debug_names The code works, but its only used by test-dynamic-debug, and wasn't asked for by anyone else, so simplify things fo

[Intel-gfx] [PATCH v7c 12/24] dyndbg: reduce verbose=3 messages in ddebug_add_module

2023-10-18 Thread Jim Cromie
The fn currently says "add-module", then "skipping" if the module has no prdbgs. Just check 1st and return quietly. no functional change Signed-off-by: Jim Cromie --- lib/dynamic_debug.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/lib/dynamic_debug.c b/lib/dynami

[Intel-gfx] [PATCH v7c 10/24] dyndbg: tighten ddebug_class_name() 1st arg type

2023-10-18 Thread Jim Cromie
Change function's 1st arg-type, and deref in the caller. The fn doesn't need any other fields in the struct. no functional change. Signed-off-by: Jim Cromie --- lib/dynamic_debug.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/dynamic_debug.c b/lib/dynamic_d

[Intel-gfx] [PATCH v7c 08/24] dyndbg: reduce verbose/debug clutter

2023-10-18 Thread Jim Cromie
currently, for verbose=3, these are logged (blank lines for clarity): dyndbg: query 0: "class DRM_UT_CORE +p" mod:* dyndbg: split into words: "class" "DRM_UT_CORE" "+p" dyndbg: op='+' dyndbg: flags=0x1 dyndbg: *flagsp=0x1 *maskp=0x dyndbg: parsed: func="" file="" module="" format="

[Intel-gfx] [PATCH v7c 09/24] dyndbg: silence debugs with no-change updates

2023-10-18 Thread Jim Cromie
check for actual changes before announcing them, declutter logs. Signed-off-by: Jim Cromie --- lib/dynamic_debug.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c index b0e11f6bfaa2..b07aab422604 100644 --- a/lib/dynamic_

[Intel-gfx] [PATCH v7c 06/24] dyndbg: split param_set_dyndbg_classes to module/wrapper fns

2023-10-18 Thread Jim Cromie
rename param_set_dyndbg_classes: add _module_ name & arg, old name is wrapper to new. New arg allows caller to specify that only one module is affected by a prdbgs update. Outer fn preserves kernel_param interface, passing NULL to inner fn. This selectivity will be used later to narrow the scope

[Intel-gfx] [PATCH v7c 05/24] dyndbg: ddebug_apply_class_bitmap - add module arg, select on it

2023-10-18 Thread Jim Cromie
Add query_module param to ddebug_apply_class_bitmap(). This allows its caller to update just one module, or all (as currently). We'll use this later to propagate drm.debug to each USEr as they're modprobed. No functional change. Signed-off-by: Jim Cromie --- after `modprobe i915`, heres the m

[Intel-gfx] [PATCH v7c 03/24] dyndbg: make ddebug_class_param union members same size

2023-10-18 Thread Jim Cromie
struct ddebug_class_param keeps a ref to the state-storage of the param, make both flavors use the same unsigned long under-type. ISTM this is simpler and safer. Signed-off-by: Jim Cromie --- include/linux/dynamic_debug.h | 2 +- lib/dynamic_debug.c | 2 +- 2 files changed, 2 insertion

[Intel-gfx] [PATCH v7c 02/24] dyndbg: reword "class unknown, " to "class:_UNKNOWN_"

2023-10-18 Thread Jim Cromie
This appears in the control-file to report an unknown class-name, which indicates that the class_id is not authorized, and dyndbg will ignore changes to it. Generally, this means that a DYNDBG_CLASSMAP_DEFINE or DYNDBG_CLASSMAP_USE is missing. But the word "unknown" appears in quite a few prdbg f

[Intel-gfx] [PATCH v7c 04/24] dyndbg: replace classmap list with a vector

2023-10-18 Thread Jim Cromie
Classmaps are stored/linked in a section/array, but are each added to the module's ddebug_table.maps list-head. This is unnecessary; even when ddebug_attach_classmap() is handling the builtin section (with classmaps for multiple builtin modules), its contents are ordered, so a module's possibly mu

[Intel-gfx] [PATCH v7c 01/24] test-dyndbg: fixup CLASSMAP usage error

2023-10-18 Thread Jim Cromie
more careful reading of test output reveals: lib/test_dynamic_debug.c:103 [test_dynamic_debug]do_cats =pmf "doing categories\n" lib/test_dynamic_debug.c:105 [test_dynamic_debug]do_cats =p "LOW msg\n" class:MID lib/test_dynamic_debug.c:106 [test_dynamic_debug]do_cats =p "MID msg\n" class:HI lib/t

[Intel-gfx] [PATCH v7c 00/24] fix DRM_USE_DYNAMIC_DEBUG=y regression

2023-10-18 Thread Jim Cromie
hi Jason, DRM-folk (v7c now with all checkpatch fixes) This patchest fixes the chicken-egg initialization problem in the 1st version of ddebug-class-maps, that DRM-CI uncovered. The root-problem was DECLARE_DYNDBG_CLASSMAP, which broke the K&R rule: "define once, refer many". In patch 14 it i

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5)

2023-10-18 Thread Andi Shyti
Hi Vinay, > Possible regressions > > • igt@gem_exec_nop@basic-series: > > □ shard-glk: PASS -> INCOMPLETE +1 other test incomplete > • igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: > > □ shard-dg2: PASS -> TIMEOUT > • igt@kms_cursor_crc@cursor-onscreen-

Re: [Intel-gfx] [PATCH v5 2/3] drm/i915/guc: Close deregister-context race against CT-loss

2023-10-18 Thread Gupta, Anshuman
> -Original Message- > From: Teres Alexis, Alan Previn > Sent: Saturday, October 14, 2023 6:34 AM > To: intel-gfx@lists.freedesktop.org > Cc: Teres Alexis, Alan Previn ; dri- > de...@lists.freedesktop.org; Vivi, Rodrigo ; Ceraolo > Spurio, Daniele ; Harrison, John C > ; Gupta, Anshuman

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Use kmap_local_page() in gem/i915_gem_execbuffer.c

2023-10-18 Thread Zhao Liu
Hi Rodrigo and Tvrtko, It seems this series is missed in v6.5. This work should not be forgotten. Let me rebase and refresh the version. Regards, Zhao On Mon, Apr 17, 2023 at 10:53:28AM -0400, Rodrigo Vivi wrote: > Date: Mon, 17 Apr 2023 10:53:28 -0400 > From: Rodrigo Vivi > Subject: Re: [PATCH

[Intel-gfx] [PATCH 4/4] drm/i915/mst: Always write CHICKEN_TRANS

2023-10-18 Thread Ville Syrjala
From: Ville Syrjälä Since we're asked to disable FECSTALL_DIS_DPTSTREAM_DPTTG when the transcoder is disabled it seems prudent to also clear it when enabliing the transcoder w/o FEC, just in case someone else left it enabled by mistake. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/dis

[Intel-gfx] [PATCH 3/4] drm/i915/mst: Clear ACT just before triggering payload allocation

2023-10-18 Thread Ville Syrjala
From: Ville Syrjälä Follow the bspec sequqnece more closely and clear ACT sent just before triggering the allocation. Can't see why we'd want to deviate from the spec sequence here. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- 1 file changed, 2 inserti

[Intel-gfx] [PATCH 2/4] drm/i915/mst: Disable transcoder before deleting the payload

2023-10-18 Thread Ville Syrjala
From: Ville Syrjälä Bspec tells us that we should disable the transcoder before deleting the payload. Looks like this has been reversed since MST support was added. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++-- 1 file changed, 2 insertions(+), 6 del

[Intel-gfx] [PATCH 1/4] drm/i915/mst: Swap TRANSCONF vs. FECSTALL_DIS_DPTSTREAM_DPTTG disable

2023-10-18 Thread Ville Syrjala
From: Ville Syrjälä The DP modeset sequence asks us to disable TRANSCONF before clearing the FECSTALL_DIS_DPTSTREAM_DPTTG bit, although we are still asked to wait for the transcoder to stop only after both steps have been done. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/inte

[Intel-gfx] [PATCH 0/4] drm/i915/mst: MST modeset sequence fixes

2023-10-18 Thread Ville Syrjala
From: Ville Syrjälä Fixes for issues I noticed while perusing the MST modeset sequence. Ville Syrjälä (4): drm/i915/mst: Swap TRANSCONF vs. FECSTALL_DIS_DPTSTREAM_DPTTG disable drm/i915/mst: Disable transcoder before deleting the payload drm/i915/mst: Clear ACT just before triggering paylo

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Ville Syrjälä
On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: > We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence > implementation. Lets drop i915_sw_fence usage from display code and > use dma_fence interfaces directly. > > For this purpose stack dma fences from related objec

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Ville Syrjälä
On Wed, Oct 18, 2023 at 05:23:00PM +0200, Maarten Lankhorst wrote: > > > On 2023-10-18 17:19, Ville Syrjälä wrote: > > On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: > >> We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence > >> implementation. Lets drop i915_sw_f

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Maarten Lankhorst
On 2023-10-18 17:19, Ville Syrjälä wrote: On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence implementation. Lets drop i915_sw_fence usage from display code and use dma_fence interfaces directly. For this purpo

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Ville Syrjälä
On Mon, Oct 16, 2023 at 11:08:03AM +0300, Jouni Högander wrote: > We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence > implementation. Lets drop i915_sw_fence usage from display code and > use dma_fence interfaces directly. > > For this purpose stack dma fences from related objec

Re: [Intel-gfx] [PATCH v3] drm/i915: Flush WC GGTT only on required platforms

2023-10-18 Thread Nirmoy Das
On 10/18/2023 3:00 PM, Andi Shyti wrote: Hi Nirmoy, gen8_ggtt_invalidate() is only needed for limited set of platforms where GGTT is mapped as WC. This was added as way to fix WC based GGTT in commit 0f9b91c754b7 ("drm/i915: flush system agent TLBs on SNB") and there are no reference in HW do

Re: [Intel-gfx] [PATCH v3 1/3] pwm: make it possible to apply pwm changes in atomic context

2023-10-18 Thread Hans de Goede
Hi Sean, On 10/17/23 11:17, Sean Young wrote: > Some drivers require sleeping, for example if the pwm device is connected > over i2c. The pwm-ir-tx requires precise timing, and sleeping causes havoc > with the generated IR signal when sleeping occurs. > > This patch makes it possible to use pwm w

Re: [Intel-gfx] [PATCH v12 3/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

2023-10-18 Thread Nirmoy Das
On 10/18/2023 3:24 PM, Andrzej Hajda wrote: On 20.09.2023 23:07, Jonathan Cavitt wrote: Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt > ---   drivers/gpu

Re: [Intel-gfx] [PATCH v12 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

2023-10-18 Thread Andrzej Hajda
On 20.09.2023 23:07, Jonathan Cavitt wrote: Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt Reviewed-by: Andrzej Hajda Regards Andrzej --- drivers/gpu/drm/i915/gt/intel_en

Re: [Intel-gfx] [PATCH v12 3/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

2023-10-18 Thread Andrzej Hajda
On 20.09.2023 23:07, Jonathan Cavitt wrote: Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt > --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + driv

[Intel-gfx] [PATCH] drm/i915: Add bigjoiner force enable option to debugfs

2023-10-18 Thread Stanislav Lisovskiy
For validation purposes, it might be useful to be able to force Bigjoiner mode, even if current dotclock/resolution do not require that. Lets add such to option to debugfs. v2: - Apparently intel_dp_need_bigjoiner can't be used, when debugfs entry is created so lets just check manually

Re: [Intel-gfx] [PATCH v12 2/4] drm/i915: Reserve some kernel space per vm

2023-10-18 Thread Andrzej Hajda
On 20.09.2023 23:07, Jonathan Cavitt wrote: Reserve two pages in each vm for kernel space to use for things such as workarounds. Signed-off-by: Jonathan Cavitt Suggested-by: Chris Wilson --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 +++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + 2 fil

Re: [Intel-gfx] [PATCH v12 1/4] drm/i915: Enable NULL PTE support for vm scratch

2023-10-18 Thread Andrzej Hajda
On 20.09.2023 23:07, Jonathan Cavitt wrote: Enable NULL PTE support for vm scratch pages. The use of NULL PTEs in teh vm scratch pages requires us to change how the i915 gem_contexts live selftest perform vm_isolation: instead of checking the scratch pages are isolated and don't affect each othe

Re: [Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

2023-10-18 Thread Maarten Lankhorst
Hey, Thanks, this version looks a lot better than duplicating drm_gem_plane_helper_prepare_fb functionality. :) Reviewed-by: Maarten Lankhorst On 2023-10-16 10:08, Jouni Högander wrote: We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence implementation. Lets drop i915_sw_fe

Re: [Intel-gfx] [PATCH v3] drm/i915: Flush WC GGTT only on required platforms

2023-10-18 Thread Andi Shyti
Hi Nirmoy, > > > gen8_ggtt_invalidate() is only needed for limited set of platforms > > > where GGTT is mapped as WC. This was added as way to fix WC based GGTT in > > > commit 0f9b91c754b7 ("drm/i915: flush system agent TLBs on SNB") and > > > there are no reference in HW docs that forces us to u

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL

2023-10-18 Thread Kahola, Mika
> -Original Message- > From: Borah, Chaitanya Kumar > Sent: Wednesday, October 18, 2023 2:36 PM > To: intel-gfx@lists.freedesktop.org > Cc: Kahola, Mika ; Syrjala, Ville > ; Sripada, Radhakrishna > ; Murthy, Arun R ; > Borah, Chaitanya Kumar > ; sta...@vger.kernel.org > Subject: [PATCH]

Re: [Intel-gfx] [rft, PATCH v1 0/2] drm/i915/dsi: An attempt to get rid of IOSF GPIO on VLV

2023-10-18 Thread Andy Shevchenko
On Wed, Oct 18, 2023 at 11:09:35AM +0200, Hans de Goede wrote: > On 10/18/23 07:10, Andy Shevchenko wrote: > > DSI code for VBT has a set of ugly GPIO hacks, one of which is direct > > talking to GPIO IP behind the actual driver's back. An attempt to fix > > that is here. > > > > If I understood c

Re: [Intel-gfx] [PATCH v3] drm/i915: Flush WC GGTT only on required platforms

2023-10-18 Thread Nirmoy Das
Hi Andi, On 10/18/2023 1:49 PM, Andi Shyti wrote: Hi Nirmoy, On Wed, Oct 18, 2023 at 11:38:15AM +0200, Nirmoy Das wrote: gen8_ggtt_invalidate() is only needed for limited set of platforms where GGTT is mapped as WC. This was added as way to fix WC based GGTT in commit 0f9b91c754b7 ("drm/i915:

Re: [Intel-gfx] [PATCH v3] drm/i915: Flush WC GGTT only on required platforms

2023-10-18 Thread Andi Shyti
Hi Nirmoy, On Wed, Oct 18, 2023 at 11:38:15AM +0200, Nirmoy Das wrote: > gen8_ggtt_invalidate() is only needed for limited set of platforms > where GGTT is mapped as WC. This was added as way to fix WC based GGTT in > commit 0f9b91c754b7 ("drm/i915: flush system agent TLBs on SNB") and > there are

[Intel-gfx] [PATCH] drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL

2023-10-18 Thread Chaitanya Kumar Borah
eDP specification supports HBR3 link rate since v1.4a. Moreover, C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. Cc: BSpec: 70073 74224 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_dp.c | 2

Re: [Intel-gfx] [PATCH v2] drm/i915: Prevent potential null-ptr-deref in engine_init_common

2023-10-18 Thread Nirmoy Das
This now merged. CI errors are unrelated. On 10/11/2023 2:25 PM, Nirmoy Das wrote: If measure_breadcrumb_dw() returns an error and bce isn't created, this commit ensures that intel_engine_destroy_pinned_context() is not called with a NULL bce. v2: Fix the subject s/UAF/null-ptr-deref(Jani) Fix

[Intel-gfx] [PATCH v4 0/2] display device info as a separate debugfs entry

2023-10-18 Thread Vinod Govindapillai
Expose the display device info as a separate debugfs entry to list out display device info and remove the same from i915_capabilities v2: rename the debugs entry to i915_display_capabilities and patch description changes v3: Exclude the patch to remove display device and runtime info from

[Intel-gfx] [PATCH v4 1/2] drm/i915/display: debugfs entry to list display capabilities

2023-10-18 Thread Vinod Govindapillai
Create a separate debugfs entry to list the display capabilities IGT can rely on this debugfs entry for tests that depend on display device and display runtime info for both xe and i915 drivers. v2: rename the entry to i915_display_capabilities (Chaitanya) Signed-off-by: Vinod Govindapillai ---

[Intel-gfx] [PATCH v4 2/2] drm/i915: remove display device info from i915 capabilities

2023-10-18 Thread Vinod Govindapillai
Display device and display runtime info is exposed as part of i915_display_capabilities debugfs entry. Remove this information from i915_ capabilities as it is now reduntant. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/i915_debugfs.c | 1 - 1 file changed, 1 deletion(-) diff --g

[Intel-gfx] [PATCH v3] drm/i915: Flush WC GGTT only on required platforms

2023-10-18 Thread Nirmoy Das
gen8_ggtt_invalidate() is only needed for limited set of platforms where GGTT is mapped as WC. This was added as way to fix WC based GGTT in commit 0f9b91c754b7 ("drm/i915: flush system agent TLBs on SNB") and there are no reference in HW docs that forces us to use this on non-WC backed GGTT. This

Re: [Intel-gfx] [rft, PATCH v1 0/2] drm/i915/dsi: An attempt to get rid of IOSF GPIO on VLV

2023-10-18 Thread Hans de Goede
Hi Andy, On 10/18/23 07:10, Andy Shevchenko wrote: > DSI code for VBT has a set of ugly GPIO hacks, one of which is direct > talking to GPIO IP behind the actual driver's back. An attempt to fix > that is here. > > If I understood correctly, my approach should work in the similar way as > the cur

[Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_14019821291

2023-10-18 Thread Dnyaneshwar Bhadane
This workaround is primarily implemented by the BIOS. However if the BIOS applies the workaround it will reserve a small piece of our DSM (which should be at the top, right below the WOPCM); we just need to keep that region reserved so that nothing else attempts to re-use it. Signed-off-by: Dnyan