== Series Details ==
Series: Enable Lunar Lake display (rev4)
URL : https://patchwork.freedesktop.org/series/122799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_122799v4
Summary
---
**SUCCESS**
== Series Details ==
Series: Enable Lunar Lake display (rev4)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable Lunar Lake display (rev4)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim checkpatch failed
356326aadadf drm/i915/xelpdp: Add XE_LPDP_FEATURES
4f94768bb2f6 drm/i915/lnl: Add display definitions
2e5186a89210 drm
== Series Details ==
Series: drm/i915/dsc: Fix pic_width readout (rev2)
URL : https://patchwork.freedesktop.org/series/123415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_123415v2
Summary
---
**S
From: Stanislav Lisovskiy
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename th
From: Stanislav Lisovskiy
Add a new CDCLK table for Lunar Lake.
v2:
- Remove mdclk from the table as it's not needed (Matt Roper)
- Update waveform values to the latest from spec (Matt Roper)
- Rename functions and calculation to match by pixel rate (Lucas)
v3: Keep only the table: as far
From: Juha-Pekka Heikkilä
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal
Signed-off-by: Juha-Pekka Heikkilä
Reviewed-by: Suraj Kandpal
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
1 file changed, 8 insertions(+)
d
From: Matt Roper
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Sr
From: Ravi Kumar Vodapalli
Add programming sequence for changes on CDCLK for Lunar Lake
platforms. It's mostly the same as MTL, but with some
additional programming for the squash and crawling steps when
a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for bxt_cdclk_cd2x_pipe(
From: Clint Taylor
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drive
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register lo
From: Ravi Kumar Vodapalli
Add Display Power Well for LNL platform. It's mostly the same as MTL
platform so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.
BSpec: 68886
Signed-off-by: Ravi Kumar Vod
Xe2_LPD also needs workaround 15010685871. While adding the new display
version, also re-order the condition to follow the convention of new
version first.
v2: Remove redundant HAS_CDCLK_SQUASH(). As the platform or IP version
needing the workaround are handpicked, there is no need to also
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa
Reviewed-by: M
Fix some whitespace issues for register definitions and keep the defines
for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with
the bit definition.
While at it add a TODO entry that those defines shouldn't be using an
implicit dev_priv.
Signed-off-by: Lucas De Marchi
---
.../gpu
From: Gustavo Sousa
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
p
From: Matt Roper
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.
From: Clint Taylor
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
Reviewed-by: Vinod Govindapillai
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/di
From: Gustavo Sousa
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge. The approach used by BXT/GLK can't be used here since
leaving it
From: Stanislav Lisovskiy
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do
From: Stanislav Lisovskiy
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we ar
XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer
using _PICK_EVEN_2RANGES() over PICK().
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 30 +++
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/d
The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD:
now they are all in a single range, with CH_A and CH_B coming right after
the USBC instances. Like was done when moving registers to PICA, use
a helper macro to remap the ch passed to an index that can be used to
calculate th
From: Gustavo Sousa
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
While at it, drop some trailing newlines.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/
From: Stanislav Lisovskiy
We now start calculating relative plane data rate for cursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Bspec: 68907
Signed-off-by: Stanislav Lisov
From: Stanislav Lisovskiy
Introduce correspondent definitions for choosing between CD2X CDCLK
and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
defined with PLL CDCLK as source, so simply set it. Also
skl_cdclk_decimal() shouldn't be set in CDCLK_CTL anymore, so skip it
for
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() fun
From: Clint Taylor
We use multiple variables for HDMI and DisplayPort to store the value of
DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
to just one in struct intel_digital_port. This is a preparation step for
future changes in D2D enable/disable sequence for xe2lpd th
Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/soc/intel_pch.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
v2: Move everything from xe_lpdp_display to the new macro and remove
the version setting: it's not needed with GMD_ID.
Signed-off-by: Lucas De Marchi
---
.../drm/
From: Balasubramani Vivekanandan
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Xe2 display is derived from the Xe_LPD+ IP; additional feature
deltas will be introduced in subsequent patches, so he
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
to work with multiple reg location and bitfield layout.
v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_EN
Cross posting this to the i915 and xe mailing lists. The basic platform
enabling for Lunar Lake is already applied in the xe driver[1].
This patch series adds the display support in the i915 driver, that is
going to be shared with xe.
Differently than v1, this v2 is based off drm-intel-next so we
From: Matt Roper
FBC is no longer limited by pipe: add the defines for pipes B and C that
will be used by platforms supporting FBC on such pipes.
Bspec: 68881, 68904
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/int
== Series Details ==
Series: i915/guc: Run busyness worker only if gt is awake (rev2)
URL : https://patchwork.freedesktop.org/series/123470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13622_full -> Patchwork_123470v2_full
> -Original Message-
> From: Kandpal, Suraj
> Sent: Tuesday, September 12, 2023 1:08 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Manna, Animesh
> ; Borah, Chaitanya Kumar
> ; Kandpal, Suraj
>
> Subject: [PATCH] drm/i915/dsc: Fix pic_width readout
>
> pic_width when w
== Series Details ==
Series: drm/tests: Fix incorrect argument in drm_test_mm_insert_range
URL : https://patchwork.freedesktop.org/series/123541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13622_full -> Patchwork_123541v1_full
===
== Series Details ==
Series: i915/guc: Run busyness worker only if gt is awake (rev2)
URL : https://patchwork.freedesktop.org/series/123470/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_123470v2
Summary
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend.
Only update stats if gt is awake. If not, intel_guc_busyness_park would
have already updated the stats. Note that we do not requeue the worker
if gt is not awake since intel_guc_busyness_unpark woul
On Mon, Sep 11, 2023 at 08:44:39AM -0700, Daniele Ceraolo Spurio wrote:
On 9/8/2023 10:16 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend. This is likely because some code is
getting a gt wakeref in the __gt_pa
== Series Details ==
Series: fix DRM_USE_DYNAMIC_DEBUG regression
URL : https://patchwork.freedesktop.org/series/123572/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/123572/revisions/1/mbox/ not
applied
Applying: test-dyndbg: fixup CLASSMAP usag
Lots of burn-in testing needed before signing, upstreaming.
NOTE: I set default Y to maximize testing by default.
Is there a better way to do this ?
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/Kconfi
Add a DRM_CLASSMAP_USE declaration to 2nd batch of helpers and *_drv.c
files. For drivers, add the decl just above the module's PARAMs,
since it identifies the "inherited" drm.debug param.
Note: with CONFIG_DRM_USE_DYNAMIC_DEBUG=y, a module not also declaring
DRM_CLASSMAP_USE will have its class'
Incorrectly spelled CFLAGS- failed to add -DDYNAMIC_DEBUG_MODULE,
which broke builds with:
CONFIG_DRM_USE_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_DYNAMIC_DEBUG=n
Also add subdir-ccflags so that all drivers pick up the addition.
Fixes: 84ec67288c10 ("drm_print: wrap drm_*_dbg in dyndbg
Reserve bit 7 to remember that a pr-debug callsite is/was:
- enabled, with +p
- wants a dynamic-prefix, with one+ of module:function:sourcfile
- was previously called
- was thus saved in the cache. NOT YET.
Its unclear whether any cache fetch would be faster than 2-3 field
fetches, but theres anot
Make the test-module buildable with just CONFIG_DYNAMIC_DEBUG_CORE;
add CFLAGS_$ofile defns to supply -DDYNAMIC_DEBUG_MODULE to cc.
Change the Kconfig entry to allow building with just _CORE, and fix
the help text.
Signed-off-by: Jim Cromie
---
lib/Kconfig.debug | 10 +-
lib/Makefile
Add some basic info on classmap usage and api
Signed-off-by: Jim Cromie
---
v5- adjustments per Randy Dunlap, me
---
.../admin-guide/dynamic-debug-howto.rst | 60 ++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/dynamic-debug-howto
move macro from test-dynamic-debug.c into header, and refine it.
Distinguish the 2 use cases of DYNDBG_CLASSMAP_PARAM*
1.DYNDBG_CLASSMAP_PARAM_REF
for DRM, to pass in extern __drm_debug by name.
dyndbg keeps bits in it, so drm can still use it as before
2.DYNDBG_CLASSMAP_PARAM
new us
dyndbg's dynamic prefixing (by +tmfsl flags) is needlessly expensive.
When an enabled (with +p) pr_debug is called, _DPRINTK_FLAGS_INCL_ANY
prefix decorations are sprintf'd into stack-mem for every call.
This string (or part of it) could be cached once its 1st generated,
and retreived thereafter,
Extract input validation code, from param_set_dyndbg_module_classes()
(the sys-node >handler) to new: ddebug_classparam_clamp_input(kp),
call it from former. It takes kernel-param arg, so it can complain
about "foo: bad input".
Reuse ddparam_clamp_input(kp) in ddebug_sync_classbits(),
to validate
DECLARE_DYNDBG_CLASSMAP() has a design error; it fails a basic K&R
rule: "define once, refer many times".
When DRM_USE_DYNAMIC_DEBUG=y, DECLARE_DYNDBG_CLASSMAP() is used across
DRM core & drivers; they all repeat the same classmap-defn args, which
must match for the modules to respond together whe
old_bits arg is currently a pointer to the input bits, but this could
allow inadvertent changes to the input by the fn. Disallow this.
And constify new_bits while here.
Signed-off-by: Jim Cromie
---
lib/dynamic_debug.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-
check for actual changes before announcing them, declutter logs.
Signed-off-by: Jim Cromie
---
lib/dynamic_debug.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
index f64d55d191ad..05c777dedf27 100644
--- a/lib/dynamic_
Add a for_each iterator to walk a counted vector member in a struct
(ie the box), and use it to replace 8 open-coded loops.
Signed-off-by: Jim Cromie
---
v5- parens-on-box-force-precedence
---
lib/dynamic_debug.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff -
Change function's 1st arg-type, and deref in the caller.
The fn doesn't need any other fields in the struct.
no functional change.
Signed-off-by: Jim Cromie
---
lib/dynamic_debug.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/dynamic_debug.c b/lib/dynamic_d
Remove the NAMED class types; these 2 classmap types accept class
names at the PARAM interface, for example:
echo +DRM_UT_CORE,-DRM_UT_KMS > /sys/module/drm/parameters/debug_names
The code works, but its only used by test-dynamic-debug, and wasn't
asked for by anyone else, so simplify things fo
Add query_module param to ddebug_apply_class_bitmap(). This allows
its caller to update just one module, or all (as currently). We'll
use this later to propagate drm.debug to each USEr as they're
modprobed.
No functional change.
Signed-off-by: Jim Cromie
---
after `modprobe i915`, heres the m
rename param_set_dyndbg_classes: add _module_ name & arg, old name is
wrapper to new. New arg allows caller to specify that only one module
is affected by a prdbgs update.
Outer fn preserves kernel_param interface, passing NULL to inner fn.
This selectivity will be used later to narrow the scope
currently, for verbose=3, these are logged (blank lines for clarity):
dyndbg: query 0: "class DRM_UT_CORE +p" mod:*
dyndbg: split into words: "class" "DRM_UT_CORE" "+p"
dyndbg: op='+'
dyndbg: flags=0x1
dyndbg: *flagsp=0x1 *maskp=0x
dyndbg: parsed: func="" file="" module="" format="
ARRAY_SIZE works here, since array decl is complete.
no functional change
Signed-off-by: Jim Cromie
---
include/linux/dynamic_debug.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
index b53217e4b711..8116d0a0
Classmaps are stored/linked in a section/array, but are each added to
the module's ddebug_table.maps list-head.
This is unnecessary; even when ddebug_attach_classmap() is handling
the builtin section (with classmaps for multiple builtin modules), its
contents are ordered, so a module's possibly mu
more careful reading of test output reveals:
lib/test_dynamic_debug.c:103 [test_dynamic_debug]do_cats =pmf "doing
categories\n"
lib/test_dynamic_debug.c:105 [test_dynamic_debug]do_cats =p "LOW msg\n"
class:MID
lib/test_dynamic_debug.c:106 [test_dynamic_debug]do_cats =p "MID msg\n" class:HI
lib/t
struct ddebug_class_param keeps a ref to the state-storage of the
param, make both flavors use the same unsigned long under-type.
ISTM this is simpler and safer.
Signed-off-by: Jim Cromie
---
include/linux/dynamic_debug.h | 2 +-
lib/dynamic_debug.c | 2 +-
2 files changed, 2 insertion
This series fixes the regression in DRM_USE_DYNAMIC_DEBUG=y
blame analysis: (all mine)
1. my early test scripts did a lot of 'modprobe $m $*',
with dyndbg=.. and debug=.. args
this obscured the lack of drm.debug -> drivers propagation
2. I broke K&R rule: "define once, refer many times".
This series fixes the regression in DRM_USE_DYNAMIC_DEBUG=y
blame analysis: (all mine)
1. my early test scripts did a lot of 'modprobe $m $*',
with dyndbg=.. and debug=.. args
this obscured the lack of drm.debug -> drivers propagation
2. I broke K&R rule: "define once, refer many times".
== Series Details ==
Series: drm/i915/dsc: Fix pic_width readout (rev2)
URL : https://patchwork.freedesktop.org/series/123415/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_123415v2
Summary
---
**F
== Series Details ==
Series: drm/i915/cx0: Add step for programming msgbus timer
URL : https://patchwork.freedesktop.org/series/123551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_123551v1
Summary
-
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 11/19] drm/i915/dsb: Don't use DSB to load the
> LUTs during full modeset
>
> From: Ville Syrjälä
>
> Usi
> -Original Message-
> From: Intel-gfx On Behalf Of Manna,
> Animesh
> Sent: Tuesday, July 11, 2023 11:13 AM
> To: Ville Syrjala ;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 10/19] drm/i915/dsb: Add support for non-
> posted DSB registers writes
>
>
>
> >
== Series Details ==
Series: drm/i915/cx0: Add step for programming msgbus timer
URL : https://patchwork.freedesktop.org/series/123551/
State : warning
== Summary ==
Error: dim checkpatch failed
93e020d2353e drm/i915/cx0: Add step for programming msgbus timer
-:210: WARNING:LONG_LINE: line len
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 09/19] drm/i915/dsb: Introduce
> intel_dsb_reg_write_masked()
>
> From: Ville Syrjälä
>
> Add a function
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 08/19] drm/i915/dsb: Introduce intel_dsb_noop()
>
> From: Ville Syrjälä
>
> Add a helper for emitting a n
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 05/19] drm/i915/dsb: Define the contents of
> some
> intstructions bit better
>
> From: Ville Syrjälä
>
On Mon, Sep 11, 2023 at 09:59:34PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:05:03AM +0300, Imre Deak wrote:
> > At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> > lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> > link bpp in this case,
== Series Details ==
Series: drm/tests: Fix incorrect argument in drm_test_mm_insert_range
URL : https://patchwork.freedesktop.org/series/123541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13622 -> Patchwork_123541v1
Sum
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits
>
> From: Ville Syrjälä
>
> Define all the DSB register bits so
On Mon, Sep 11, 2023 at 05:19:33PM +0530, Dnyaneshwar Bhadane wrote:
> This workaround has two different implementations,
> one for gen 12 to DG2 and another for DG2 and later.
Since this workaround is no longer relevant to any platforms DG2 or
later, I think we can drop the mention of those.
> I
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, June 8, 2023 5:16 PM
> To: Ville Syrjala ;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked
> register
> access
>
> On Tue, 06 Jun 2023, Ville
pic_width when written into the PPS register is divided by the no.
of vdsc instances first but the actual variable that we compare it
to does not change i.e vdsc_cfg->pic_width hence when reading the
register back for pic_width it needs to be multiplied by
num_vdsc_instances rather than being divid
On 9/10/23 19:11, Stephen Rothwell wrote:
> Hi all,
>
> Please do *not* include material destined for v6.7 in your linux-next
> included branches until *after* v6.6-rc1 has been released. Also,
> do *not* rebase your linu-next included branches onto v6.5.
>
> Changes since 20230908:
>
> Non-m
On Thu, Aug 24, 2023 at 11:05:03AM +0300, Imre Deak wrote:
> At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> link bpp in this case, until pipe B uses only up to 2 FDI lanes.
>
> For this instead of the
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
>
> From: Ville Syrjälä
>
> In order to reconcile seamless M/N upda
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 28 August 2023 11:12
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
>
> From: Ville Syrjälä
>
> In order to reconcile seamless M/N updates w
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/12] drm/i915: Extract
> intel_crtc_vblank_evade_scanlines()
>
> From: Ville Syrjälä
>
> Pull the vblank evasion sc
I didn't spot anything to nag about. Just hope that warning doesn't
become excessively noisy. These two patches are
Reviewed-by: Juha-Pekka Heikkila
On 4.9.2023 7.16, Ville Syrjala wrote:
From: Ville Syrjälä
The cursor hardware only does sync updates, and thus the hardware
will be scanning
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/12] drm/i915: Change
> intel_pipe_update_{start, end}() calling convention
>
> From: Ville Syrjälä
>
> We'll need
Hello Suraj,
> -Original Message-
> From: Kandpal, Suraj
> Sent: Friday, September 8, 2023 10:26 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Manna, Animesh
> ; Borah, Chaitanya Kumar
> ; Kandpal, Suraj
>
> Subject: [PATCH] drm/i915/dsc: Fix pic_width readout
>
> pic_wi
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless
> M/N changes
>
> From: Ville Syrjälä
>
> Make life less confusing by ma
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:34
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the
> pipe update critical section
>
> From: Ville Syrjälä
>
> Do the PSR u
On Tue, 08 Aug 2023, Allen Ballway wrote:
> Cybernet T10C cannot be dimmed without the backlight strobing. Create a
> new quirk to lock the minimum brightness to the highest supported value.
> This aligns the device with its behavior on Windows, which will not
> lower the brightness below maximum.
== Series Details ==
Series: drm/i915/gt: rename DBG() to GTT_TRACE()
URL : https://patchwork.freedesktop.org/series/123538/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13617_full -> Patchwork_123538v1_full
Summary
--
There was a recent update in the BSpec adding an extra step to the PLL
enable sequence, which is for programming the msgbus timer. Since we
also touch PHY registers during hw readout, let's do the programming
when starting a transaction rather than only when doing the PLL enable
sequence.
The BSpe
On Thu, 07 Sep 2023, "Kandpal, Suraj" wrote:
>> Subject: [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write
>> helpers
>
> Should be clarity here in the commit header
Thanks, fixed.
>
> With that fixed
> Reviewed-by: Suraj Kandpal
Thanks for the reviews, pushed the lot to drm-
== Series Details ==
Series: drm/i915: Added Wa_18022495364 (rev4)
URL : https://patchwork.freedesktop.org/series/123377/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13617_full -> Patchwork_123377v4_full
Summary
---
On 9/8/2023 10:16 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend. This is likely because some code is
getting a gt wakeref in the __gt_park path.
This possible root-cause doesn't seem plausible to me, because a
On Sun, 10 Sep 2023, Alexander Usyskin wrote:
> From: Jani Nikula
I'm almost certain I did not write this patch originally. The authorship
may have been changed accidentally along the way, but it's not mine.
BR,
Jani.
>
> Enable access to internal spi on DGFX devices via a child device.
> The
On Mon, 11 Sep 2023, Lucas De Marchi wrote:
> On Mon, Sep 11, 2023 at 03:33:05PM +0300, Jani Nikula wrote:
>>intel_gtt.h is indirectly included absolutely everywhere in the
>>driver. DBG() is too short a name. Rename it GTT_TRACE() after
>>GEM_TRACE().
>>
>>Signed-off-by: Jani Nikula
>>---
>> dri
On Mon, Sep 11, 2023 at 08:19:21AM +, Coelho, Luciano wrote:
> On Fri, 2023-09-08 at 08:25 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Apparently Acer Chromebook C740 (BDW-ULT) doesn't have the
> > eDP HPD line properly connected, and thus fails the new
> > HPD check during eD
On Mon, Sep 11, 2023 at 03:33:05PM +0300, Jani Nikula wrote:
intel_gtt.h is indirectly included absolutely everywhere in the
driver. DBG() is too short a name. Rename it GTT_TRACE() after
GEM_TRACE().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 36 ++---
Hi Dave and Daniel,
here are two more fixes that got stuck in drm-misc-next-fixes. As
discussed on IRC, they should go directly into drm-fixes.
Best regards
Thomas
drm-misc-next-fixes-2023-09-11:
Short summary of fixes pull:
* nouveau: Lockdep workaround
* fbdev/g364fb: Build fix
The followin
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