On Mon, Aug 28, 2023 at 04:01:38PM -0700, John Harrison wrote:
> On 8/23/2023 10:37, John Harrison wrote:
> > On 8/23/2023 09:00, Daniel Vetter wrote:
> > > On Tue, Aug 22, 2023 at 11:53:24AM -0700, John Harrison wrote:
> > > > On 8/11/2023 11:20, Zhanjun Dong wrote:
> > > > > This attempts to avoi
Am 05.09.23 um 16:28 schrieb Sui Jingfeng:
Hi,
On 2023/9/5 21:28, Christian König wrote:
2) Typically, those non-86 machines don't have a good UEFI firmware
support, which doesn't support select primary GPU as firmware
stage.
Even on x86, there are old UEFI firmwares which already mad
Am 05.09.23 um 15:30 schrieb suijingfeng:
Hi,
On 2023/9/5 18:45, Thomas Zimmermann wrote:
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above m
On Tue, 2023-09-05 at 19:49 -0700, Lucas De Marchi wrote:
> On Fri, Aug 25, 2023 at 11:16:34AM +0300, Luca Coelho wrote:
> > Hi,
> >
> > Here are four patches with some clean-ups in the code that handles the
> > max lane count of Type-C connections.
> >
> > This is done mostly in preparation for
On Tue, 2023-09-05 at 08:52 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf
> > Of Jouni
> > Högander
> > Sent: Monday, August 28, 2023 2:01 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH] drm/i915/psr: Add psr sink error
Hi,
On 2023/9/5 23:05, Thomas Zimmermann wrote:
You might have found a bug in the ast driver. Ast has means to detect
if the device has been POSTed and maybe do that. If this doesn't work
correctly, it needs a fix.
That sounds fine.
The bug is not a big deal, I'm just take it as an example
== Series Details ==
Series: drm/i915/mtl: Drop force_probe requirement
URL : https://patchwork.freedesktop.org/series/123303/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599_full -> Patchwork_123303v1_full
Summary
Hi,
On 2023/9/5 22:52, Alex Williamson wrote:
On Tue, 5 Sep 2023 03:57:15 +0800
Sui Jingfeng wrote:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the
Hi,
On 2023/9/5 23:05, Thomas Zimmermann wrote:
However, on modern Linux systems the primary display does not really
exist. 'Primary' is the device that is available via VGA, VESA or EFI.
I may miss the point, what do you means by choose the word "modern"?
Are you trying to tell me that X se
On Fri, Aug 25, 2023 at 11:16:34AM +0300, Luca Coelho wrote:
Hi,
Here are four patches with some clean-ups in the code that handles the
max lane count of Type-C connections.
This is done mostly in preparation for a new way to read the pin
assignments and lane count in future devices.
In v2:
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123306/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123306v1
Summary
---
**FAILUR
On 2023/9/5 23:05, Thomas Zimmermann wrote:
Hi
Am 05.09.23 um 15:30 schrieb suijingfeng:
Hi,
On 2023/9/5 18:45, Thomas Zimmermann wrote:
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over
which
one is prim
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123
URL : https://patchwork.freedesktop.org/series/123306/
State : warning
== Summary ==
Error: dim checkpatch failed
dfea335bb6dc drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
-:10: WARNING:BAD_SIGN_OFF: Co-developed
== Series Details ==
Series: drm/i915/dsc: cleanups
URL : https://patchwork.freedesktop.org/series/123291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599_full -> Patchwork_123291v1_full
Summary
---
**SUCCESS**
Hi,
On 2023/9/5 23:05, Thomas Zimmermann wrote:
However, on modern Linux systems the primary display does not really
exist.
No, it do exist. X server need to know which one is the primary GPU.
The '*' character at the of (4@0:0:0) PCI device is the Primary.
The '*' denote primary, see the l
== Series Details ==
Series: drm/i915/mtl: Drop force_probe requirement
URL : https://patchwork.freedesktop.org/series/123303/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123303v1
Summary
---
**S
== Series Details ==
Series: Drop caches per GT
URL : https://patchwork.freedesktop.org/series/123301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123301v1
Summary
---
**SUCCESS**
No regressio
== Series Details ==
Series: drm/i915/gt: Fix reservation address in ggtt_reserve_guc_top (rev2)
URL : https://patchwork.freedesktop.org/series/122970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599_full -> Patchwork_122970v2_full
=
== Series Details ==
Series: drm/i915/dsc: cleanups
URL : https://patchwork.freedesktop.org/series/123291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123291v1
Summary
---
**SUCCESS**
No regre
== Series Details ==
Series: PCI/VGA: Allowing the user to select the primary video adapter at boot
time (rev2)
URL : https://patchwork.freedesktop.org/series/123258/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/123258/revisions/2/mbox/ not
app
== Series Details ==
Series: drm/i915/dsc: cleanups
URL : https://patchwork.freedesktop.org/series/123291/
State : warning
== Summary ==
Error: dim checkpatch failed
485ced3f5bf8 drm/i915/dsc: improve clarify of the pps reg read/write helpers
21be8697dfba drm/i915/dsc: have intel_dsc_pps_read_
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion
URL : https://patchwork.freedesktop.org/series/123282/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123282v1
Summary
---
**F
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion
URL : https://patchwork.freedesktop.org/series/123282/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion
URL : https://patchwork.freedesktop.org/series/123282/
State : warning
== Summary ==
Error: dim checkpatch failed
f1aa77045061 Revert "drm/i915: Use uabi engines for the default engine map"
-:41: ERROR:BAD_SIGN_OFF: Unreco
== Series Details ==
Series: drm/i915/gt: Fix reservation address in ggtt_reserve_guc_top (rev2)
URL : https://patchwork.freedesktop.org/series/122970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_122970v2
===
== Series Details ==
Series: drm/i915/gt: Fix reservation address in ggtt_reserve_guc_top (rev2)
URL : https://patchwork.freedesktop.org/series/122970/
State : warning
== Summary ==
Error: dim checkpatch failed
824eede2a92d drm/i915/gt: Fix reservation address in ggtt_reserve_guc_top
-:14: WAR
== Series Details ==
Series: drm/i915/tc: some clean-ups in max lane count handling code (rev5)
URL : https://patchwork.freedesktop.org/series/120980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599_full -> Patchwork_120980v5_full
==
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev2)
URL : https://patchwork.freedesktop.org/series/123182/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123182v2
Summary
---
*
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev2)
URL : https://patchwork.freedesktop.org/series/123182/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev2)
URL : https://patchwork.freedesktop.org/series/123182/
State : warning
== Summary ==
Error: dim checkpatch failed
f68c376c1650 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
-:10: WARNING:BAD_SIGN_OFF: Co-de
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_94470v7
Summary
---
**FAIL
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim checkpatch failed
df46f8fc2937 drm/panelreplay: dpcd register definition for panelreplay
a4cfe5eb05ad drm/i915/psr: Move psr spe
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/tc: some clean-ups in max lane count handling code (rev5)
URL : https://patchwork.freedesktop.org/series/120980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_120980v5
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Co-developed-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +
d
Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.
Signed-off-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 8 i
Meteorlake has been very usable for a while now, all of uapi changes
related to fundamental platform usage have been finalized and all
required firmware blobs are available. Recent CI results have also
been healthy, so we're ready to drop the force_probe requirement and
enable the platform by defau
When the user sends the drop caches command through the debugfs
interface, do it on all the GT's, rather than just the root GT.
Based on a patch by Tvrtko.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 --
1 file changed, 12 insertion
In preparation for multi-gt cache flushing debugfs interface,
split the cache dropping function and gt idling.
Based on a patch by Tvrtko.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 +
1 file changed, 24 insertions(+),
Hi,
this bit of code escaped the multi-gt wave from a couple of years
ago.
Andi
Andi Shyti (2):
drm/i915: Split gt cache flushing and gt idling functions
drm/i915: When asked to drop the cache, do it per GT
drivers/gpu/drm/i915/i915_debugfs.c | 44 +
1 file chan
Hi,
On 2023/9/5 13:50, Christian König wrote:
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over
which one
is primary at boot time.
Question is why is that useful? Should we give users the ability to
control th
Use the register helper macros for PPS0 and PPS1 register contents.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +--
.../gpu/drm/i915/display/intel_vdsc_regs.h| 27 ++-
2 files changed, 22 in
Improve clarity by specifying the PPS number in the register content
macros. It's easier to notice if macros are being used for the wrong
register.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
Probably easiest to review by applying and using 'git show --word-diff'
---
Unify comments to be the simple "PPS n" instead of all sorts of
variants.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 56 +--
.../gpu/drm/i915/display/intel_vdsc_regs.h| 29 +-
2 files changed,
Make the function name conform to existing style better.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/inte
Register read functions usually return the value instead of passing via
pointer parameters. Return the multiple register verification results
via a pointer parameter, which can also be NULL to skip the extra
checks.
Make the name conform to existing style better while at it.
Cc: Suraj Kandpal
Cc
Register read functions usually return the value instead of passing via
pointer parameters. The calling code becomes easier to read.
Make the name conform to existing style better while at it.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/int
Jani Nikula (8):
drm/i915/dsc: improve clarify of the pps reg read/write helpers
drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value
drm/i915/dsc: have intel_dsc_pps_read() return the value
drm/i915/dsc: rename pps write to intel_dsc_pps_write()
drm/i915/dsc: drop redund
Directly assign the values instead of first assigning 0 and then |= the
values.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 43 ---
1 file changed, 15 insertions(+), 28 deletions(-)
diff --git a/drivers/gp
Make it clear what's the number of vdsc per pipe, and what's the number
of registers to grab. Have intel_dsc_get_pps_reg() return the registers
it knows even if the requested amount is bigger.
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/inte
On Wed, 6 Sep 2023 00:21:09 +0800
suijingfeng wrote:
> Hi,
>
> On 2023/9/5 22:52, Alex Williamson wrote:
> > On Tue, 5 Sep 2023 03:57:15 +0800
> > Sui Jingfeng wrote:
> >
> >> From: Sui Jingfeng
> >>
> >> On a machine with multiple GPUs, a Linux user has no control over which
> >> one is pr
Hi,
On 2023/9/5 22:52, Alex Williamson wrote:
On Tue, 5 Sep 2023 03:57:15 +0800
Sui Jingfeng wrote:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the -
On 2023/9/5 18:49, Thomas Zimmermann wrote:
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the ->be_primary
Hi
Am 05.09.23 um 15:30 schrieb suijingfeng:
Hi,
On 2023/9/5 18:45, Thomas Zimmermann wrote:
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve abo
On Tue, 5 Sep 2023 03:57:15 +0800
Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> On a machine with multiple GPUs, a Linux user has no control over which
> one is primary at boot time. This series tries to solve above mentioned
> problem by introduced the ->be_primary() function stub. The specifi
Hi,
On 2023/9/5 21:28, Christian König wrote:
2) Typically, those non-86 machines don't have a good UEFI firmware
support, which doesn't support select primary GPU as firmware
stage.
Even on x86, there are old UEFI firmwares which already made
undesired
decision for you.
3) This
Commit 1ec23ed7126e ("drm/i915: Use uabi engines for the default engine
map") switched from using for_each_engine() to for_each_uabi_engine() to
iterate over the user engines. While this seems to be a sensible change,
it's only safe to do when the engines are actually chained using the
rb-tree stru
Commit 1ec23ed7126e ("drm/i915: Use uabi engines for the default engine
map") introduced a bug regarding engine iteration in default_engines()
as the rb tree isn't set up yet that early during driver initialization.
This triggered a sanity check we have in our grsecurity kernels, fixed
by reverting
Chaining user engines happens in multiple passes during driver
initialization, mutating its type along the way. It starts off with a
simple lock-less linked list (struct llist_node/head) populated by
intel_engine_add_user() which later gets sorted and converted to an
intermediate regular list (stru
There is an assertion in ggtt_reserve_guc_top that the global GTT
is of size at least GUC_GGTT_TOP, which is not the case on a 32-bit
platform; see commit 562d55d991b39ce376c492df2f7890fd6a541ffc
("drm/i915/bdw: Only use 2g GGTT for 32b platforms"). If GEM_BUG_ON
is enabled, this triggers a BUG();
On Thu, 31 Aug 2023 15:49:28 -0700
"Ceraolo Spurio, Daniele" wrote:
> On 8/25/2023 7:33 AM, Javier Pello wrote:
> > There is an assertion in ggtt_reserve_guc_top that the global GTT
> > is of size at least GUC_GGTT_TOP, which is not the case on a 32-bit
> > platform; see commit 562d55d991b39ce376
Hi,
On 2023/9/5 18:45, Thomas Zimmermann wrote:
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
If anything, the primary graphic
Am 05.09.23 um 12:38 schrieb Jani Nikula:
On Tue, 05 Sep 2023, Sui Jingfeng wrote:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the ->be_primary() functi
On Tue, Sep 05, 2023 at 02:33:04PM +0200, Sebastian Wick wrote:
> On Tue, Sep 05, 2023 at 02:33:26PM +0300, Pekka Paalanen wrote:
> > On Mon, 4 Sep 2023 14:29:56 +
> > "Shankar, Uma" wrote:
> >
> > > > -Original Message-
> > > > From: Sebastian Wick
> > > > Sent: Thursday, August 31,
On Tue, Sep 05, 2023 at 02:33:26PM +0300, Pekka Paalanen wrote:
> On Mon, 4 Sep 2023 14:29:56 +
> "Shankar, Uma" wrote:
>
> > > -Original Message-
> > > From: Sebastian Wick
> > > Sent: Thursday, August 31, 2023 2:46 AM
> > > To: Shankar, Uma
> > > Cc: Harry Wentland ; intel-
> > >
Hi Animesh,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm
On Mon, 4 Sep 2023 14:29:56 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Sebastian Wick
> > Sent: Thursday, August 31, 2023 2:46 AM
> > To: Shankar, Uma
> > Cc: Harry Wentland ; intel-
> > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; wayland-
> > de...@li
On Mon, 4 Sep 2023 14:10:05 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: dri-devel On Behalf Of Pekka
> > Paalanen
> > Sent: Wednesday, August 30, 2023 6:30 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> > ; dri-de...@lists.free
On Mon, 4 Sep 2023 13:44:49 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: dri-devel On Behalf Of Pekka
> > Paalanen
> > Sent: Wednesday, August 30, 2023 5:59 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> > ; dri-de...@lists.free
Hi Animesh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the ->be_primary() function stub. The specific
device drivers c
Hi
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
If anything, the primary graphics adapter is the one initialized by the
firmware.
On Tue, 05 Sep 2023, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> On a machine with multiple GPUs, a Linux user has no control over which
> one is primary at boot time. This series tries to solve above mentioned
> problem by introduced the ->be_primary() function stub. The specific
> device drive
> Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display: Configure and initialize
> HDMI
> audio capabilities
>
> Initialize the source audio capabilities in the crtc_state property, setting
> them to
Nit: maybe mention the above as intel_crtc_state rather than crtc_state
property as
property usua
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Monday, August 28, 2023 2:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/psr: Add psr sink error status into sink
> status debugfs
>
> Normally PSR errors detected by the pa
Add debugfs support which will print source and sink status
per connector basis.
Cc: Jouni Högander
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 70
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/displ
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Bspec: 1407940617
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jo
Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff
Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.
v1: Initial version.
v2:
- Set source_panel_replay_support flag under
From: Jouni Högander
This patch is preparing adding panel replay specific dpcd init.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 39 +---
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.
Add DPCD register definition for discovering, enabling and
checking status of panel replay of the sink.
Cc: Jouni Högander
Signed-off-by: Animesh Manna
---
include/drm/display/drm_dp.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches added on top of
existing psr framework to enable full-screen live active frame
update mode of panel replay. Panel replay also can be enabled
in selective update mode whic
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