On Wed, Aug 30, 2023 at 06:51:25AM +, Golani, Mitulkumar Ajitkumar wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: 30 August 2023 10:47
> > To: Golani, Mitulkumar Ajitkumar
> >
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 5
Hi Ville,
> -Original Message-
> From: Ville Syrjälä
> Sent: 30 August 2023 10:47
> To: Golani, Mitulkumar Ajitkumar
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> behaviour
>
> On Tue, Aug 29, 2023 at 01:48:18PM +
On Tue, Aug 29, 2023 at 09:04:28AM -0700, Matt Roper wrote:
> On Tue, Aug 29, 2023 at 06:50:02AM -0700, Govindapillai, Vinod wrote:
> > On Mon, 2023-08-28 at 17:16 -0700, Matt Roper wrote:
> > > On Mon, Aug 28, 2023 at 09:20:34AM +0300, Vinod Govindapillai wrote:
> > > > In LNL onwards, FBC can be
On Tue, Aug 29, 2023 at 01:34:56PM +, Govindapillai, Vinod wrote:
> On Tue, 2023-08-29 at 10:50 +0300, Ville Syrjälä wrote:
> > On Mon, Aug 28, 2023 at 09:20:34AM +0300, Vinod Govindapillai wrote:
> > > In LNL onwards, FBC can be associated to the first three planes.
> > > The FBC will be enabl
On Tue, Aug 29, 2023 at 01:48:18PM +, Golani, Mitulkumar Ajitkumar wrote:
> Hi Ville,
>
> Thanks for the inputs.
>
> I encountered an interesting observation while validating the changes.
> In scenarios where VRR is by default ON from the panel, I noticed that during
> the first-time enabli
On Tue, Aug 29, 2023 at 07:58:18AM -0700, Manasi Navare wrote:
> On Tue, Aug 29, 2023 at 1:26 AM Ville Syrjälä
> wrote:
> >
> > On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote:
> > > On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> > > wrote:
> > > >
> > > > From: Ville Syrjälä
> >
== Series Details ==
Series: drm/i915/dg2: Add support for new DG2-G12 revid 0x1
URL : https://patchwork.freedesktop.org/series/123014/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13573_full -> Patchwork_123014v1_full
Sum
On Tue, Aug 29, 2023 at 07:29:45PM +0530, Swati Sharma wrote:
> The bspec has been updated with a new revision 0x1 that
> translates to A1 GT stepping and C0 display stepping.
>
> Bspec: 44477
>
> Signed-off-by: Swati Sharma
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_step.c |
On Tue, Aug 29, 2023 at 12:44:35PM +0300, Jouni Högander wrote:
> According to recent Bspec Wa 14015648006 has to be applied for all display
> 14 steppings.
>
> Bspec: 66624
>
> Signed-off-by: Jouni Högander
Reviewed-by: Matt Roper
and applied to drm-intel-next. Thanks for the patch.
Matt
== Series Details ==
Series: drm/i915/gt: Wait longer for tasks in migrate selftest (rev2)
URL : https://patchwork.freedesktop.org/series/122984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573_full -> Patchwork_122984v2_full
===
On Wed, Aug 23, 2023 at 10:07:36AM -0700, Lucas De Marchi wrote:
From: Stanislav Lisovskiy
mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
hw to be poked, so we must serialize the global state in that case.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Ma
On Thu, Aug 24, 2023 at 04:54:57PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:34AM -0700, Lucas De Marchi wrote:
From: Ravi Kumar Vodapalli
Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform.
CDCLK frequency change sequence is different for
== Series Details ==
Series: drm/i915: Populate connector->ddc always
URL : https://patchwork.freedesktop.org/series/123006/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13573_full -> Patchwork_123006v1_full
Summary
--
== Series Details ==
Series: Add Support for Plane Color Pipeline
URL : https://patchwork.freedesktop.org/series/123023/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13574 -> Patchwork_123023v1
Summary
---
**FAILURE
== Series Details ==
Series: Add Support for Plane Color Pipeline
URL : https://patchwork.freedesktop.org/series/123023/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add Support for Plane Color Pipeline
URL : https://patchwork.freedesktop.org/series/123023/
State : warning
== Summary ==
Error: dim checkpatch failed
5b6e9790b630 drm/doc/rfc: Add RFC document for proposed Plane Color Pipeline
-:14: WARNING:FILE_PATH_CHANGES: adde
== Series Details ==
Series: drm/i915/psr: Apply Wa_14015648006 for all display 14 steppings
URL : https://patchwork.freedesktop.org/series/122999/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573_full -> Patchwork_122999v1_full
=
On 2023-08-29 12:03, Uma Shankar wrote:
Add the documentation for the new proposed Plane Color Pipeline.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/rfc/plane_color_pipeline.rst | 394 ++
1 f
+CC Naseer and Chris, FYI
See https://patchwork.freedesktop.org/series/123024/ for whole series.
On 2023-08-29 12:03, Uma Shankar wrote:
Introduction
Modern hardwares have various color processing capabilities both
at pre-blending and post-blending phases in the color pipeline.
Th
On 2023-08-29 11:03, Jani Nikula wrote:
On Tue, 29 Aug 2023, Jani Nikula wrote:
On Tue, 29 Aug 2023, Alex Deucher wrote:
On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
On Wed, 23 Aug 2023, Jani Nikula wrote:
On Tue, 22 Aug 2023, Alex Hung wrote:
On 2023-08-22 06:01, Jani Nikula
On Wed, Aug 23, 2023 at 03:01:37PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
From: Stanislav Lisovskiy
Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source.
Signed-off-by: Stanislav Lisovskiy
Signed-
On Tue, Aug 29, 2023 at 02:35:34PM -0400, James Zhu wrote:
>
> On 2023-08-29 14:33, Matthew Wilcox wrote:
> > On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
> > > > > > @@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
> > > > > > unregister_chrdev(DRM_MAJOR, "drm");
>
On 2023-08-29 14:33, Matthew Wilcox wrote:
On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
@@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
unregister_chrdev(DRM_MAJOR, "drm");
debugfs_remove(drm_debugfs_root);
drm_sysfs_destroy();
- idr_destroy(&d
On Tue, Aug 29, 2023 at 01:34:22PM -0400, James Zhu wrote:
> > > > @@ -1067,7 +1055,7 @@ static void drm_core_exit(void)
> > > > unregister_chrdev(DRM_MAJOR, "drm");
> > > > debugfs_remove(drm_debugfs_root);
> > > > drm_sysfs_destroy();
> > > > - idr_destroy(&drm_minor
On Wed, Aug 23, 2023 at 02:14:39PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
From: Stanislav Lisovskiy
In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
always 2 times CDCLK. Now we might afford lower CDCLK, while having
hi
On 2023-08-28 17:08, Michał Winiarski wrote:
On Fri, Aug 25, 2023 at 12:59:26PM -0400, James Zhu wrote:
On 2023-07-24 17:14, Michał Winiarski wrote:
IDR is deprecated, and since XArray manages its own state with internal
locking, it simplifies the locking on DRM side.
Additionally, don't use
On Mon, Aug 28, 2023 at 08:16:35PM +0200, Nirmoy Das wrote:
>
> On 8/28/2023 8:34 AM, Tejas Upadhyay wrote:
> > Now this workaround is permanent workaround on MTL and DG2,
> > earlier we used to apply on MTL A0 step only.
> > VLK-45480
>
> Please remove the internal VLK reference. Otherwise this
On Tue, 29 Aug 2023, Jani Nikula wrote:
> On Tue, 29 Aug 2023, Alex Deucher wrote:
>> On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
>>>
>>> On Wed, 23 Aug 2023, Jani Nikula wrote:
>>> > On Tue, 22 Aug 2023, Alex Hung wrote:
>>> >> On 2023-08-22 06:01, Jani Nikula wrote:
>>> >>> Over the p
== Series Details ==
Series: drm/i915/dg2: Add support for new DG2-G12 revid 0x1
URL : https://patchwork.freedesktop.org/series/123014/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573 -> Patchwork_123014v1
Summary
-
On Tue, 29 Aug 2023, Alex Deucher wrote:
> On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
>>
>> On Wed, 23 Aug 2023, Jani Nikula wrote:
>> > On Tue, 22 Aug 2023, Alex Hung wrote:
>> >> On 2023-08-22 06:01, Jani Nikula wrote:
>> >>> Over the past years I've been trying to unify the override
== Series Details ==
Series: drm/i915/gt: Wait longer for tasks in migrate selftest (rev2)
URL : https://patchwork.freedesktop.org/series/122984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573 -> Patchwork_122984v2
Sum
On Tue, Aug 29, 2023 at 06:50:02AM -0700, Govindapillai, Vinod wrote:
> On Mon, 2023-08-28 at 17:16 -0700, Matt Roper wrote:
> > On Mon, Aug 28, 2023 at 09:20:34AM +0300, Vinod Govindapillai wrote:
> > > In LNL onwards, FBC can be associated to the first three planes.
> >
> > The title of this pat
From: Chaitanya Kumar Borah
Initialize and expose all plane color features.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 1 -
drivers/gpu/drm/i915/display/skl_universal_plane.c | 1 +
2 f
From: Chaitanya Kumar Borah
This patch is to demonstrate how a pipeline can be added.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++
drivers/gpu/drm/drm_atomic_uapi.c | 15 +
Implement plane CSC for Xe_LPD.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c| 86 +++
drivers/gpu/drm/i915/display/intel_color.h| 1 +
.../drm/i915/display/skl_univ
From: Chaitanya Kumar Borah
This is an example of how vendor specific color operation could be
supported by the uapi
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c| 42 ---
driver
Extract the LUT and program plane pre-csc registers.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 120 +
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files ch
Add macros to define Plane Post CSC registers
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i
Extract the LUT and program plane post csc registers.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 95 +-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 8
drivers
From: Chaitanya Kumar Borah
Create and attach "SET_COLOR_PIPELINE" property to planes.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
Add callbacks for color plane operations.
load_plane_luts: used to load pre/post csc luts
load_plane_csc_matrix: used to load csc matrix
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 6 ++
Register color callbacks for ADL and beyond. While we have to register
new callbacks for pre-blending color operations, re-use callbacks for
post-blend operations.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/di
Add macros to define Plane Degamma registers
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 49 +
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i9
Extended glk_plane_color_ctl to have plane color checks. This helps
enabling the csc, degamma or gamma block based on user inputs.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13
From: Chaitanya Kumar Borah
Add supported plane color pipelines. To represent all
hardware blocks in their inactive state, we introduce a pipeline
called "no color pipeline" which is the default pipeline.
Add respective color pipelines for SDR and HDR planes. Create and
attach plane enum property
From: Chaitanya Kumar Borah
Add LUT ranges for color blocks in SDR planes. Userspace can
parse through this information to generate proper LUT data for
respective hardware blocks. It will be exposed to the user space
by the color pipeline.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
From: Chaitanya Kumar Borah
Create a helper function to add details about LUT ranges that HDR
planes can support. Userspace can parse through this information
to generate proper LUT data for respective hardware blocks. It will
be exposed to the user space by the color pipeline.
Co-developed-by:
SDR planes provides programmable color hardware blocks for
Pre-CSC and Post-CSC operations. Add a color pipeline to
expose these capabilities.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c |
Add color pipeline for HDR planes. It consists of the following
hardware blocks.
* Pre-CSC : This block can used to linearize the input frame buffer data.
The linear data then can be further acted on by the following
color hardware blocks in the display hardware pipeline
From: Chaitanya Kumar Borah
This patch manages the references for color blobs.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_state_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/dr
Add lut range information for HDR planes. This is used to
hint the userspace what kind of LUT values are needed by
the hardware block. Pre-CSC and Post-CSC blocks have
different lut ranges for HDR planes.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by:
Add lut range information for SDR planes. This is used to
hint the userspace what kind of LUT values are needed by
the hardware block. Pre-CSC and Post-CSC blocks have similar
lut range for HDR planes.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma
Add a new structure drm_plane_color to plane state. It consists
of blobs with data needed for respective color HW blocks.
Currently defining below blobs
pre-csc: can be used to linearize the input frame buffer data.
csc: used for color space conversion.
post-csc: can be used non-linearize
From: Chaitanya Kumar Borah
When a pipeline switch is requested by user, driver resets
blobs for all the hardware blocks to get to clean state. These
are then populated with the new blob id's as programmed by user.
For the already enabled hardware blocks, if the user does not
add entry in the new
From: Chaitanya Kumar Borah
User can disable the color pipeline entirely, thereby
disabling all the color hardware blocks in the pipeline.
User should set NULL as the blob id and invoke SET_COLOR_PIPELINE
property. Driver will disable all the color hardware blocks by
updating respective blob id'
From: Chaitanya Kumar Borah
Replace the color operation blobs depending on the values sent by
userspace.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_uapi.c | 97 +++
1 file changed, 97
Add color lut range structure which is to be used to advertize
the capabilities of pre-csc/post-csc color operation blocks.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
include/uapi/drm/drm_mode.h | 77 ++
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Sig
Add a new plane blob property "SET_COLOR_PIPELINE" using
which the user can select a color pipeline and send data
for corresponding hardware blocks.
Once the user space decides on a color pipeline, it can
set the pipeline and corresponding data for the hardware
blocks within the pipeline.
Co-deve
Add structures using which user space can set a color pipeline it
desires. The patch introduces two structures
struct drm_color_op_data represents data to be passed
onto individual color hardware blocks.
struct drm_color_pipeline represents the aggregate of drm_color_op_data
structures to program
From: Chaitanya Kumar Borah
Create a helper function to add a color pipeline for a plane.
Color pipeline is an array of struct drm_color_op which represent
a possible logical combination of color operations. Color
operations can be re-arranged, substracted or added to create
distinct color pipeli
From: Chaitanya Kumar Borah
Each hardware plane can consist of multiple color hardware blocks.
These hardware blocks are defined by a color pipeline. In case,
hardware blocks can be re-arranged/muxed a distinct pipeline can
be defined to represent the same.
Introduce a new enum plane property "G
From: Chaitanya Kumar Borah
Each Color Hardware block will be represented uniquely
in the color pipeline. Define the structure to represent
the same.
These color operations will form the building blocks of
a color pipeline which best represents the underlying
Hardware. Color operations can be re
Add the documentation for the new proposed Plane Color Pipeline.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/rfc/plane_color_pipeline.rst | 394 ++
1 file changed, 394 insertions(+)
create mode 100
Introduction
Modern hardwares have various color processing capabilities both
at pre-blending and post-blending phases in the color pipeline.
The current drm implementation exposes only the post-blending
color hardware blocks. Support for pre-blending hardware is missing.
There are mu
On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
>
> On Wed, 23 Aug 2023, Jani Nikula wrote:
> > On Tue, 22 Aug 2023, Alex Hung wrote:
> >> On 2023-08-22 06:01, Jani Nikula wrote:
> >>> Over the past years I've been trying to unify the override and firmware
> >>> EDID handling as well as EDID
On Mon, 28 Aug 2023, Gustavo Sousa wrote:
>>> +#define INTEL_CX0_MSGBUS_TIMER_VAL_MAX0x200
Either make this 0x200U (for unsigned)...
>>> +
>>> bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
>>> {
>>> if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C
On Tue, Aug 29, 2023 at 1:26 AM Ville Syrjälä
wrote:
>
> On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote:
> > On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> > wrote:
> > >
> > > From: Ville Syrjälä
> > >
> > > In order to reconcile seamless M/N updates with VRR we'll
> > > need t
On Tue, Aug 29, 2023 at 8:56 AM Gustavo Sousa wrote:
>
> The following changes since commit 659dfe6435b77a075d9896ff34250bcaab55d75b:
>
> Merge tag 'amd-2023-08-25' of https://gitlab.freedesktop.org/drm/firmware
> (2023-08-29 07:27:29 -0400)
>
> are available in the Git repository at:
>
> git
The bspec has been updated with a new revision 0x1 that
translates to A1 GT stepping and C0 display stepping.
Bspec: 44477
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_step.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i
On Mon, 2023-08-28 at 17:16 -0700, Matt Roper wrote:
> On Mon, Aug 28, 2023 at 09:20:34AM +0300, Vinod Govindapillai wrote:
> > In LNL onwards, FBC can be associated to the first three planes.
>
> The title of this patch shouldn't say "any plane" when the reality is
> that only the first three sup
== Series Details ==
Series: drm/i915: Populate connector->ddc always
URL : https://patchwork.freedesktop.org/series/123006/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573 -> Patchwork_123006v1
Summary
---
**SUC
Hi Ville,
Thanks for the inputs.
I encountered an interesting observation while validating the changes.
In scenarios where VRR is by default ON from the panel, I noticed that during
the first-time enabling of VRR, a full modeset is required due to a fastset
requirement mismatch, as indicated i
== Series Details ==
Series: drm/i915: Populate connector->ddc always
URL : https://patchwork.freedesktop.org/series/123006/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:1
== Series Details ==
Series: drm/i915: Populate connector->ddc always
URL : https://patchwork.freedesktop.org/series/123006/
State : warning
== Summary ==
Error: dim checkpatch failed
29067f60239e drm: Reorder drm_sysfs_connector_remove() vs.
drm_debugfs_connector_remove()
fe48fc1d50c3 drm/sy
On Tue, 2023-08-29 at 10:50 +0300, Ville Syrjälä wrote:
> On Mon, Aug 28, 2023 at 09:20:34AM +0300, Vinod Govindapillai wrote:
> > In LNL onwards, FBC can be associated to the first three planes.
> > The FBC will be enabled for first FBC capable visible plane
> > until the userspace can select one
Hi Tejas,
On Mon, Aug 28, 2023 at 12:04:50PM +0530, Tejas Upadhyay wrote:
> Now this workaround is permanent workaround on MTL and DG2,
> earlier we used to apply on MTL A0 step only.
> VLK-45480
>
> Fixes: d922b80b1010 ("drm/i915/gt: Add workaround 14016712196")
> Signed-off-by: Tejas Upadhyay
== Series Details ==
Series: drm/i915/psr: Apply Wa_14015648006 for all display 14 steppings
URL : https://patchwork.freedesktop.org/series/122999/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13573 -> Patchwork_122999v1
S
The following changes since commit 659dfe6435b77a075d9896ff34250bcaab55d75b:
Merge tag 'amd-2023-08-25' of https://gitlab.freedesktop.org/drm/firmware
(2023-08-29 07:27:29 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dmc-mtl_2.16
for you to
On Mon, 2023-08-28 at 16:58 -0700, Matt Roper wrote:
> On Mon, Aug 28, 2023 at 09:20:32AM +0300, Vinod Govindapillai wrote:
> > FBC restriction with PSR2 can be removed from LNL onwards
> >
> > Signed-off-by: Vinod Govindapillai
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
> >
Quoting Kahola, Mika (2023-08-29 06:35:17-03:00)
>> -Original Message-
>> From: Intel-gfx On Behalf Of
>> Sripada, Radhakrishna
>> Sent: Tuesday, August 29, 2023 1:54 AM
>> To: Sousa, Gustavo ; intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915/cx0: Check and inc
From: Ville Syrjälä
Remove the i915 specific i2c-N symlink from HDMI connectors.
This was added to sort of mirror the DP connectors that alreayd
had their aux ch based i2c adapter sitting beneath them in the
sysfs hierarchy. But now that we have the standard "ddc" symlink
approach provided by the
From: Ville Syrjälä
We aren't intending to mutate the SDVO device mapping structs,
so make them const.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
From: Ville Syrjälä
Remove the mostly redundant hdmi->ddc_bus. The only thing that needs
it anymore is get_encoder_by_ddc_bus(), but that can be replaced with
a slight detour through attached_connector+intel_gmbus_get_adapter().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/int
From: Ville Syrjälä
We already populate connector->ddc for HDMI ports, but
so far we've not taken full advantage of it. Do that by
eliminating a bunch of intel_gmbus_get_adapter() lookups.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/
From: Ville Syrjälä
Populate connector->ddc, and thus create the "ddc" symlink
in sysfs for analog DP SST connectors.
Let's also reorder intel_dp_aux_init() vs. drm_connector_init_with_ddc()
a bit to make sure the i2c aux ch is at least somewhat populated
before we pass it on, though drm_connect
From: Ville Syrjälä
Populate connector->ddc, and thus create the "ddc" symlink
in sysfs for DVO connectors.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dvo.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/int
From: Ville Syrjälä
Populate connector->ddc, and thus create the "ddc" symlink
in sysfs for DP MST connectors.
TODO: test that this actually works
References: https://gitlab.freedesktop.org/drm/intel/-/issues/3605
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_mst.c |
From: Ville Syrjälä
Populate connector->ddc, and thus create the "ddc" symlink
in sysfs for analog VGA connectors.
As a bonus we can replace a bunch of intel_gmbus_get_adapter()
lookups with just the connector->ddc pointer. Sadly one extra
lookup still remains due to the g4x DVI-I shenanigans. W
From: Ville Syrjälä
Populate connector->ddc, and thus create the "ddc" symlink
in sysfs for the LVDS port.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i9
From: Ville Syrjälä
Rename the various names we've used for the DDC bus
i2c adapter ("i2c", "adapter", etc.) to just "ddc".
This differentiates it from the various other i2c
busses we might have (DSI panel stuff, DVO control bus, etc.).
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display
From: Ville Syrjälä
Use the standard onion peeling approach and call
drm_debugfs_connector_remove() and
drm_sysfs_connector_remove() in the reverse order in
drm_connector_unregister() than what we called their
add counterpartse in drm_connector_register().
The error unwiding in drm_connector_reg
From: Ville Syrjälä
Currently drm_sysfs_connector_add() attempts to register
the "ddc" symlink (based one connector->ddc) before the
driver's .early_register() hook has been called. That is
too early for i915 which only fully registers the aux ch
and associated i2c bus from said hook (to prevent
From: Ville Syrjälä
Populate connector->ddc for all output types that don't already
do so, and clean up a bunch of code as a result of having the
ddc i2c adapter in easy reach. And this also provides the sysfs
"ddc" symlink.
There are potentially a few oddball (mostly DVI-I) cases where
the conn
> Possible regressions
>
> • igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-6:
> □ bat-adlp-11: NOTRUN -> FAIL
mmmhhh... this failure doesn't look related. Would you mind
restarting the tests?
Andi
On Wed, 23 Aug 2023, Jani Nikula wrote:
> On Tue, 22 Aug 2023, Alex Hung wrote:
>> On 2023-08-22 06:01, Jani Nikula wrote:
>>> Over the past years I've been trying to unify the override and firmware
>>> EDID handling as well as EDID property updates. It won't work if drivers
>>> do their own rand
On Tue, 29 Aug 2023 11:44:13 +0200
Boris Brezillon wrote:
> On Tue, 29 Aug 2023 10:52:03 +0200
> Christian König wrote:
>
> > Am 29.08.23 um 09:29 schrieb Boris Brezillon:
> > > On Tue, 29 Aug 2023 05:34:23 +0300
> > > Dmitry Osipenko wrote:
> > >
> > >> On 8/28/23 13:12, Boris Brezillon
Hi Zhanjun,
On Tue, Aug 22, 2023 at 11:53:24AM -0700, John Harrison wrote:
> On 8/11/2023 11:20, Zhanjun Dong wrote:
>
> This attempts to avoid circular locking dependency between flush delayed
> work and intel_gt_reset.
> When intel_gt_reset was called, task will hold a lock.
> T
According to recent Bspec Wa 14015648006 has to be applied for all display
14 steppings.
Bspec: 66624
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/driv
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