On Thursday, August 17th, 2023 at 21:33, Dmitry Baryshkov
wrote:
> We have been looking for a way to document that the corresponding DP
> port is represented by the USB connector on the device.
>
> Consequently, I believe the best way to document it, would be to use
> DisplayPort / USB, when th
On 8/18/2023 11:30 AM, Gupta, Anshuman wrote:
-Original Message-
From: Intel-gfx On Behalf Of
Sujaritha Sundaresan
Sent: Friday, August 18, 2023 8:16 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe
Added intel_pcode_probe, promoted
> -Original Message-
> From: Intel-gfx On Behalf Of
> Sujaritha Sundaresan
> Sent: Friday, August 18, 2023 8:16 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe
>
> Added intel_pcode_probe, promoted wait for lmem init and intel_pco
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
Reviewed-by:
== Series Details ==
Series: drm/i915: Add intel_pcode_probe
URL : https://patchwork.freedesktop.org/series/122610/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13534 -> Patchwork_122610v1
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915: Add intel_pcode_probe
URL : https://patchwork.freedesktop.org/series/122610/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
== Series Details ==
Series: drm/i915: Add intel_pcode_probe
URL : https://patchwork.freedesktop.org/series/122610/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
Added intel_pcode_probe, promoted wait for lmem init and
intel_pcode_init prior to mmio_probe during load,
so that GT registers can be accessed only after this, else MCA
is observed.
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_driver.c | 37 -
d
== Series Details ==
Series: drm/i915/display: Remove unused POWER_DOMAIN_MODESET
URL : https://patchwork.freedesktop.org/series/122593/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13534 -> Patchwork_122593v1
Summary
== Series Details ==
Series: drm/i915/display: Remove unused POWER_DOMAIN_MODESET
URL : https://patchwork.freedesktop.org/series/122593/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
== Series Details ==
Series: drm/i915/display: Remove unused POWER_DOMAIN_MODESET
URL : https://patchwork.freedesktop.org/series/122593/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or director
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13534 -> Patchwork_122589v1
Summary
-
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
== Series Details ==
Series: drm/i915: Improve BW management on shared display links
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or direc
== Series Details ==
Series: drm/i915/color: cleanups and refactoring
URL : https://patchwork.freedesktop.org/series/122588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13534 -> Patchwork_122588v1
Summary
---
**SUC
== Series Details ==
Series: drm/i915/color: cleanups and refactoring
URL : https://patchwork.freedesktop.org/series/122588/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
== Series Details ==
Series: drm/i915/color: cleanups and refactoring
URL : https://patchwork.freedesktop.org/series/122588/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: drm/i915/dgfx: Enable d3cold at s2idle (rev3)
URL : https://patchwork.freedesktop.org/series/122413/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122413/revisions/3/mbox/ not
applied
Applying: drm/i915/dgfx: Enable d
== Series Details ==
Series: DSC misc fixes (rev8)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13533 -> Patchwork_117662v8
Summary
---
**SUCCESS**
No regres
On Sun, Aug 13, 2023 at 07:19:45AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/selftest: Simplify Y-major tiling
> in blit selftest (rev3)
> URL : https://patchwork.freedesktop.org/series/122318/
> State : success
>
> == Summary ==
>
> CI Bug
== Series Details ==
Series: DSC misc fixes (rev8)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
== Series Details ==
Series: DSC misc fixes (rev8)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
On Thu, Aug 17, 2023 at 12:34:40PM +, Patchwork wrote:
> == Series Details ==
>
> Series: Drop support for pre-production DG2 hardware (rev3)
> URL : https://patchwork.freedesktop.org/series/122469/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13528_full -> Patc
On 8/15/2023 5:39 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If GuC hits an internal error (and survives long enough to report it
to the KMD), it is basically toast and will stop until a GT reset and
subsequent GuC reload is performed. Previously, the KMD just printed
an error
On Wed, Aug 16, 2023 at 02:42:05PM -0700, Matt Roper wrote:
> DG2 first production steppings were C0 (for DG2-G10), B1 (for DG2-G11),
> and A1 (for DG2-G12). Several workarounds that apply onto to
> pre-production hardware can be dropped. Furthermore, several
> workarounds that apply to all produ
== Series Details ==
Series: Add DSC PPS readout (rev8)
URL : https://patchwork.freedesktop.org/series/120456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13528_full -> Patchwork_120456v8_full
Summary
---
**SUCCESS
On Thu, Aug 17, 2023 at 06:47:41AM -, Patchwork wrote:
> == Series Details ==
>
> Series: Fix C10/C20 implementation w.r.t. owned PHY lanes (rev3)
> URL : https://patchwork.freedesktop.org/series/121334/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13526_full ->
Simon, Laurent,
On 03/08/2023 23:46, Simon Ser wrote:
On Thursday, August 3rd, 2023 at 22:44, Laurent Pinchart
wrote:
On Thu, Aug 03, 2023 at 03:31:16PM +, Simon Ser wrote:
On Thursday, August 3rd, 2023 at 17:22, Simon Ser cont...@emersion.fr wrote:
The KMS docs describe "subconnecto
That power domain became unused after commit 41b4c7fe72b6 ("drm/i915:
Disable DC states for all commits").
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 --
drivers/gpu/drm/i915/display/intel_display_power.h | 1 -
drivers/gpu/drm/i915/display/in
On Thu, 17 Aug 2023, Imre Deak wrote:
> A follow-up patch will need to limit the output link bpp both in the
> non-DSC and DSC configuration, so track the pipe and link bpp limits
> separately in the link_config_limits struct.
>
> Use .4 fixed point format for link bpp matching the 1/16 bpp granul
On 8b/10b MST links the PBN value for DSC streams must be calculated
accounting for the FEC overhead. The same applies to 8b/10b non-DSC
streams if there is another DSC stream on the same link. Fix up the PBN
calculation accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/inte
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolve
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signe
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port an
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all t
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude P
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
link bpp in this case, until pipe B uses only up to 2 FDI lanes.
For this instead of the encoder compute config retry loop - which
reduced link bpp only for t
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp .. max_bpp range the same way it's done in non-DSC mode.
Atm, this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its current value
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c
A follow-up patch will need to limit the output link bpp both in the
non-DSC and DSC configuration, so track the pipe and link bpp limits
separately in the link_config_limits struct.
Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
in DSC mode and for now keep this limit ma
Factor out intel_atomic_check_config() to check and compute all the CRTC
states. This will be used by a follow up patch to recompute/check the
state until required by BW limitations between CRTCs.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 78
Computing the non-DSC mode link config is redundant once it's determined
that DSC will be needed, so skip computing it. In a follow-up patch this
simplifies setting the link limits which are dependent on the DSC vs.
non-DSC mode.
While at it sanitize the debug print about the MST DSC fallback path
Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
used in a follow-up patch.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
2 files changed, 11 insertions(+), 3 deletions(-)
d
This patchset improves the BW management of display output links shared
by multiple streams (pipes). At the moment each stream tries to reduce
its own BW in case of a limitation (by reducing the output pixel color
depth or enabling compression), however this may not reduce the BW
sufficiently resul
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and
Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +
== Series Details ==
Series: drm/i915/display: add lock while printing frontbuffer tracking bits to
debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/122429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13530 -> Patchwork_122429v2
Thanks for review and Testing.
CI Full run failure was unrelated to this patch.
Pushed to drm-intel-next
Regards,
Anshuman Gupta.
> -Original Message-
> From: Yu, Jianshui
> Sent: Thursday, August 17, 2023 8:09 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org
> Cc: Nilawar,
== Series Details ==
Series: drm/i915/display: add lock while printing frontbuffer tracking bits to
debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/122429/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2
== Series Details ==
Series: drm/i915/display: add lock while printing frontbuffer tracking bits to
debugfs (rev2)
URL : https://patchwork.freedesktop.org/series/122429/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.di
Abstract the register access better. The DSPCNTR read could be moved to
either i9xx_plane.c or intel_color.c. The latter feels better, even if
the register is written in the former.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 25
drivers/gpu
Abstract the platform specific register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 26 +---
drivers/gpu/drm/i915/display/intel_display.c | 12 +
2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/
Abstract the platform specific register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 17 +
drivers/gpu/drm/i915/display/intel_display.c | 6 --
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i91
Abstract the platform specific register access better. The separate
hsw_read_gamma_mode() will make more sense with the following changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 20
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
Split out register macros to a separate file, and move more color
register access to intel_color.c.
Jani Nikula (6):
drm/i915/regs: split out intel_color_regs.h
drm/i915/color: move CHV CGM pipe mode read to intel_color
drm/i915: move HSW+ gamma mode read to intel_color
drm/i915: move ILK+
Declutter i915_regs.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.c| 1 +
drivers/gpu/drm/i915/display/intel_color.c| 1 +
.../gpu/drm/i915/display/intel_color_regs.h | 286 ++
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drive
Add color .get_config hook to read config other than LUTs and CSCs, and
start off with CHV CGM pipe mode to abstract the platform specific
register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 16
drivers/gpu/drm/i915/display/intel
Hi Mitul,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Mitul-Golani/drm-i915-Add-has_audio-to-separate-audio-parameter-in-crtc_state/20230817-205556
base: git
== Series Details ==
Series: Get optimal audio frequency and channels (rev9)
URL : https://patchwork.freedesktop.org/series/119121/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13530 -> Patchwork_119121v9
Summary
---
== Series Details ==
Series: Get optimal audio frequency and channels (rev9)
URL : https://patchwork.freedesktop.org/series/119121/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such
file or directory
== Series Details ==
Series: Get optimal audio frequency and channels (rev9)
URL : https://patchwork.freedesktop.org/series/119121/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No
such file or directory
Hi Dave and Daniel,
I'm covering for Tvrtko on this week's fixes flow.
These 3 patches were queued since last week, but I had hold
because I had some doubts about the CI results.
I have confirmed those issues were not related to these 3
patches, so, here they are.
drm-intel-fixes-2023-08-17:
- F
Tested-By: Jianshui Yu
-Original Message-
From: Gupta, Anshuman
Sent: Wednesday, August 16, 2023 8:52 PM
To: intel-gfx@lists.freedesktop.org
Cc: Nilawar, Badal ; Tauro, Riana
; Vivi, Rodrigo ; Yu, Jianshui
; Wang, Lidong ; Gupta, Anshuman
; sta...@vger.kernel.org
Subject: [PATCH v2]
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++---
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/dr
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal
Re
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/di
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal
Reviewed-by
Move the check for limiting compressed bits_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
v2: Fix typo in commit message. (Ankit)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file change
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
driv
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: St
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
v2: Use HAS_DSC macro instead of platform check while getting min input
bpc. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal
R
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 5-6 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
On 8/17/2023 3:19 PM, Jani Nikula wrote:
On Thu, 10 Aug 2023, Ankit Nautiyal wrote:
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it tou
Hi Ville,
> -Original Message-
> From: Ville Syrjälä
> Sent: 17 August 2023 18:34
> To: Golani, Mitulkumar Ajitkumar
>
> Cc: intel-gfx@lists.freedesktop.org; jyri.sa...@linux.intel.com
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Configure and
> initialize HDMI audio capabili
== Series Details ==
Series: drm/i915/huc: silence injected failure in the load via GSC path (rev3)
URL : https://patchwork.freedesktop.org/series/121080/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13528_full -> Patchwork_121080v3_full
==
Hi,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2023-08-17:
One EPROBE_DEFER handling fix for the JDI LT070ME05000, a timing fix for
the AUO G121EAN01 panel, an integer overflow and a memory leak fixes for
the qaic accel, a use-after-free fix for nouveau and a revert for an
alleged
Tested-by: Aaron Ma
Hi Dave and Daniel,
this is the PR for drm-misc-next-fixes.
Best regards
Thomas
drm-misc-next-fixes-2023-08-17:
Short summary of fixes pull:
* Add MMU dependency to TTM unit tests
* panel: Fix Innolux G156HCE-L01 LVDS clock
The following changes since commit a8b273a8fd9c88cee038ffdae05b7eca06
On Thu, 17 Aug 2023, Dirk Lehmann wrote:
> VESA Enhanced EDID Standard does not clearly describe how display
> panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
> the Detailed Timing Definition (relative offset 17, absolute offset
> 47h[+18]) for Digital Video Signal Interfaces
On Thu, Aug 17, 2023 at 06:20:06PM +0530, Mitul Golani wrote:
> Initialize the source audio capabilities in crtc_state
> property by setting them to their maximum supported values,
> including max_channel and max_frequency. This allows for the
> calculation of audio source capabilities with respect
Compute SADs that takes into account the supported rate
and channel based on the capabilities of the audio source.
This wrapper function should encapsulate the logic for
determining the supported rate and channel and should
return a set of SADs that are compatible with the source.
--v1:
- call int
Initialize the source audio capabilities in crtc_state
property by setting them to their maximum supported values,
including max_channel and max_frequency. This allows for the
calculation of audio source capabilities with respect to
the available mode bandwidth. These capabilities encompass
paramet
To enhance the relationship between the has_audio and the source
audio parameter, create a separate crtc_state audio property and
add the has_audio parameter into it. Additionally, update the
access of the has_audio parameter from the crtc_state pointer as
it is wrapped under the audio. These modif
Currently we do not check if there is enough bandwidth for
audio, and what channels and freq it can really support.
Also sometimes there can be HW constraints e.g. GLK where audio
channels supported are only 2.
https://patchwork.freedesktop.org/series/107647/
Obtain the optimal audio rate and cha
On Thu, 17 Aug 2023, Ville Syrjälä wrote:
> On Tue, Aug 15, 2023 at 01:19:07PM +0300, Jani Nikula wrote:
>> This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
>>
>> Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
>> EDID detailed mode sync parsing. Unfortunately
== Series Details ==
Series: Drop support for pre-production DG2 hardware (rev3)
URL : https://patchwork.freedesktop.org/series/122469/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13528_full -> Patchwork_122469v3_full
Sum
On Tue, Aug 15, 2023 at 01:19:07PM +0300, Jani Nikula wrote:
> This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
>
> Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
> EDID detailed mode sync parsing. Unfortunately, there are quite a few
> displays out there that
On Thu, 10 Aug 2023, Ankit Nautiyal wrote:
> This series is an attempt to address multiple issues with DSC,
> scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it touches the same areas.
However, once you ha
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