> From: Tvrtko Ursulin
>
> On Meteorlake CPU cache will not contain stale data after GPU
> access since write-invalidate protocol is used, which means
> there is no need to flush before potentially transitioning the
> buffer to a non-coherent domain.
>
> Use the opportunity to documet the situatio
== Series Details ==
Series: DSC misc fixes (rev5)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13435 -> Patchwork_117662v5
Summary
---
**SUCCESS**
No regres
== Series Details ==
Series: DSC misc fixes (rev5)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 7/25/2023 4:49 PM, Nautiyal, Ankit K wrote:
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
registe
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/d
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal
---
driver
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++---
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal
-
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 +++
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal
---
drivers/gp
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
---
include
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/di
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal
Re
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 5-6 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
== Series Details ==
Series: drm/i915/gem: Add check for bitmap_zalloc()
URL : https://patchwork.freedesktop.org/series/121491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13435 -> Patchwork_121491v1
Summary
---
**
== Series Details ==
Series: Handle dma fences in dirtyfb ioctl (rev3)
URL : https://patchwork.freedesktop.org/series/116620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432_full -> Patchwork_116620v3_full
Summary
-
Add the check for the return value of bitmap_zalloc() in order to
guarantee the success of the allocation.
Fixes: e9b73c67390a ("drm/i915: Reduce memory pressure during shrinker by
preallocating swizzle pages")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 5 +++
== Series Details ==
Series: drm/i915/guc/slpc: Restore efficient freq earlier (rev3)
URL : https://patchwork.freedesktop.org/series/121150/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13432_full -> Patchwork_121150v3_full
Hi Daniele and John,
On Thu, Jul 27, 2023 at 12:35:02PM +0100, Tvrtko Ursulin wrote:
>
> On 26/07/2023 16:53, Jonathan Cavitt wrote:
> > Refactor i915_coherent_map_type to be GT-centric rather than
> > device-centric. Each GT may require different coherency
> > handling due to hardware workaroun
== Series Details ==
Series: drm/i915: Avoid circular locking dependency when flush delayed work on
gt reset (rev4)
URL : https://patchwork.freedesktop.org/series/118898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13434 -> Patchwork_118898v4
===
== Series Details ==
Series: Another take on PAT/object cache mode refactoring
URL : https://patchwork.freedesktop.org/series/121450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13432_full -> Patchwork_121450v1_full
Summa
== Series Details ==
Series: drm/i915: Avoid circular locking dependency when flush delayed work on
gt reset (rev4)
URL : https://patchwork.freedesktop.org/series/118898/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/i915: Avoid circular locking dependency when flush delayed work on
gt reset (rev4)
URL : https://patchwork.freedesktop.org/series/118898/
State : warning
== Summary ==
Error: dim checkpatch failed
bf7983c87486 drm/i915: Avoid circular locking dependency when f
On Thu, Jul 27, 2023 at 04:57:53PM -0700, Matt Roper wrote:
> On Thu, Jul 27, 2023 at 03:55:00PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
> > introduced PAT indices to i915 internal APIs, partially rep
== Series Details ==
Series: drm/i915/huc: fix intel_huc.c doc bulleted list format error
URL : https://patchwork.freedesktop.org/series/121438/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13432_full -> Patchwork_121438v1_full
On Thu, Jul 27, 2023 at 03:55:03PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Now that i915 understands the caching modes behind PAT indices, we can
> refine the check in use_cpu_reloc() to not reject the uncached PAT if it
> was set by userspace.
>
> Instead it can decide based on
On Thu, Jul 27, 2023 at 03:55:02PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Now that i915 understands the caching modes behind PAT indices, and having
> also special cased the Meteorlake snooping fully coherent mode, we can
> remove the user PAT check from gpu_write_needs_clflush()
On Thu, Jul 27, 2023 at 03:55:01PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Now that i915 understands the caching modes behind PAT indices, we can
> refine the check in vm_fault_gtt() to not reject the uncached PAT if it
> was set by userspace on a snoopable platform.
>
> Signed-o
On Thu, Jul 27, 2023 at 03:55:00PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
> introduced PAT indices to i915 internal APIs, partially replacing the
> usage of driver internal cache_level, but has also added
On Thu, Jul 27, 2023 at 03:54:59PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Eliminate a bunch of runtime calls to i915_gem_get_pat_index() by caching
> the interesting PAT indices in struct drm_i915_private. They are static
> per platfrom so no need to consult a function every time
On Thu, Jul 27, 2023 at 03:54:58PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> No need to run extra instructions which will never trigger on platforms
> before Meteorlake.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++
On Thu, Jul 27, 2023 at 03:54:57PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> On Meteorlake CPU cache will not contain stale data after GPU access since
> write-invalidate protocol is used, which means there is no need to flush
> before potentially transitioning the buffer to a non-c
== Series Details ==
Series: MTL Degamma implementation (rev4)
URL : https://patchwork.freedesktop.org/series/119844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432_full -> Patchwork_119844v4_full
Summary
---
**
On 6/1/2023 8:59 AM, Alan Previn wrote:
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when
== Series Details ==
Series: Handle dma fences in dirtyfb ioctl (rev3)
URL : https://patchwork.freedesktop.org/series/116620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432 -> Patchwork_116620v3
Summary
---
**SU
== Series Details ==
Series: Handle dma fences in dirtyfb ioctl (rev3)
URL : https://patchwork.freedesktop.org/series/116620/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc/slpc: Restore efficient freq earlier (rev3)
URL : https://patchwork.freedesktop.org/series/121150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432 -> Patchwork_121150v3
Summary
This attempts to avoid circular locking dependency between flush delayed work
and intel_gt_reset.
Switched from cancel_delayed_work_sync to cancel_delayed_work, the non-sync
version for reset path, it is safe as the worker has the trylock code to handle
the lock; Meanwhile keep the sync version
== Series Details ==
Series: Another take on PAT/object cache mode refactoring
URL : https://patchwork.freedesktop.org/series/121450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432 -> Patchwork_121450v1
Summary
---
== Series Details ==
Series: Another take on PAT/object cache mode refactoring
URL : https://patchwork.freedesktop.org/series/121450/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Another take on PAT/object cache mode refactoring
URL : https://patchwork.freedesktop.org/series/121450/
State : warning
== Summary ==
Error: dim checkpatch failed
7ea1d7a9ac31 drm/i915: Skip clflush after GPU writes on Meteorlake
5658be9fc6d2 drm/i915: Split PTE e
== Series Details ==
Series: drm/i915/huc: fix intel_huc.c doc bulleted list format error
URL : https://patchwork.freedesktop.org/series/121438/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432 -> Patchwork_121438v1
Summ
== Series Details ==
Series: drm/i915/huc: fix intel_huc.c doc bulleted list format error
URL : https://patchwork.freedesktop.org/series/121438/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
On Thu, Jul 27, 2023 at 03:38:46PM -0300, Lucas De Marchi wrote:
> On Mon, Jul 24, 2023 at 05:13:21PM -0700, Matt Roper wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>
> for the phy checks what I have locally is:
>
> > ind
On Mon, Jul 24, 2023 at 05:13:21PM -0700, Matt Roper wrote:
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
for the phy checks what I have locally is:
index 1b00ef2c6185..a42b3c4c0ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0
== Series Details ==
Series: MTL Degamma implementation (rev4)
URL : https://patchwork.freedesktop.org/series/119844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13432 -> Patchwork_119844v4
Summary
---
**SUCCESS**
== Series Details ==
Series: MTL Degamma implementation (rev4)
URL : https://patchwork.freedesktop.org/series/119844/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
On 27/07/2023 12:54, Maarten Lankhorst wrote:
Hey,
On 2023-07-26 13:41, Tvrtko Ursulin wrote:
On 26/07/2023 11:14, Maarten Lankhorst wrote:
Hey,
On 2023-07-22 00:21, Tejun Heo wrote:
On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:
$ cat drm.memory.stat
card0 region=
On 27/07/2023 14:42, Maarten Lankhorst wrote:
On 2023-07-26 21:44, Tejun Heo wrote:
Hello,
On Wed, Jul 26, 2023 at 12:14:24PM +0200, Maarten Lankhorst wrote:
So, yeah, if you want to add memory controls, we better think
through how
the fd ownership migration should work.
I've taken a look
On 7/18/23 18:44, Nathan Chancellor wrote:
Hi all,
A proposed update to clang's -Wconstant-logical-operand [1] to warn when
the left hand side is a constant as well now triggers with the modulo
expression in nsecs_to_jiffies_timeout() when NSEC_PER_SEC is not a
multiple of HZ, such as CONFIG_HZ=
== Series Details ==
Series: fdinfo memory stats (rev6)
URL : https://patchwork.freedesktop.org/series/119082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13429_full -> Patchwork_119082v6_full
Summary
---
**SUCCESS
Hi,
On 27/07/2023 15:10, Kamil Konieczny wrote:
Hi Tvrtko,
On 2023-07-27 at 10:20:24 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Define the storage structure and copy over memory data as parsed by the
fdinfo helpers.
v2:
* Fix empty region map entry skip condition. (Kamil, Chris)
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in vm_fault_gtt() to not reject the uncached PAT if it
was set by userspace on a snoopable platform.
Signed-off-by: Tvrtko Ursulin
Cc: Fei Yang
Cc: Matt Roper
---
drivers/gpu/drm/i915
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in i915_gem_object_can_bypass_llc() to stop assuming any
user PAT can bypass the shared cache (if there is any).
Instead we can use the absence of I915_BO_CACHE_COHERENT_FOR_WRITE as the
From: Tvrtko Ursulin
Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
introduced PAT indices to i915 internal APIs, partially replacing the
usage of driver internal cache_level, but has also added a few sub-
optimal design decisions which this patch tries to improve upon
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, we can
refine the check in use_cpu_reloc() to not reject the uncached PAT if it
was set by userspace.
Instead it can decide based on the presence of full coherency which
should be functionally equivalent on lega
From: Tvrtko Ursulin
Now that i915 understands the caching modes behind PAT indices, and having
also special cased the Meteorlake snooping fully coherent mode, we can
remove the user PAT check from gpu_write_needs_clflush().
Signed-off-by: Tvrtko Ursulin
Cc: Fei Yang
Cc: Matt Roper
---
drive
From: Tvrtko Ursulin
Eliminate a bunch of runtime calls to i915_gem_get_pat_index() by caching
the interesting PAT indices in struct drm_i915_private. They are static
per platfrom so no need to consult a function every time.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
Cc: Fei Yang
---
drive
From: Tvrtko Ursulin
No need to run extra instructions which will never trigger on platforms
before Meteorlake.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_pp
From: Tvrtko Ursulin
On Meteorlake CPU cache will not contain stale data after GPU access since
write-invalidate protocol is used, which means there is no need to flush
before potentially transitioning the buffer to a non-coherent domain.
Use the opportunity to documet the situation on discrete
From: Tvrtko Ursulin
Good news is that I realized series can be split after all. Bad news is that it
is still a lot to go through.
drm/i915: Skip clflush after GPU writes on Meteorlake
This is based on what Fei found out from hardware architects. If we agree the
the function this helper shoul
Hi Tvrtko,
On 2023-07-27 at 10:20:23 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Add parsing and memory storage for the memory usage related fdinfo stats.
>
> Uses the same approach as the engine utilization code by either auto-
> discovering different memory regions, or allowing fo
Hi Maira,
On Thu, Jul 27, 2023 at 11:01:27AM -0300, Maira Canal wrote:
> Hi Nathan,
>
> On 7/18/23 18:44, Nathan Chancellor wrote:
> > A proposed update to clang's -Wconstant-logical-operand to warn when the
> > left hand side is a constant shows the following instance in
> > nsecs_to_jiffies_tim
Hi Tvrtko,
On 2023-07-27 at 10:20:24 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Define the storage structure and copy over memory data as parsed by the
> fdinfo helpers.
>
> v2:
> * Fix empty region map entry skip condition. (Kamil, Chris)
>
> Signed-off-by: Tvrtko Ursulin
> Cc:
Hi Nathan,
On 7/18/23 18:44, Nathan Chancellor wrote:
A proposed update to clang's -Wconstant-logical-operand to warn when the
left hand side is a constant shows the following instance in
nsecs_to_jiffies_timeout() when NSEC_PER_SEC is not a multiple of HZ,
such as CONFIG_HZ=300:
In file inc
Hey,
On 2023-07-26 21:44, Tejun Heo wrote:
Hello,
On Wed, Jul 26, 2023 at 12:14:24PM +0200, Maarten Lankhorst wrote:
So, yeah, if you want to add memory controls, we better think through how
the fd ownership migration should work.
I've taken a look at the series, since I have been working on
== Series Details ==
Series: fdinfo memory stats (rev6)
URL : https://patchwork.freedesktop.org/series/119082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13429 -> Patchwork_119082v6
Summary
---
**SUCCESS**
No r
Fix the following make htmldocs errors/warnings:
./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29: ERROR: Unexpected indentation.
./drivers/gpu/drm/i915/gt/uc/intel_huc.c:30: WARNING: Block quote ends without
a blank line; unexpected unindent.
./drivers/gpu/drm/i915/gt/uc/intel_huc.c:35: WARNING: Bull
Thanks for the patches and the reviews, pushed to drm-intel-next.
Regards,
Ankit
On 7/27/2023 5:27 PM, Nautiyal, Ankit K wrote:
LGTM.
Acked-by: Ankit Nautiyal
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to
On Fri, Jul 21, 2023 at 04:50:44PM +0200, Maxime Ripard wrote:
> Hi,
>
> Here's this week drm-misc-next PR
>
> Thanks!
> Maxime
>
> The following changes since commit 36672dda2eb715af99e9abbcdc400d46598b691c:
>
> drm/loongson: Remove a useless check in cursor_plane_atomic_async_check()
> (20
== Series Details ==
Series: fdinfo memory stats (rev6)
URL : https://patchwork.freedesktop.org/series/119082/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from userland to 24 bit before writing into the
HW to contin
Hi Jonathan,
On Wed, Jul 26, 2023 at 08:53:54AM -0700, Jonathan Cavitt wrote:
> The object pin created for shmem_create_from_object is just a
> single use mapping with the sole purpose of reading the contents
> of the whole object in bulk. And the whole source object is also
> even a throw-away.
Hi Jonathan,
On Wed, Jul 26, 2023 at 08:53:56AM -0700, Jonathan Cavitt wrote:
> WA_22016122933 was recently applied to all MeteorLake engines, which is
> simultaneously too broad (should only apply to Media engines) and too
> specific (should apply to all platforms that use the same media engine
>
Hi Jonathan,
On Wed, Jul 26, 2023 at 08:53:55AM -0700, Jonathan Cavitt wrote:
> Refactor i915_coherent_map_type to be GT-centric rather than
> device-centric. Each GT may require different coherency
> handling due to hardware workarounds.
>
> Since the function now takes a GT instead of the i915
Am 26.07.23 um 20:15 schrieb Simon Ser:
On Monday, July 24th, 2023 at 23:14, Michał Winiarski
wrote:
Having a limit of 64 DRM devices is not good enough for modern world
where we have multi-GPU servers, SR-IOV virtual functions and virtual
devices used for testing.
Let's utilize full minor ra
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdepth,
upscale the values sent from
LGTM.
Acked-by: Ankit Nautiyal
On 7/25/2023 2:00 PM, Chaitanya Kumar Borah wrote:
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from
16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16
bit precision. Until a new uapi comes along to support higher bitdept
Hey,
On 2023-07-26 13:41, Tvrtko Ursulin wrote:
On 26/07/2023 11:14, Maarten Lankhorst wrote:
Hey,
On 2023-07-22 00:21, Tejun Heo wrote:
On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:
$ cat drm.memory.stat
card0 region=system total=12898304 shared=0 active=0
resident
== Series Details ==
Series: fdinfo memory stats (rev5)
URL : https://patchwork.freedesktop.org/series/119082/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13428 -> Patchwork_119082v5
Summary
---
**FAILURE**
Seri
On 26/07/2023 16:53, Jonathan Cavitt wrote:
Refactor i915_coherent_map_type to be GT-centric rather than
device-centric. Each GT may require different coherency
handling due to hardware workarounds.
Since the function now takes a GT instead of the i915, the function is
renamed and moved to th
On 26/07/2023 16:53, Jonathan Cavitt wrote:
The object pin created for shmem_create_from_object is just a
single use mapping with the sole purpose of reading the contents
of the whole object in bulk. And the whole source object is also
even a throw-away. Ergo, the additional logic required by
== Series Details ==
Series: fdinfo memory stats (rev5)
URL : https://patchwork.freedesktop.org/series/119082/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Tvrtko Ursulin
Account ring buffers and logical context space against the owning client
memory usage stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_context.c | 14 ++
drivers/gpu/drm/i915/i915_drm_client.c | 10 +++
From: Tvrtko Ursulin
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
and accumulate object size into the respective drm_memory_stats
categories.
Obj
From: Tvrtko Ursulin
To enable accounting of indirect client memory usage (such as page tables)
in the following patch, lets start recording the creator of each PPGTT.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11
From: Tvrtko Ursulin
A short series to enable fdinfo memory stats for i915.
I added tracking of most classes of objects (user objects, page tables, context
state, ring buffers) which contribute to client's memory footprint and am
accouting their memory use along the similar lines as in Rob's msm
From: Tvrtko Ursulin
In order to show per client memory usage lets add some infrastructure
which enables tracking buffer objects owned by clients.
We add a per client list protected by a new per client lock and to support
delayed destruction (post client exit) we make tracked objects hold
refere
From: Tvrtko Ursulin
Account page table backing store against the owning client memory usage
stats.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt
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