== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
URL : https://patchwork.freedesktop.org/series/120086/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_120086v1_full
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next
head: 0c4f52bac4401dfd6f82984040bc0e163b0ccb9c
commit: f6757dfcfde722fdeaee371b66f63d7eb61dd7e4 [1/2] drm/doc: fix duplicate
declaration warning
reproduce:
(https://download.01.org/0day-ci/archive/20230701/202307011340.vny1abul-...@
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15)
URL : https://patchwork.freedesktop.org/series/107550/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_107550v15_full
== Series Details ==
Series: DSC misc fixes (rev3)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340_full -> Patchwork_117662v3_full
Summary
---
**SUCCESS**
On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote:
> v3 of https://patchwork.freedesktop.org/series/119766/
>
> Changes from v2:
>
> - Do not rmw if (clr | set) covers all bits
> - Add patch to make sure the set bits are also checked on
> wa_*_clr_set() when clr is
== Series Details ==
Series: Fix ctx workarounds for non-masked regs (rev3)
URL : https://patchwork.freedesktop.org/series/119826/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340 -> Patchwork_119826v3
Summary
---
== Series Details ==
Series: Fix ctx workarounds for non-masked regs (rev3)
URL : https://patchwork.freedesktop.org/series/119826/
State : warning
== Summary ==
Error: dim checkpatch failed
f9ace84612b8 drm/i915/gt: Move wal_get_fw_for_rmw()
98981921388c drm/i915/gt: Clear all bits from GEN12_
Most of the context workarounds tweak masked registers, but not all. For
masked registers, when writing the value it's sufficient to just write
the wa->set_bits since that will take care of both the clr and set bits
as well as not overwriting other bits.
However there are some workarounds, the reg
When checking if the workarounds were applied succesfully, the read-back
mask should also contain the bits being set: it's possible that in a
call to wa_write_clr_set(), the cleared bits are not a superset of the
set bits.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarou
Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
1 file changed, 1 insertion(+), 4 deleti
v3 of https://patchwork.freedesktop.org/series/119766/
Changes from v2:
- Do not rmw if (clr | set) covers all bits
- Add patch to make sure the set bits are also checked on
wa_*_clr_set() when clr is not a superset.
Tested on DG2 with intel_reg reading 0xb158 with a bu
The comment on the parameter being 0 to avoid the read back doesn't
apply as this is not a call to wa_add(), but rather to
wa_write_clr_set(). So, this register is actually checked and it's
according to the Bspec that the register is RW, not RO.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm
Contrary to GEN12_FF_MODE2, platforms using XEHP_FF_MODE2 are not
affected by Wa_1608008084, hence read back can be enabled.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
Right now context workarounds don't do a rmw and instead only write to
the register. Since 2 separate programmings to the same register are
coalesced into a single write, this is not problematic for
GEN12_FF_MODE2 since both TDS and GS timer are going to be written
together and the other remaining
Move helper function to get all the forcewakes required by the wa list
to the top, so it can be re-used by other functions.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++---
1 file changed, 16 insertions(+), 1
On 5/23/2023 3:51 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Exercise a bunch of up and down rps thresholds to verify hardware
is happy with them all.
To limit the overall runtime relies on probability and number of runs
to approach complete coverage.
Signed-off-by: Tvrtko Ursulin
Cc:
On Fri, 30 Jun 2023, Bjorn Helgaas wrote:
> On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote:
>> On 2023/6/30 01:44, Limonciello, Mario wrote:
>> > > On 2023/6/29 23:54, Bjorn Helgaas wrote:
>> > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote:
>
>> > > > 4) Right now w
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
URL : https://patchwork.freedesktop.org/series/120086/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340 -> Patchwork_120086v1
On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote:
> On 2023/6/30 01:44, Limonciello, Mario wrote:
> > > On 2023/6/29 23:54, Bjorn Helgaas wrote:
> > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote:
> > > > 4) Right now we're in the middle of the v6.5 merge window, so ne
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Do not use stolen on MTL
URL : https://patchwork.freedesktop.org/series/120086/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x8
On Wed, Jun 28, 2023 at 05:10:17PM +0300, Stanislav Lisovskiy wrote:
> If we are using Bigjoiner dpll_hw_state is supposed to be exactly
> same as for master crtc, so no need to save it's state for slave crtc.
Yeah, and the master has recalculated this already. I guess this
used to make some sense
== Series Details ==
Series: drm/i915: Init DDI ports in VBT order (rev5)
URL : https://patchwork.freedesktop.org/series/114200/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13340 -> Patchwork_114200v5
Summary
---
*
Use smem on MTL due to a HW bug in MTL that prevents
reading from stolen memory using LMEM BAR.
Cc: Oak Zeng
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Andi Shyti
Cc: Andrzej Hajda
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
Use smem on MTL due to a HW bug in MTL that prevents
reading from stolen memory using LMEM BAR.
Cc: Oak Zeng
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Andi Shyti
Cc: Andrzej Hajda
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 ++
drivers/gpu/drm/i915/display/i
== Series Details ==
Series: drm/i915: Init DDI ports in VBT order (rev5)
URL : https://patchwork.freedesktop.org/series/114200/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Init DDI ports in VBT order (rev5)
URL : https://patchwork.freedesktop.org/series/114200/
State : warning
== Summary ==
Error: dim checkpatch failed
458507c5d81b drm/i915: Initialize dig_port->aux_ch to NONE to be sure
c63ca1d72c9b drm/i915: Only populate
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Try to deal with duplicate child devices for the same DDI port
> by attempting to initialize them in VBT defined order The first
> on to succeed for a specific DDI port will be the one we use.
>
> We'll also get rid of i915->disp
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop with the VBT DDC pin sanitation, and instead just check
> that the appropriate DDC pin is still available when initializing
> a HDMI connector.
>
> The reason being that we want to start initializing ports in
> VBT order to
On Fri, 30 Jun 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We'll have a few places where we need to do the full (incl. ICL+ DSI)
> DVO port->port conversion, so extract the code for that into a helper.
>
> Suggested-by: Jani Nikula
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Niku
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 6352a698ca5bf26a9199202666b16cf741f579f6 Add linux-next specific
files for 20230630
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/20230613.hher4zoo-...@intel.com
https
From: Ville Syrjälä
We'll have a few places where we need to do the full (incl. ICL+ DSI)
DVO port->port conversion, so extract the code for that into a helper.
Suggested-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 18 ++
1 file
From: Ville Syrjälä
Stop with the VBT AUX CH sanitation, and instead just check
that the appropriate AUX CH is still available when initializing
a DP/TC port.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly confli
From: Ville Syrjälä
Stop with the VBT DDC pin sanitation, and instead just check
that the appropriate DDC pin is still available when initializing
a HDMI connector.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly
From: Ville Syrjälä
Mixing VBT based AUX CH with platform defaults seems like
a recipe for conflicts. Let's only populate AUX CH if we
absolutely need it, that is only if we are dealing with
a DP output or a TC port (which need it due to some power
well shenanigans).
TODO: double check that real
From: Ville Syrjälä
Try to deal with duplicate child devices for the same DDI port
by attempting to initialize them in VBT defined order The first
on to succeed for a specific DDI port will be the one we use.
We'll also get rid of i915->display.vbt.ports[] here as any conflicts
will now be handl
From: Ville Syrjälä
The remaining parts of the big VBT based DDI port initialization
series.
The main goal being to get the HDMI port working on many
ADL-P machines where the VBT declares both eDP and HDMI
for the same DDI port (B).
v3: Pimped commit messages
Add intel_bios_encoder_port() a
From: Ville Syrjälä
Make sure dig_port->aux_ch is trustworthy by initializing it
to NONE (-1) at the start. The encoder init will later fill in
the actual value, if appropriate.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c| 2 ++
drivers/
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev15)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340 -> Patchwork_107550v15
==
== Series Details ==
Series: DSC misc fixes (rev3)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13340 -> Patchwork_117662v3
Summary
---
**WARNING**
Minor unk
On 2023-06-22 20:57:50 [-0400], Paul Gortmaker wrote:
[ longer report about what is broken.]
Commit ade8a0f598443 ("drm/i915: Make all GPU resets atomic") introduces
a preempt_disable() section around the invocation of the reset callback.
I can't find an explanation why this is needed. There was a
== Series Details ==
Series: DSC misc fixes (rev3)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: DSC misc fixes (rev3)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim checkpatch failed
eaaa78e717b1 drm/i915/dp: Consider output_format while computing dsc bpp
6395d26c8fa4 drm/i915/dp: Move compressed bpp check with
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
v2: Use new wrapper while getting max bpc also.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Check for
This series fixes issues faced when an HDMI2.1 sink that does not
support DSC is connected via HDMI2.1PCON. It also includes other minor
HDMI2.1 PCON fixes/refactoring.
Patch 1-3 Have minor fixes to consider output_format while computing
dsc_bpp and have consistent naming for pipe_bpp, link_bpp an
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 189
1 file changed
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++---
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
registe
Currently we check if pipe_bpp is max the min DSC bpc requirements.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +
1 file changed, 24 insertions(
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 11
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
---
include
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
dri
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above case, while computing cdclk.
v2: Use helper to get the adjusted pixel rate.
Signed-off-by: Ankit Nautiyal
---
drive
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 4-5 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
Follow consistent naming convention. Replace MTL with
METEORLAKE. Added defines that are replacing IS_MTL_GRAPHICS_STEP with
IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
v2:
- Replace IS_MLT_GRAPHICS_STEP with IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
- Changed subject prefix
Currently, the default VGA device selection is not perfect. Potential
problems are:
1) This function is a no-op on non-x86 architectures.
2) It does not take the PCI Bar may get relocated into consideration.
3) It is not effective for the PCI device without a dedicated VRAM Bar.
4) It is device-ag
Currently, the default VGA device selection is not perfect. Potential
problems are:
1) This function is a no-op on non-x86 architectures.
2) It does not take the PCI Bar may get relocated into consideration.
3) It is not effective for the PCI device without a dedicated VRAM Bar.
4) It is device-ag
This patch adds the aperture_contain_firmware_fb() function to do the
determination. Unfortunately due to the fact that apertures list will be
freed dynamically, the location and size information of the firmware fb
will be lost after dedicated drivers call
aperture_remove_conflicting_devices(),
ape
== Series Details ==
Series: drm/i915/shrinker: Treat fb's with higher priority than active reference
URL : https://patchwork.freedesktop.org/series/120039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13337_full -> Patchwork_120039v1_full
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