On 5/19/2023 11:45 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
On 5/19/2023 11:03 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that
== Series Details ==
Series: i915/perf: Avoid reading OA reports before they land
URL : https://patchwork.freedesktop.org/series/118054/
State : warning
== Summary ==
Error: dim checkpatch failed
0e9ec65e25cf i915/perf: Avoid reading OA reports before they land
-:9: WARNING:TYPO_SPELLING: 'occ
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13168_full -> Patchwork_118034v1_full
Summary
---
**S
On 20/05/2023 00:16, Rodrigo Vivi wrote:
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
On 19/04/2023 18:43, Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change
On DG2, capturing OA reports while running heavy render workloads
sometimes results in invalid OA reports where 64-byte chunks inside
reports have stale values. Under memory pressure, high OA sampling rates
(13.3 us) and heavy render workload, occassionally, the OA HW TAIL
pointer does not progress
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote:
> On 19/04/2023 18:43, Mark Yacoub wrote:
> > Hi all,
> > This is v10 of the HDCP patches. The patches are authored by Sean Paul.
> > I rebased and addressed the review comments in v6-v10.
> >
> > Main change in v10 is handling the
On Wed, May 17, 2023 at 01:02:03PM +0800, Cong Liu wrote:
> Be sure to properly free the allocated memory before exiting
> the live_nop_switch function.
>
> Signed-off-by: Cong Liu
> Suggested-by: Rodrigo Vivi
pushed, thanks for the patch
> ---
> .../gpu/drm/i915/gem/selftests/i915_gem_contex
On Fri, May 19, 2023 at 07:36:56PM +, Prahlad Kilambi wrote:
> > One question is are we able to find a "one size fits all" values.
>
> > However regardless of that, given we already expose frequency controls in
> > sysfs
> > with the same reasoning of allowing system owners explicit control i
On Fri, Apr 28, 2023 at 09:14:56AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
> driver
On Fri, Apr 28, 2023 at 09:44:53AM +0100, Tvrtko Ursulin wrote:
>
> On 28/04/2023 09:14, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > User feedback indicates significant performance gains are possible in
> > specific games with non default RPS up/down thresholds.
> >
> > Expose these
On 5/17/2023 2:04 PM, John Harrison wrote:
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the ima
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13168 -> Patchwork_118034v1
Summary
---
**SUCCESS**
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/118034/
State : warning
== Summary ==
Error: dim checkpatch failed
b0667b45bb9b drm/i915/pmu: Change bitmask of enabled events to u32
3120083f65f4 drm/i915/pmu: Support PMU for all engi
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticat
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabl
On Friday, 19 May 2023 12:28:49 CEST Andrzej Hajda wrote:
> On 19.05.2023 11:43, Janusz Krzysztofik wrote:
> > Visible glitches have been observed when running graphics applications on
> > Linux under Xen hypervisor. Those observations have been confirmed with
> > failures from kms_pwrite_crc IGT
On Thu, May 18, 2023 at 10:08:42PM +, Taylor, Clinton A wrote:
> On Thu, 2023-05-18 at 19:31 +, Patchwork wrote:
> > Patch Details
> > Series: C20 Computed HDMI TMDS pixel clocks (rev3)
> > URL:https://patchwork.freedesktop.org/series/117399/
> > State: failure
> > Details:
== Series Details ==
Series: drm/i915: Fix memory leaks in function live_nop_switch (rev3)
URL : https://patchwork.freedesktop.org/series/117458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13166_full -> Patchwork_117458v3_full
===
On 19/04/2023 18:43, Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change in v10 is handling the kernel test bot warnings.
Patches 1-4 focus on moving the common HDCP helpers to comm
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add some
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/i915_p
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global de
With MTL, frequency and rc6 counters are specific to a gt. Export these
counters via gt-specific events to the user space.
v2: Remove aggregation support from kernel
v3: Review comments (Ashutosh, Tvrtko)
v4:
- Include R-b for 6/6
- Add Test-with
- Fix versioning info in cover letter
v5:
- Include
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXM
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i91
== Series Details ==
Series: drm/i915: Fix memory leaks in function live_nop_switch (rev3)
URL : https://patchwork.freedesktop.org/series/117458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13166 -> Patchwork_117458v3
Sum
On 2023-05-04 18:35:05, Dmitry Baryshkov wrote:
>
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
Propagate*
> the drm_dsc_config.
>
> Reviewed-by: Jani Nikula
> Signed-off-by: Dmitry Baryshkov
Aft
Hello Maarten Lankhorst,
This is a semi-automatic email about new static checker warnings.
The patch cf3e3e86d779: "drm/i915: Use ttm mmap handling for ttm
bo's." from Jun 10, 2021, leads to the following Smatch complaint:
./drivers/gpu/drm/i915/gem/i915_gem_mman.c:1008 i915_gem_mmap()
Be sure to properly free the allocated memory before exiting
the live_nop_switch function.
Signed-off-by: Cong Liu
Suggested-by: Rodrigo Vivi
---
.../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
On Thu, 06 Apr 2023 19:06:30 +0300, Dmitry Osipenko wrote:
> This patchset makes dma-buf exporters responisble for taking care of
> the reservation lock. I also included patch that moves drm-shmem to use
> reservation lock, to let CI test the whole set. I'm going to take all
> the patches via the
== Series Details ==
Series: Use different intel_hdcp_gsc_message instances
URL : https://patchwork.freedesktop.org/series/118009/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13165 -> Patchwork_118009v1
Summary
---
== Series Details ==
Series: Use different intel_hdcp_gsc_message instances
URL : https://patchwork.freedesktop.org/series/118009/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, May 17, 2023 3:58 PM
> To: David Airlie ; Daniel Vetter ; Jani
> Nikula ; Kandpal, Suraj
> ; Joonas Lahtinen
> ; Vivi, Rodrigo ;
> Tvrtko Ursulin ; Rob Clark
> ; Abhinav Kumar ;
> Sean Paul ; Marijn Suijten
>
> Cc: Ville
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev10)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13165_full -> Patchwork_116870v10_full
===
On 19.05.2023 11:43, Janusz Krzysztofik wrote:
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using ha
Fill out hdcp_gsc_message_in and hdcp_gsc_message_out structure
which also includes differentiating header of both messages
using header_in and header_out.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp_gs
Add hdcp_gsc_message_in and hdcp_gsc_message_out to help
differenctiate the reply given by gsc to avoid any kind of
message corruption due message structure reuse.
hdcp_gsc_message_out will be filled in upcoming patches
Cc: Ankit Nautiyal
Cc: Alan Previn
Cc: Daniele Ceraolo Spurio
Signed-off-by
Use different intel_hdcp_gsc_message instances to send
and receive the messages from gsc since there are chances
using the same instance can cause corruption of data.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (2):
drm/i915/hdcp: Create hdcp_gsc_message in and out
drm/i915/hdcp: Fill in hdcp
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc IGT test that verifies data coherency of DRM
frame buffer objects using hardware CRC checksums calculated by display
contro
On 18/05/2023 15:44, Tetsuo Handa wrote:
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
i915 became the last flush_scheduled_work() user, but developers cannot
find time for auditing which work i
> From: Liu, Yi L
> Sent: Thursday, May 18, 2023 9:26 PM
> > > +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> > > +{
> > > + if (vdev->iommufd_device)
> > > + return iommufd_device_to_id(vdev->iommufd_device);
> > > + if (vdev->noiommu_access)
> > > + return iommufd_a
On 17/05/2023 12:18, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 13:16 +0100, Tvrtko Ursulin wrote:
On 12/05/2023 10:54, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 10:32 +0100, Tvrtko Ursulin wrote:
On 12/05/2023 10:10, Coelho, Luciano wrote:
On Fri, 2023-05-12 at 10:04 +0100, Tvrtko Urs
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