: RE: [PATCH v2] drm/i915/display: Increase AUX timeout for Type-C
>
> > -Original Message-
> > From: Kandpal, Suraj
> > Sent: Wednesday, April 5, 2023 12:50 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R ; Sharma, Swati2
> > ; Kandpal, Suraj
> > Subject: [PATCH v2] dr
> fei.y...@intel.com kirjoitti 17.4.2023 klo 9.24:
>> From: Fei Yang
>>
>> The series includes patches needed to enable MTL.
>> Also add new extension for GEM_CREATE uAPI to let user space set cache
>> policy for buffer objects.
>
> if I'm counting right, this would be version 5 of the series, y
fei.y...@intel.com kirjoitti 17.4.2023 klo 9.24:
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
if I'm counting right, this would be version 5 of the series, yet that
is not sh
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
Fei Yang (7):
drm/i915/mtl: Set has_llc=0
drm/i915/mtl: Add PTE encode function
drm/i915/mtl: workaround coherency issue for Me
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls a
MOCS/PAT table update.
Alos the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. This p
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out its life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a defau
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i
From: Fei Yang
On MTL, GT is no longer allocated on LLC, set has_llc=0.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cddb6e197972..025d32c0b161 100644
---
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CT
-next' into drm-tip
config: sparc-allyesconfig
(https://download.01.org/0day-ci/archive/20230416/202304162325.yltnxysy-...@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/mak
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, April 5, 2023 12:50 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Sharma, Swati2
> ; Kandpal, Suraj
> Subject: [PATCH v2] drm/i915/display: Increase AUX timeout for Type-C
>
> Type-C PHYs are taking longer t
> From: Alex Williamson
> Sent: Saturday, April 15, 2023 1:11 AM
>
> On Fri, 14 Apr 2023 11:38:24 +
> "Liu, Yi L" wrote:
>
> > > From: Tian, Kevin
> > > Sent: Friday, April 14, 2023 5:12 PM
> > >
> > > > From: Alex Williamson
> > > > Sent: Friday, April 14, 2023 2:07 AM
> > > >
> > > > We
== Series Details ==
Series: drm/i915: Make IRQ reset and postinstall multi-gt aware (rev3)
URL : https://patchwork.freedesktop.org/series/115465/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13017_full -> Patchwork_115465v3_full
==
== Series Details ==
Series: drm/i915: Make IRQ reset and postinstall multi-gt aware (rev3)
URL : https://patchwork.freedesktop.org/series/115465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13017 -> Patchwork_115465v3
Su
In multi-gt systems IRQs need to be reset and enabled per GT.
This might add some redundancy when handling interrupts for
engines that might not exist in every tile, but helps to keep the
code cleaner and more understandable.
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
---
Hi,
Following the m
== Series Details ==
Series: Prepare for MTL sagv config patches
URL : https://patchwork.freedesktop.org/series/116541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13016_full -> Patchwork_116541v1_full
Summary
---
== Series Details ==
Series: Prepare for MTL sagv config patches
URL : https://patchwork.freedesktop.org/series/116541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13016 -> Patchwork_116541v1
Summary
---
**SUCCESS*
== Series Details ==
Series: Prepare for MTL sagv config patches
URL : https://patchwork.freedesktop.org/series/116541/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
ci/archive/20230416/202304162325.yltnxysy-...@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git remote a
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 7 +--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i91
In MTL sagv configuration differs from the previous platforms.
Modify sagv configuration part so that MTL specific code
variation can be added easily and also fix some issues observed
in current sagv configuration,
Vinod Govindapillai (4):
drm/i915: fix the derating percentage for MTL
drm/i915
01
(https://download.01.org/0day-ci/archive/20230416/202304162307.7pcvuwlb-...@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
#
https://github.com/intel-lab-lkp/li
On Fri, Apr 14, 2023 at 01:59:12PM +0100, broo...@kernel.org wrote:
> Hi all,
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/ttm/ttm_pool.c
>
> between commit:
>
> 23baf831a32c0 ("mm, treewide: redefine MAX_ORDER sanely")
>
> from the mm-stable tre
On Fri, Apr 14, 2023 at 07:52:12PM +0900, Tetsuo Handa wrote:
> On 2023/04/14 19:13, Jani Nikula wrote:
> > On Fri, 14 Apr 2023, Tetsuo Handa
> > wrote:
> >> On 2023/03/15 19:47, Luca Coelho wrote:
> >>> On Tue, 2023-03-14 at 20:21 +0900, Tetsuo Handa wrote:
> Like commit c4f135d643823a86 ("
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