> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, March 16, 2023 2:59 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Shankar, Uma
> ; Kandpal, Suraj
> Subject: [PATCH v13 0/6] Enable HDCP2.x via GSC CS
>
> These patches enable HDCP2.x on machines MTL an
== Series Details ==
Series: drm/i915/pxp: limit drm-errors or warning on firmware API failures
(rev3)
URL : https://patchwork.freedesktop.org/series/113680/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12902 -> Patchwork_113680v3
> From: Jason Gunthorpe
> Sent: Wednesday, March 22, 2023 9:43 PM
>
> On Wed, Mar 22, 2023 at 01:33:09PM +, Liu, Yi L wrote:
>
> > Thanks. So this new _INFO only reports a limited scope instead of
> > the full list of affected devices. Also, it is not static scope since device
> > may be ope
== Series Details ==
Series: Improvements to GuC load failure handling (rev3)
URL : https://patchwork.freedesktop.org/series/114168/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12902 -> Patchwork_114168v3
Summary
---
MESA driver is creating protected context on every driver handle
creation to query caps bits for app. So when running CI tests,
they are observing hundreds of drm_errors when enabling PXP
in .config but using SOC fusing or BIOS configuration that cannot
support PXP sessions.
The fixes tag referenc
== Series Details ==
Series: Improvements to GuC load failure handling (rev3)
URL : https://patchwork.freedesktop.org/series/114168/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Improvements to GuC load failure handling (rev3)
URL : https://patchwork.freedesktop.org/series/114168/
State : warning
== Summary ==
Error: dim checkpatch failed
b4df7f16c846 drm/i915/guc: Improve GuC load error reporting
2be0fcf3087c drm/i915/guc: Allow for very
On Mar 22, 2023, Rodrigo Vivi wrote:
> On Sun, Mar 12, 2023 at 04:56:23PM -0300, Alexandre Oliva wrote:
>>
> Since __uc_fw_auto_select is also called from another place,
> intel_uc_fw_init_early
> out of the intel_uc_fw_fetch infinite loop,
That other place is conceptually, sort of, the first i
On Fri, 2023-03-17 at 13:37 +0200, Tamminen, Eero T wrote:
> Hi,
>
> On 16.3.2023 10.50, Tvrtko Ursulin wrote:
> > > [ 11.674183] i915 :00:02.0: PXP init-arb-session-15 failed due
> > > to BIOS/SOC:0x101a:ERR_PLATFORM_CONFIG
> ...
> > Alan - is this expected during normal operation on s
Hi,
> On 3/22/2023 12:44 PM, John Harrison wrote:
> > On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
> > > Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to
> > > always hit the GDRST register twice when doing a reset, with the
> > > reported aim to fix invalid post-reset en
Hi Bjorn,
On Wed, 2023-03-22 at 15:57 -0500, Bjorn Helgaas wrote:
> On Wed, Mar 22, 2023 at 03:45:01PM -0500, Bjorn Helgaas wrote:
> > Hi David,
> >
> > On Tue, Mar 21, 2023 at 04:38:49PM -0700, David E. Box wrote:
> > > The VMD driver calls pci_enabled_link_state as a callback from
> > > pci_bus
On Wed, Mar 22, 2023 at 11:22:56PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 22, 2023 at 04:36:09PM -0400, Rodrigo Vivi wrote:
> > On Wed, Mar 22, 2023 at 08:12:19PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Currently we have no sane way to forcibly disable SAGV, which
> >
On Wed, Mar 22, 2023 at 04:36:09PM -0400, Rodrigo Vivi wrote:
> On Wed, Mar 22, 2023 at 08:12:19PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we have no sane way to forcibly disable SAGV, which
> > makes debugging things a PITA. Manually poking at the pcode
> > mailbox
On 3/16/2023 3:06 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the GuC is occasionally observed where the GuC log
actually showed that the GuC had loaded just fine. The implication
being that the load just took ever so slightly longer than the 200ms
timeout. Giv
On 3/22/2023 13:59, Ceraolo Spurio, Daniele wrote:
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
The WA states that we need to alert the GSC FW before doing a GSC
engine
reset and then wait for 200ms. The GuC owns engine reset, so on the
i915
si
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to
always hit the GDRST register twice when doing a reset, with the
reported aim to fix invalid post-reset engine state on some plat
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
The WA states that we need to alert the GSC FW before doing a GSC engine
reset and then wait for 200ms. The GuC owns engine reset, so on the i915
side we only need to apply this for full GT reset.
G
On Wed, Mar 22, 2023 at 03:45:01PM -0500, Bjorn Helgaas wrote:
> Hi David,
>
> On Tue, Mar 21, 2023 at 04:38:49PM -0700, David E. Box wrote:
> > The VMD driver calls pci_enabled_link_state as a callback from
> > pci_bus_walk. Both will acquire the pci_bus_sem lock leading to a lockdep
> > warning.
On Sun, Mar 12, 2023 at 04:56:23PM -0300, Alexandre Oliva wrote:
>
> If two or more suitable entries with the same filename are found in
> __uc_fw_auto_select's fw_blobs, and that filename fails to load in the
> first attempt and in the retry, when __uc_fw_auto_select is called for
> the third tim
Hi David,
On Tue, Mar 21, 2023 at 04:38:49PM -0700, David E. Box wrote:
> The VMD driver calls pci_enabled_link_state as a callback from
> pci_bus_walk. Both will acquire the pci_bus_sem lock leading to a lockdep
> warning. Add an argument to pci_enable_link_state to set whether the lock
> should
On Wed, Mar 22, 2023 at 08:12:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we have no sane way to forcibly disable SAGV, which
> makes debugging things a PITA. Manually poking at the pcode
> mailbox with it's various SAGV/QGV/PSF formats is no fun,
> and likely to be clobb
== Series Details ==
Series: Correction to QGV related register addresses (rev2)
URL : https://patchwork.freedesktop.org/series/115473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12897_full -> Patchwork_115473v2_full
Sum
On 21.03.23 14:12, Greg Kroah-Hartman wrote:
On Tue, Mar 21, 2023 at 07:58:44AM +0700, Philip Müller wrote:
On 20.03.23 20:28, Greg Kroah-Hartman wrote:
On Sun, Mar 19, 2023 at 10:01:01AM +0700, Philip Müller wrote:
Have to correct the affected kernels to these: 4.14.310, 4.19.278, 5.4.237,
5.
On 20.03.23 20:28, Greg Kroah-Hartman wrote:
On Sun, Mar 19, 2023 at 10:01:01AM +0700, Philip Müller wrote:
Have to correct the affected kernels to these: 4.14.310, 4.19.278, 5.4.237,
5.10.175
Please don't top-post :(
Anyway, should be fixed in the next round of releases in a few days, if
not
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to
always hit the GDRST register twice when doing a reset, with the
reported aim to fix invalid post-reset engine state on some platforms
(Jasperlake being the only one actually me
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
The WA states that we need to alert the GSC FW before doing a GSC engine
reset and then wait for 200ms. The GuC owns engine reset, so on the i915
side we only need to apply this for full GT reset.
Given that we do full GT resets in the resume pat
== Series Details ==
Series: drm/i915: Add i915.enable_sagv modparam
URL : https://patchwork.freedesktop.org/series/115523/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12898 -> Patchwork_115523v1
Summary
---
**FAIL
On Wed, Mar 22, 2023 at 03:07:44PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tc: Fix a few TypeC / MST issues (rev6)
> URL : https://patchwork.freedesktop.org/series/115270/
> State : success
Thanks for the reviews, the patchset is pushed to din.
> == Summary ==
>
>
On Wed, Mar 22, 2023 at 09:11:15AM +, Patchwork wrote:
Patch Details
Series: Add OAM support for MTL
URL: [1]https://patchwork.freedesktop.org/series/115469/
State: failure
Details:
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115469v1/index.html
CI Bug Log - changes
== Series Details ==
Series: drm/i915: Add i915.enable_sagv modparam
URL : https://patchwork.freedesktop.org/series/115523/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Add i915.enable_sagv modparam
URL : https://patchwork.freedesktop.org/series/115523/
State : warning
== Summary ==
Error: dim checkpatch failed
0c284872ae1b drm/i915: Add i915.enable_sagv modparam
-:49: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match
== Series Details ==
Series: High refresh rate PSR fixes (rev5)
URL : https://patchwork.freedesktop.org/series/115109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12897_full -> Patchwork_115109v5_full
Summary
---
*
From: Ville Syrjälä
Currently we have no sane way to forcibly disable SAGV, which
makes debugging things a PITA. Manually poking at the pcode
mailbox with it's various SAGV/QGV/PSF formats is no fun,
and likely to be clobbered by the driver anyway.
Let's add a modparam for this.
Signed-off-by:
On Wed, Mar 22, 2023 at 05:15:56PM +0200, Juha-Pekka Heikkila wrote:
> Set look all ok,
>
> Reviewed-by: Juha-Pekka Heikkila
Thanks.
>
> I guess should start to think about how to write igt tests which would
> target directly at dpt so this kind of issues wouldn't get missed.
Yeah, I was alr
== Series Details ==
Series: Correction to QGV related register addresses (rev2)
URL : https://patchwork.freedesktop.org/series/115473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12897 -> Patchwork_115473v2
Summary
-
== Series Details ==
Series: Correction to QGV related register addresses (rev2)
URL : https://patchwork.freedesktop.org/series/115473/
State : warning
== Summary ==
Error: dim checkpatch failed
fb0563a71e40 drm/i915/reg: fix QGV points register access offsets
-:26: WARNING:LONG_LINE: line len
Set look all ok,
Reviewed-by: Juha-Pekka Heikkila
I guess should start to think about how to write igt tests which would
target directly at dpt so this kind of issues wouldn't get missed.
/Juha-Pekka
On 20.3.2023 11.05, Ville Syrjala wrote:
From: Ville Syrjälä
Avoid the shrinker evicting
On Wed, Mar 22, 2023 at 04:20:50PM +0200, Vinod Govindapillai wrote:
> Wrong offsets are calculated to read QGV point registers. Fix it
> to read from the correct registers.
>
> v2: Avoid magic number and better handling the second bitgroup
>
> Bspec: 64602
>
> Signed-off-by: Vinod Govindapillai
On 2023-03-08 at 05:28:44 -0800, Yi Liu wrote:
> This defines KVM_DEV_VFIO_FILE* and make alias with KVM_DEV_VFIO_GROUP*.
> Old userspace uses KVM_DEV_VFIO_GROUP* works as well.
>
> Signed-off-by: Yi Liu
> Reviewed-by: Jason Gunthorpe
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested
Wrong register address is used to read the SAG block time. Fix
the register address according to the bspec.
Bspec: 64608
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
Wrong offsets are calculated to read QGV point registers. Fix it
to read from the correct registers.
v2: Avoid magic number and better handling the second bitgroup
Bspec: 64602
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
1
Wrong offsets are calculated to read QGV points from mem ss. Also
a wrong register address is used to get the dagv block time. Fix
these two issues.
Vinod Govindapillai (2):
drm/i915/reg: fix QGV points register access offsets
drm/i915/reg: use the correct register to access SAGV block time
On Wed, Mar 22, 2023 at 03:01:38AM +0200, Vinod Govindapillai wrote:
> Wrong register address is used to read the SAG block time. Fix
> the register address according to the bspec.
>
> Bspec: 64608
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file c
== Series Details ==
Series: High refresh rate PSR fixes (rev5)
URL : https://patchwork.freedesktop.org/series/115109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12897 -> Patchwork_115109v5
Summary
---
**SUCCESS**
Am 22.03.23 um 12:58 schrieb Jani Nikula:
On Thu, 16 Mar 2023, Patchwork wrote:
== Series Details ==
Series: series starting with [1/7] drm: remove drm_dev_set_unique
URL : https://patchwork.freedesktop.org/series/115239/
State : failure
== Summary ==
Error: patch
https://patchwork.freede
On Wed, Mar 22, 2023 at 01:33:09PM +, Liu, Yi L wrote:
> Thanks. So this new _INFO only reports a limited scope instead of
> the full list of affected devices. Also, it is not static scope since device
> may be opened just after the _INFO returns.
Yes, it would be simplest for qemu to do the
== Series Details ==
Series: High refresh rate PSR fixes (rev5)
URL : https://patchwork.freedesktop.org/series/115109/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1:
== Series Details ==
Series: High refresh rate PSR fixes (rev5)
URL : https://patchwork.freedesktop.org/series/115109/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/115109/revisions/5/mbox/ not
found
> From: Jason Gunthorpe
> Sent: Wednesday, March 22, 2023 8:18 PM
>
> On Wed, Mar 22, 2023 at 08:17:54AM +, Liu, Yi L wrote:
>
> > Could you elaborate what is required with _INFO before libvirt can
> > use a FD pass?
>
> Make a new _INFO that returns an array of dev_ids within the cdev's
> i
On Wed, Mar 22, 2023 at 06:36:14AM -0600, Alex Williamson wrote:
> On Wed, 22 Mar 2023 09:27:16 -0300
> Jason Gunthorpe wrote:
>
> > On Tue, Mar 21, 2023 at 04:47:37PM -0600, Alex Williamson wrote:
> > > On Tue, 21 Mar 2023 19:20:37 -0300
> > > Jason Gunthorpe wrote:
> > >
> > > > On Tue, Mar
On Wed, 22 Mar 2023 09:27:16 -0300
Jason Gunthorpe wrote:
> On Tue, Mar 21, 2023 at 04:47:37PM -0600, Alex Williamson wrote:
> > On Tue, 21 Mar 2023 19:20:37 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Tue, Mar 21, 2023 at 03:01:12PM -0600, Alex Williamson wrote:
> > >
> > > > > Though i
On Tue, Mar 21, 2023 at 04:47:37PM -0600, Alex Williamson wrote:
> On Tue, 21 Mar 2023 19:20:37 -0300
> Jason Gunthorpe wrote:
>
> > On Tue, Mar 21, 2023 at 03:01:12PM -0600, Alex Williamson wrote:
> >
> > > > Though it would be nice if qemu didn't need two implementations so Yi
> > > > I'd rath
On Wed, 22 Mar 2023 04:42:16 +
"Liu, Yi L" wrote:
> > From: Alex Williamson
> > Sent: Wednesday, March 22, 2023 6:48 AM
> >
> > On Tue, 21 Mar 2023 19:20:37 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Tue, Mar 21, 2023 at 03:01:12PM -0600, Alex Williamson wrote:
> > >
> > > > > Thou
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev2)
URL : https://patchwork.freedesktop.org/series/115371/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12895 -> Patchwork_115371v2
===
On Wed, Mar 22, 2023 at 08:17:54AM +, Liu, Yi L wrote:
> Could you elaborate what is required with _INFO before libvirt can
> use a FD pass?
Make a new _INFO that returns an array of dev_ids within the cdev's
iommufd_ctx that are part of the reset group, eg the devset.
qemu will call this fo
On Wed, Mar 22, 2023 at 12:19:26PM +0100, Andrzej Hajda wrote:
> On 16.03.2023 14:17, Imre Deak wrote:
> > On TC ports the 4ms AUX timeout combined with the 5 * 32 retry
> > attempts during DPCD accesses adds a 640ms delay to each access if the
> > sink is disconnected. This in turn slows down a mo
On Thu, 16 Mar 2023, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/7] drm: remove drm_dev_set_unique
> URL : https://patchwork.freedesktop.org/series/115239/
> State : failure
>
> == Summary ==
>
> Error: patch
> https://patchwork.freedesktop.org/api/1.0/series/115
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev2)
URL : https://patchwork.freedesktop.org/series/115371/
State : warning
== Summary ==
Error: git fetch origin failed
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev2)
URL : https://patchwork.freedesktop.org/series/115371/
State : warning
== Summary ==
Error: dim checkpatch failed
c32b9b91ef02 drm/i915/display: Communicate display power demands to pcode
-:9: WARN
== Series Details ==
Series: drm/i915/display: Communicate display power demands to pcode (rev2)
URL : https://patchwork.freedesktop.org/series/115371/
State : warning
== Summary ==
Error: git fetch origin failed
On Thu, Mar 16, 2023 at 09:20:28AM +0100, Christian König wrote:
> Hi guys,
>
> I've messed up the last send out. Cleanup up some issues reported by people
> with the accel drivers (duplicated files) and rebased the result.
>
> Apart from that the same approach we already discussed previously.
On 16.03.2023 14:17, Imre Deak wrote:
On TC ports the 4ms AUX timeout combined with the 5 * 32 retry
attempts during DPCD accesses adds a 640ms delay to each access if the
sink is disconnected. This in turn slows down a modeset during which the
sink is disconnected (for instance a disabling modes
On Thu, Mar 16, 2023 at 09:20:32AM +0100, Christian König wrote:
> Instead of the per minor directories only create a single debugfs
> directory for the whole device directly when the device is initialized.
>
> For DRM devices each minor gets a symlink to the per device directory
> for now until w
pre/post hooks are doing things differently. Unify them.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers
Implement Display WA #1136 for SKL/BXT.
Bspec: 21664
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 17 +
drivers/gpu/drm/i915/display/skl_watermark.c | 5 -
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i9
Ensure vblank >= psr2 vblank
where
Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
Bspec: 71580, 49274
v2: Use calculated block count number maximum line count
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +
1 file changed, 9 insertions(+
Wa_16013835468 is a separate from Wa_14015648006 and needs to be
applied for TGL onwards. Fix this by removing all the references to
Wa_14015648006 and apply Wa_16013835468 according to Bspec.
Also move workaround into separate function as a preparation for
Wa_14015648006 implementation. Apply thi
PSR WM optimization should be disabled based on any wm level being
disabled. Also same WA should be applied for ICL as well.
Bspec: 71580
v3
- Split patch
v2
- set/clear chicken bit in post_plane_update
- apply for ICL as well
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/i
Fix/adjust Wa_16013835468 and implement Wa_14015648006. Implement Wa_1136 and
check for vblank being long enough for psr2.
v5:
- Add missing patch
v4:
- Keep/fix Wa_16013835468
- Use calculated block count number instead of fixed 12
v3:
- apply Wa_16013835468 for icl as well
- set/clear chick
Implement Display WA #1136 for SKL/BXT.
Bspec: 21664
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 17 +
drivers/gpu/drm/i915/display/skl_watermark.c | 5 -
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i9
Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers
Ensure vblank >= psr2 vblank
where
Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
Bspec: 71580, 49274
v2: Use calculated block count number maximum line count
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +
1 file changed, 9 insertions(+
PSR WM optimization should be disabled based on any wm level being
disabled. Also same WA should be applied for ICL as well.
Bspec: 71580
v3
- Split patch
v2
- set/clear chicken bit in post_plane_update
- apply for ICL as well
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/i
Wa_16013835468 is a separate from Wa_14015648006 and needs to be
applied for TGL onwards. Fix this by removing all the references to
Wa_14015648006 and apply Wa_16013835468 according to Bspec.
Also move workaround into separate function as a preparation for
Wa_14015648006 implementation. Apply thi
Fix/adjust Wa_16013835468 and implement Wa_14015648006. Implement Wa_1136 and
check for vblank being long enough for psr2.
v4:
- Keep/fix Wa_16013835468
- Use calculated block count number instead of fixed 12
v3:
- apply Wa_16013835468 for icl as well
- set/clear chicken bit in post plane upda
== Series Details ==
Series: drm/i915/tc: Fix a few TypeC / MST issues (rev6)
URL : https://patchwork.freedesktop.org/series/115270/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12893 -> Patchwork_115270v6
Summary
---
== Series Details ==
Series: Correction to QGV related register addresses
URL : https://patchwork.freedesktop.org/series/115473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12893_full -> Patchwork_115473v1_full
Summary
--
== Series Details ==
Series: drm/i915/tc: Fix a few TypeC / MST issues (rev6)
URL : https://patchwork.freedesktop.org/series/115270/
State : warning
== Summary ==
Error: git fetch origin failed
== Series Details ==
Series: drm/i915/tc: Fix a few TypeC / MST issues (rev6)
URL : https://patchwork.freedesktop.org/series/115270/
State : warning
== Summary ==
Error: git fetch origin failed
== Series Details ==
Series: drm/i915/tc: Fix a few TypeC / MST issues (rev6)
URL : https://patchwork.freedesktop.org/series/115270/
State : warning
== Summary ==
Error: dim checkpatch failed
396311312b37 drm/i915/tc: Abort DP AUX transfer on a disconnected TC port
-:19: WARNING:BAD_REPORTED_B
== Series Details ==
Series: drm/i915: Use i915 instead of dev_priv insied the file_priv structure
URL : https://patchwork.freedesktop.org/series/115471/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12893_full -> Patchwork_115471v1_full
===
== Series Details ==
Series: Add OAM support for MTL
URL : https://patchwork.freedesktop.org/series/115469/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12893_full -> Patchwork_115469v1_full
Summary
---
**FAILURE**
On 21.03.2023 18:09, Andi Shyti wrote:
From: Matt Roper
Although we now sanitycheck MMIO access during driver load to make sure
the MMIO BAR isn't returning all 0x, there have been a few cases
where (temporarily?) unreliable MMIO access has happened after GPU
resets or power events. We
== Series Details ==
Series: PCI/ASPM: pci_enable_link_state: Add argument to acquire bus lock
URL : https://patchwork.freedesktop.org/series/115466/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12893_full -> Patchwork_115466v1_full
===
On 22.03.2023 01:16, Andi Shyti wrote:
In the process of renaming all instances of 'dev_priv' to 'i915',
start using 'i915' within the 'drm_i915_file_private' structure.
Signed-off-by: Andi Shyti
Apparently the last struct member with this name, R.I.P.
Reviewed-by: Andrzej Hajda
Regards
An
On 21.03.2023 23:43, Andi Shyti wrote:
Hi Matt,
We occasionally see the PCI device in a non-accessible state at the
point the driver is loaded. When this happens, all BAR accesses will
read back as 0x. Rather than reading registers and
misinterpreting their (invalid) values, let's spe
On Wed, Mar 22, 2023 at 03:01:38AM +0200, Vinod Govindapillai wrote:
> Wrong register address is used to read the SAG block time. Fix
> the register address according to the bspec.
>
> Bspec: 64608
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file c
On Wed, Mar 22, 2023 at 03:01:37AM +0200, Vinod Govindapillai wrote:
> Wrong offsets are calculated to read QGV point registers. Fix it
> to read from the correct registers.
>
> Bspec: 64602
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file change
> From: Jason Gunthorpe
> Sent: Wednesday, March 22, 2023 4:50 AM
>
> On Tue, Mar 21, 2023 at 02:31:22PM -0600, Alex Williamson wrote:
>
> > This just seems like nit-picking that the API could have accomplished
> > this more concisely. Probably that's true, but I think you've
> > identified a g
== Series Details ==
Series: drm/i915: Make IRQ reset and postinstall multi-gt aware
URL : https://patchwork.freedesktop.org/series/115465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12890_full -> Patchwork_115465v1_full
== Series Details ==
Series: Report MMIO communication problems more clearly (rev2)
URL : https://patchwork.freedesktop.org/series/115421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12890_full -> Patchwork_115421v2_full
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