Re: [Intel-gfx] [PATCH 3/4] drm/i915/mtl: Define new PTE encode for MTL

On 07-12-2022 05:09, Matt Roper wrote: > On Tue, Dec 06, 2022 at 01:07:28PM +0530, Aravind Iddamsetty wrote: >> Add a separate PTE encode function for MTL. The number of PAT registers >> have increased to 16 on MTL. All 16 PAT registers are available for >> PPGTT mapped pages, but only the lower

[Intel-gfx] ✓ Fi.CI.BAT: success for Add hwmon support for dgfx selftests (rev6)

== Series Details == Series: Add hwmon support for dgfx selftests (rev6) URL : https://patchwork.freedesktop.org/series/109850/ State : success == Summary == CI Bug Log - changes from CI_DRM_12476 -> Patchwork_109850v6 Summary --- **

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add hwmon support for dgfx selftests (rev6)

== Series Details == Series: Add hwmon support for dgfx selftests (rev6) URL : https://patchwork.freedesktop.org/series/109850/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./arch/x86/include/asm/bitop

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add hwmon support for dgfx selftests (rev6)

== Series Details == Series: Add hwmon support for dgfx selftests (rev6) URL : https://patchwork.freedesktop.org/series/109850/ State : warning == Summary == Error: dim checkpatch failed 6fd24b4b6090 drm/i915/selftests: Rename librapl library to libpower Traceback (most recent call last): Fi

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Reference pte_encode through vm pointer

On 07-12-2022 04:21, Matt Roper wrote: > On Tue, Dec 06, 2022 at 01:07:27PM +0530, Aravind Iddamsetty wrote: >> New platforms will use different encode functions. > > You may want to elaborate slightly. E.g., something like > > "Future patches will introduce new platform-specific page table e

Re: [Intel-gfx] [PATCH 1/4] drm/i915/mtl: Define MOCS and PAT tables for MTL

On 07-12-2022 00:09, Lucas De Marchi wrote: > On Tue, Dec 06, 2022 at 01:38:53PM +0530, Iddamsetty, Aravind wrote: >> please ignore this series will be sending a new one. some how patchwork >> didn't pick up this neatly. > > Patchwork makes a mess if you do --in-reply-to like you are doing. > A

Re: [Intel-gfx] [Intel-gfx 4/6] drm/i915/guc: Provide debugfs for log relay sub-buf info

On Mon, 05 Dec 2022 17:55:20 -0800, Teres Alexis, Alan Previn wrote: > Hi Alan, > It's been a while - trying to resurrect this now. > > On Tue, 2022-07-19 at 20:40 -0700, Dixit, Ashutosh wrote: > > On Mon, 09 May 2022 14:01:49 -0700, Alan Previn wrote: > > > > > > > Alan: [snip] > > > > +#define

Re: [Intel-gfx] [PATCH 03/13] drm/i915: Define skl+ palette anti-collision bit

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 23, 2022 8:56 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 03/13] drm/i915: Define skl+ palette > anti-collision bit > > From: Ville Syrjälä > > I've been frobbi

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915/hwmon: Add hwmon support in libpower for dgfx

On 12/7/2022 10:56 AM, Dixit, Ashutosh wrote: On Tue, 06 Dec 2022 21:17:46 -0800, Riana Tauro wrote: diff --git a/drivers/gpu/drm/i915/selftests/libpower.c b/drivers/gpu/drm/i915/selftests/libpower.c index c66e993c5f85..3d4d2dc74a54 100644 --- a/drivers/gpu/drm/i915/selftests/libpower.c +++

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915/hwmon: Add hwmon support in libpower for dgfx

On Tue, 06 Dec 2022 21:17:46 -0800, Riana Tauro wrote: > > diff --git a/drivers/gpu/drm/i915/selftests/libpower.c > b/drivers/gpu/drm/i915/selftests/libpower.c > index c66e993c5f85..3d4d2dc74a54 100644 > --- a/drivers/gpu/drm/i915/selftests/libpower.c > +++ b/drivers/gpu/drm/i915/selftests/libpowe

Re: [Intel-gfx] [PATCH 01/13] drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit

> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, November 23, 2022 8:56 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 01/13] drm/i915: Shorten > GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bit > > From: Ville Syrjälä > > s/GA

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hwmon: Silence "mailbox access failed" warning in snb_pcode_read (rev2)

On 12/6/2022 1:00 AM, Patchwork wrote: *Patch Details* *Series:* drm/i915/hwmon: Silence "mailbox access failed" warning in snb_pcode_read (rev2) *URL:* https://patchwork.freedesktop.org/series/111599/ *State:*failure *Details:* ht

Re: [Intel-gfx] [PATCHv2] drm/i915/dp: Change aux_ctl reg read to polling read

> -Original Message- > From: Nikula, Jani > Sent: Monday, December 5, 2022 4:08 PM > To: Murthy, Arun R ; intel- > g...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Deak, Imre > > Cc: Murthy, Arun R > Subject: Re: [PATCHv2] drm/i915/dp: Change aux_ctl reg read to polling read >

[Intel-gfx] [PATCH v6 2/3] drm/i915/hwmon: Add hwmon support in libpower for dgfx

Add an interface to obtain hwmon energy values. The function returns per-gt energy if gt level energy is available else returns the package level energy if there is a single gt. Use this function in libpower to verify power consumption in different subtests v2 : use i915_hwmon prefix (Anshuman) v

[Intel-gfx] [PATCH v6 0/3] Add hwmon support for dgfx selftests

Rename librapl library to libpower. Add hwmon support in libpower for dgfx. Use libpower in selftests. Rev2 : Update commit message Rev3 : Remove redundant code Rev4 : Add hwmon per-gt support Rev5 : No functional changes. Change author for last patch Rev6 : re-order libpower library patc

[Intel-gfx] [PATCH v6 1/3] drm/i915/selftests: Rename librapl library to libpower

Rename librapl files to libpower and replace librapl with libpower prefix. No functional changes v2: update commit message (Anshuman) Signed-off-by: Riana Tauro Reviewed-by: Anshuman Gupta Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm

[Intel-gfx] [PATCH v6 3/3] drm/i915/selftests: use libpower to get power consumption

From: Tilak Tangudu use libpower library to verify power consumption values in selftests. v2: add per-gt hwmon support (Ashutosh) v3: remove libpower changes (Ashutosh) Signed-off-by: Tilak Tangudu Co-developed-by: Riana Tauro Signed-off-by: Riana Tauro Reviewed-by: Anshuman Gupta Reviewed-

Re: [Intel-gfx] [PATCH] drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries

On 12/6/2022 3:49 PM, Andrzej Hajda wrote: CSB FIFOs stores 64-bit Context Status Buffers used by GuC firmware. They are accessed by 32-bit register. Reads must occur in pairs to obtain a single 64-bit CSB entry. The second read pops the CSB entry off the FIFO. In case GuC reset happens betwee

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries

== Series Details == Series: drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries URL : https://patchwork.freedesktop.org/series/111697/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12475 -> Patchwork_111697v1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries

== Series Details == Series: drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries URL : https://patchwork.freedesktop.org/series/111697/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

== Series Details == Series: series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915 URL : https://patchwork.freedesktop.org/series/111693/ State : success == Summary == CI Bug Log - changes from CI_DRM_12475_full -> Patchwork_111693v1_full

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl/UAPI: Disable GET/SET_CACHING IOCTL for MTL+

On Tue, Dec 06, 2022 at 03:49:15PM -0800, Matt Roper wrote: > On Tue, Dec 06, 2022 at 01:57:39PM +0530, Aravind Iddamsetty wrote: > > From: Pallavi Mishra > > > > It's a noop on all new platforms starting from MTL. > > To me, saying "it's a noop" implies that the ioctl will succeed and > silentl

[Intel-gfx] [PATCH] drm/i915/guc: ensure CSB FIFOs after GuC reset do not have odd entries

CSB FIFOs stores 64-bit Context Status Buffers used by GuC firmware. They are accessed by 32-bit register. Reads must occur in pairs to obtain a single 64-bit CSB entry. The second read pops the CSB entry off the FIFO. In case GuC reset happens between the reads, FIFO must be read once, to recover

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl/UAPI: Disable GET/SET_CACHING IOCTL for MTL+

On Tue, Dec 06, 2022 at 01:57:39PM +0530, Aravind Iddamsetty wrote: > From: Pallavi Mishra > > It's a noop on all new platforms starting from MTL. To me, saying "it's a noop" implies that the ioctl will succeed and silently do nothing, which isn't the case in this patch. We're explicitly reject

Re: [Intel-gfx] [PATCH 3/4] drm/i915/mtl: Define new PTE encode for MTL

On Tue, Dec 06, 2022 at 01:07:28PM +0530, Aravind Iddamsetty wrote: > Add a separate PTE encode function for MTL. The number of PAT registers > have increased to 16 on MTL. All 16 PAT registers are available for > PPGTT mapped pages, but only the lower 4 are available for GGTT mapped > pages. > >

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Reference pte_encode through vm pointer

On Tue, Dec 06, 2022 at 01:07:27PM +0530, Aravind Iddamsetty wrote: > New platforms will use different encode functions. You may want to elaborate slightly. E.g., something like "Future patches will introduce new platform-specific page table entry encoding functions. Existing PTE encoding calls

Re: [Intel-gfx] [PATCH 1/4] drm/i915/mtl: Define MOCS and PAT tables for MTL

On Tue, Dec 06, 2022 at 01:07:26PM +0530, Aravind Iddamsetty wrote: > From: Madhumitha Tolakanahalli Pradeep > > > On MTL due to the introduction of L4 cache, coherency and cacheability > selections are different and also GT can no longer allocate on LLC. The > MOCS/PAT tables needs an update. >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

== Series Details == Series: series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915 URL : https://patchwork.freedesktop.org/series/111693/ State : success == Summary == CI Bug Log - changes from CI_DRM_12475 -> Patchwork_111693v1 ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

== Series Details == Series: series starting with [v10,1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915 URL : https://patchwork.freedesktop.org/series/111693/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checke

[Intel-gfx] [PATCH v10 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

Starting with MTL, there will be two GT-tiles, a render and media tile. PXP as a service for supporting workloads with protected contexts and protected buffers can be subscribed by process workloads on any tile. However, depending on the platform, only one of the t iles is used for control events p

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/guc: Add unaligned wc memcpy for copying GuC Log

will have to get back on this - but it will be tied to a specific GuC version as opposed to a platform. On Tue, 2022-12-06 at 10:14 +, Tvrtko Ursulin wrote: > On 06/12/2022 09:20, Alan Previn wrote: > > Add usage of unaligned wc mempy in read_update_log_buffer > > as newer formats of GuC debu

Re: [Intel-gfx] [PATCH v9 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

Apologies, ignore this - typo on rev count - will resend with proper v10 subject (and cancel CI) On Tue, 2022-12-06 at 13:27 -0800, Teres Alexis, Alan Previn wrote: > Starting with MTL, there will be two GT-tiles, a render and media > tile. PXP as a service for supporting workloads with protected

[Intel-gfx] [PATCH v9 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

Starting with MTL, there will be two GT-tiles, a render and media tile. PXP as a service for supporting workloads with protected contexts and protected buffers can be subscribed by process workloads on any tile. However, depending on the platform, only one of the tiles is used for control events pe

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: improve the catch-all evict to handle lock contention

== Series Details == Series: drm/i915: improve the catch-all evict to handle lock contention URL : https://patchwork.freedesktop.org/series/111686/ State : success == Summary == CI Bug Log - changes from CI_DRM_12475_full -> Patchwork_111686v1_full =

Re: [Intel-gfx] [PATCH 1/4] drm/i915/mtl: Define MOCS and PAT tables for MTL

On Tue, Dec 06, 2022 at 01:38:53PM +0530, Iddamsetty, Aravind wrote: please ignore this series will be sending a new one. some how patchwork didn't pick up this neatly. Patchwork makes a mess if you do --in-reply-to like you are doing. As it is now, it's pretty hard to follow the version of eac

Re: [Intel-gfx] [PATCH v9 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

On Mon, 2022-12-05 at 21:06 -0800, Ceraolo Spurio, Daniele wrote: > > On 12/5/2022 4:03 PM, Alan Previn wrote: Alan:[snip] > > @@ -39,18 +45,26 @@ > >* performed via the mei_pxp component module. > >*/ > > > > -struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) > > +bool intel_

Re: [Intel-gfx] [PATCH v9 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

On Tue, 2022-12-06 at 10:04 +, Tvrtko Ursulin wrote: > On 06/12/2022 00:03, Alan Previn wrote: > > Alan: [snip] > > > > > -struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) > > +bool intel_pxp_is_supported(const struct intel_pxp *pxp) > > { > > - return container_of(pxp, struct

Re: [Intel-gfx] [PATCH 7/9] drm/i915: stop using ttm_bo_wait

Am 06.12.22 um 19:03 schrieb Matthew Auld: On 05/12/2022 19:58, Christian König wrote: Am 30.11.22 um 15:06 schrieb Daniel Vetter: On Wed, 30 Nov 2022 at 14:03, Tvrtko Ursulin wrote: On 29/11/2022 18:05, Matthew Auld wrote: On Fri, 25 Nov 2022 at 11:14, Tvrtko Ursulin wrote: + Matt On 25

Re: [Intel-gfx] [PATCH 7/9] drm/i915: stop using ttm_bo_wait

On 05/12/2022 19:58, Christian König wrote: Am 30.11.22 um 15:06 schrieb Daniel Vetter: On Wed, 30 Nov 2022 at 14:03, Tvrtko Ursulin wrote: On 29/11/2022 18:05, Matthew Auld wrote: On Fri, 25 Nov 2022 at 11:14, Tvrtko Ursulin wrote: + Matt On 25/11/2022 10:21, Christian König wrote: TTM i

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Update GuC relay logging debugfs

== Series Details == Series: drm/i915/guc: Update GuC relay logging debugfs URL : https://patchwork.freedesktop.org/series/111678/ State : success == Summary == CI Bug Log - changes from CI_DRM_12474_full -> Patchwork_111678v1_full Summary

Re: [Intel-gfx] [PATCH v8 22/22] drm/i915/vm_bind: Support capture of persistent mappings

On 01/12/2022 18:43, Niranjana Vishwanathapura wrote: On Thu, Dec 01, 2022 at 07:27:31AM -0800, Niranjana Vishwanathapura wrote: On Thu, Dec 01, 2022 at 10:49:15AM +, Matthew Auld wrote: On 29/11/2022 07:26, Niranjana Vishwanathapura wrote: Support dump capture of persistent mappings upon

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: improve the catch-all evict to handle lock contention

== Series Details == Series: drm/i915: improve the catch-all evict to handle lock contention URL : https://patchwork.freedesktop.org/series/111686/ State : success == Summary == CI Bug Log - changes from CI_DRM_12475 -> Patchwork_111686v1 S

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl/UAPI: Disable GET/SET_CACHING IOCTL for MTL+

On Tue, 6 Dec 2022 at 08:13, Aravind Iddamsetty wrote: > > From: Pallavi Mishra > > It's a noop on all new platforms starting from MTL. > Refer: (e7737b67ab46) drm/i915/uapi: reject caching ioctls for discrete > > v2: > 1. block get caching ioctl > 2. return ENODEV similar to DGFX > 3. update the

[Intel-gfx] [Bug report] Null pointer dereference unbinding i915 with gvt enabled

I see this both on the vfio next branch and on the gvt-next branch of https://github.com/intel/gvt-linux. I boot my system with i915.enable_gvt=1 and load the kvmgt module. A vGPU device is automatically created by mdevctl. If I then bind vfio-pci directly to the GPU using 'driverctl --nosave

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915/selftests: exercise emit_pte() with nearly full ring

Hi Matt, On Fri, Dec 02, 2022 at 12:28:44PM +, Matthew Auld wrote: > Simple regression test to check that we don't trample the > rq->reserved_space when returning from emit_pte(), if the ring is nearly > full. > > v2: Make spinner_kill() static > v3: Reduce the ring size further, which should

[Intel-gfx] [PATCH] drm/i915: improve the catch-all evict to handle lock contention

The catch-all evict can fail due to object lock contention, since it only goes as far as trylocking the object, due to us already holding the vm->mutex. Doing a full object lock here can deadlock, since the vm->mutex is always our inner lock. Add another execbuf pass which drops the vm->mutex and t

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915/selftests: use live_subtests for live_migrate

Hi Matt, On Fri, Dec 02, 2022 at 12:28:43PM +, Matthew Auld wrote: > Probably a good idea to do an igt_flush_test() at the end of each > subtest, just to be sure the previous work has been flushed and doesn't > somehow interfere with the current subtest. > > Signed-off-by: Matthew Auld > Cc:

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915/migrate: Account for the reserved_space

Hi Matt, On Fri, Dec 02, 2022 at 12:28:42PM +, Matthew Auld wrote: > From: Chris Wilson > > If the ring is nearly full when calling into emit_pte(), we might > incorrectly trample the reserved_space when constructing the packet to > emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserv

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add DSC fractional bpp support (rev2)

== Series Details == Series: Add DSC fractional bpp support (rev2) URL : https://patchwork.freedesktop.org/series/111391/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12474 -> Patchwork_111391v2 Summary --- **FAILUR

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev2)

== Series Details == Series: Add DSC fractional bpp support (rev2) URL : https://patchwork.freedesktop.org/series/111391/ State : warning == Summary == Error: dim checkpatch failed ca89ce658c84 drm/i915/dp: Check if force dsc bpc <= max requested bpc 1613a598e065 drm/display/dp: Fix the DP DSC

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Update GuC relay logging debugfs

== Series Details == Series: drm/i915/guc: Update GuC relay logging debugfs URL : https://patchwork.freedesktop.org/series/111678/ State : success == Summary == CI Bug Log - changes from CI_DRM_12474 -> Patchwork_111678v1 Summary ---

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915/selftests: use live_subtests for live_migrate

On 02.12.2022 13:28, Matthew Auld wrote: Probably a good idea to do an igt_flush_test() at the end of each subtest, just to be sure the previous work has been flushed and doesn't somehow interfere with the current subtest. Signed-off-by: Matthew Auld Cc: Chris Wilson Cc: Andi Shyti Cc: Andrze

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915/migrate: Account for the reserved_space

Hi, I messed-up with versions, my prev comment landed in v2, so I put it here to clean things up. On 02.12.2022 13:28, Matthew Auld wrote: From: Chris Wilson If the ring is nearly full when calling into emit_pte(), we might incorrectly trample the reserved_space when constructing the packet

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/migrate: Account for the reserved_space

On 18.11.2022 14:57, Matthew Auld wrote: From: Chris Wilson If the ring is nearly full when calling into emit_pte(), we might incorrectly trample the reserved_space when constructing the packet to emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserved_space > ring->space) when later subm

Re: [Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Add GuC CT specific debug print wrappers

On 05/12/2022 18:44, Michal Wajdeczko wrote: On 05.12.2022 14:16, Tvrtko Ursulin wrote: On 02/12/2022 20:14, John Harrison wrote: and while for dbg level messages it doesn't matter, I assume we should be consistent for err/warn/info messages (as those will eventually show up to the end user

[Intel-gfx] [PATCH v1 12/12] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

From: Swati Sharma If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff compressed bpp is fractional. Continue if we computed compressed bpp is computed as integer. Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ 1 file changed, 6 insertions(+

[Intel-gfx] [PATCH v2 10/12] drm/i915/dp: Iterate over output bpp with fractional step size

This patch adds support to iterate over compressed output bpp as per the fractional step, supported by DP sink. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 47 +++-- 1 file cha

[Intel-gfx] [PATCH v1 11/12] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

From: Swati Sharma DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to depict sink's precision. Also, new debugfs entry is created to enforce fractional bpp. If Force_DSC_Fractional_BPP_en is set then while iterating over output bpp with fractional step size we will continue if

[Intel-gfx] [PATCH v1 09/12] drm/i915/dsc/mtl: Add support for fractional bpp

From: Vandita Kulkarni Consider the fractional bpp while reading the qp values. Signed-off-by: Vandita Kulkarni Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 --- drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +--- 2 files changed, 9 inser

[Intel-gfx] [PATCH v1 04/12] drm/i915/dp: Rename helpers to get DSC max pipe bpp and max output bpp

Currently we the required dsc output bpp is set to be the largest compressed bpp supported for max, lane, rate, and bpp. The helper intel_dp_dsc_get_output_bpp gets the maximum supported compressed bpp taking into account link configuration, input bpp, bigjoiner considerations etc. Append 'max' su

[Intel-gfx] [PATCH v2 08/12] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. v2: -Fixed tu_data calculation while dealing with U6.4 format. (Stan) Signed-o

[Intel-gfx] [PATCH v1 06/12] drm/i915/display: Store compressed bpp in U6.4 format

DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp

[Intel-gfx] [PATCH v1 07/12] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v1 03/12] drm/display/dp: Add helper function to get DSC bpp prescision

Add helper to get the DSC bits_per_pixel precision for the DP sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/display/drm_dp_helper.c | 27 + include/drm/display/drm_dp_helper.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/display/dr

[Intel-gfx] [PATCH v2 05/12] drm/i915/dp: Get optimal link config to have best compressed bpp

Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possible. We then set the output bpp to this value. This patch provides support to have max bpp, min rate and min lanes, that can support the min compressed bpp. v2: -Avoid ending up with compressed bpp, same as

[Intel-gfx] [PATCH v2 00/12] Add DSC fractional bpp support

This patch series adds support for having fractional compressed bpp for MTL+. The initial patches that lay groundwork to iterate over valid compressed bpps to select the 'best' compressed bpp with optimal link configuration are taken from upstream pending series: https://patchwork.freedesktop.org/s

[Intel-gfx] [PATCH v1 02/12] drm/display/dp: Fix the DP DSC Receiver cap size

DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. Fix the DSC RECEIVER CAP SIZE accordingly. Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") Cc: Anusha Srivatsa Cc: Manasi Navare Cc: # v5.0+ Reported-by: kernel test robot Signed-off-

[Intel-gfx] [PATCH v1 01/12] drm/i915/dp: Check if force dsc bpc <= max requested bpc

Add a check to use force DSC bpc only if its less that the connector max requested bpc. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 23 ++- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c

Re: [Intel-gfx] [PATCH 07/11] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

On 12/5/2022 1:05 PM, Lisovskiy, Stanislav wrote: On Mon, Nov 28, 2022 at 03:49:18PM +0530, Ankit Nautiyal wrote: MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer u

Re: [Intel-gfx] [PATCH 04/11] drm/i915/dp: Get optimal link config to have best compressed bpp

Hi Stan, Thanks a lot for the reviews and suggestions. Please find my response inline: On 12/5/2022 12:58 PM, Lisovskiy, Stanislav wrote: On Mon, Nov 28, 2022 at 03:49:15PM +0530, Ankit Nautiyal wrote: Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possi

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915/guc: Add unaligned wc memcpy for copying GuC Log

On 06/12/2022 09:20, Alan Previn wrote: Add usage of unaligned wc mempy in read_update_log_buffer as newer formats of GuC debug-log-events are no longer guaranteed to be exactly 4-dwords long per event. If this "newer format" applies to DG2 and GuC log has been "productized" there (as in we

Re: [Intel-gfx] [PATCH v9 1/1] drm/i915/pxp: Promote pxp subsystem to top-level of i915

On 06/12/2022 00:03, Alan Previn wrote: Starting with MTL, there will be two GT-tiles, a render and media tile. PXP as a service for supporting workloads with protected contexts and protected buffers can be subscribed by process workloads on any tile. However, depending on the platform, only on

[Intel-gfx] [PATCH v2 3/5] drm/i915/guc: Provide debugfs for log relay sub-buf info

In order to provide alignment between IGT intel_guc_logger tool and i915 kernel's guc log relay channels without requiring updating both repositories everytime a sizing change is made, provide that info via debugfs files. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c

[Intel-gfx] [PATCH v2 5/5] drm/i915/guc: Move guc_log_relay_chan debugfs path to uc

All other GuC Relay Logging debugfs handles including recent additions are under the 'i915/gt/uc/path' so let's also move 'guc_log_relay_chan' to its proper home. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|

[Intel-gfx] [PATCH v2 4/5] drm/i915/guc: Rename GuC log relay debugfs descriptively

GuC log relay debugfs name for the control handle vs the actual relay channel are vague. Fix them so it's obvious from the name. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 2 +- .../drm/i915/gt/uc/intel_guc_log_debugfs.c| 22 +-- 2 files c

[Intel-gfx] [PATCH v2 2/5] drm/i915/guc: Add unaligned wc memcpy for copying GuC Log

Add usage of unaligned wc mempy in read_update_log_buffer as newer formats of GuC debug-log-events are no longer guaranteed to be exactly 4-dwords long per event. Signed-off-by: Alan Previn Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 9 ++--- 1 file changed,

[Intel-gfx] [PATCH v2 0/5] drm/i915/guc: Update GuC relay logging debugfs

This series 1. Fixes a bug introduced in GuC Error Capture that was sharing the memmap of the multi-region GuC logging buffer. 1. Adds support for unaligned wc memcpy during the copying of logs to relay channel. 2. Renames the debugfs file for controlling GuC relay logging

[Intel-gfx] [PATCH v2 1/5] drm/i915/guc: Fix GuC relay log debugfs failing open

When GuC-Error-Capture was introduced, we created buf_in_use as a way to identify if relay logging had started. It is meant to replace the previous method where a mmap of the GuC log buffer was the indicator but not since GuC Error Capture shares that mapping throughout operation. However, that me

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/gsc: Do a driver-FLR on unload if GSC was loaded

On Mon, Dec 05, 2022 at 05:19:06PM -0800, Daniele Ceraolo Spurio wrote: > If the GSC was loaded, the only way to stop it during the driver unload > flow is to do a driver-FLR. > The driver-initiated FLR is not the same as PCI config space FLR in > that it doesn't reset the SGUnit and doesn't modify

Re: [Intel-gfx] [Intel-gfx 1/6] drm/i915/guc: Fix GuC relay log debugfs failing open

On 06/12/2022 08:32, Tvrtko Ursulin wrote: On 09/05/2022 22:01, Alan Previn wrote: When GuC-Error-Capture was introduced, we created buf_in_use as a way to identify if relay logging had started. It is meant to replace the previous method where a mmap of the GuC log buffer was the indicator bu

Re: [Intel-gfx] [Intel-gfx 1/6] drm/i915/guc: Fix GuC relay log debugfs failing open

On 09/05/2022 22:01, Alan Previn wrote: When GuC-Error-Capture was introduced, we created buf_in_use as a way to identify if relay logging had started. It is meant to replace the previous method where a mmap of the GuC log buffer was the indicator but not since GuC Error Capture shares that map

Re: [Intel-gfx] [PATCH] drm/i915: use sysfs_emit() to instead of scnprintf()

On Mon, Dec 05, 2022 at 12:50:53PM +0200, Jani Nikula wrote: > On Thu, 01 Dec 2022, wrote: > > From: ye xingchen > > > > Replace the open-code with sysfs_emit() to simplify the code. > > I was going to push this, but noticed the function has a third > scnprintf(), and the last two play together

Re: [Intel-gfx] [PATCH 1/4] drm/i915/mtl: Define MOCS and PAT tables for MTL

please ignore this series will be sending a new one. some how patchwork didn't pick up this neatly. Thanks, Aravind. On 06-12-2022 13:07, Aravind Iddamsetty wrote: > From: Madhumitha Tolakanahalli Pradeep > > > On MTL due to the introduction of L4 cache, coherency and cacheability > selections