== Series Details ==
Series: drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types
URL : https://patchwork.freedesktop.org/series/109737/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109737v1_full
===
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_108156v5_full
Summary
-
== Series Details ==
Series: drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types
URL : https://patchwork.freedesktop.org/series/109737/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109737v1
=
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_108156v5
Summary
---
**SU
If GuC is being used and we initialized GuC-error-capture,
we need to be warning if we don't provide an error-capture
register list in the firmware ADS, for valid GT engines.
A warning makes sense as this would impact debugability
without realizing why a reglist wasn't retrieved and reported
by GuC
After initial upstream merge of GuC error-capture feature, we eventually
decided to remove a lot of unnecessary warning messages when we couldn't
retrieve register lists for ADS-error-state-capture initialization. It was
a justified decision because the majority of that noise was being repeated
thr
Add compute reglist for GuC error capture.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 290c1e1343dd..da
On Tue, 20 Sep 2022 01:06:52 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, "Dixit, Ashutosh" wrote:
> > On Mon, 19 Sep 2022 05:13:18 -0700, Jani Nikula wrote:
> >>
> >> On Mon, 19 Sep 2022, Badal Nilawar wrote:
> >> > For MTL SAMedia updated relevant functions and places in the code to get
>
On Mon, 19 Sep 2022 09:49:07 -0700, Andi Shyti wrote:
>
> Hi Badal,
Hi Andi,
Badal is out for a bit so I am sending out this version.
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
>
> can you
On Mon, 19 Sep 2022 15:49:17 -0700, Matt Roper wrote:
>
> On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> > On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > > Updated the CAGF functions to get actual resolved frequency of
> > > 3D and SAMedia
> > >
> > > Bspec: 66300
From: Badal Nilawar
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
Bspec: 66300
Signed-off-by: Ashutosh Dixit
Si
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept register ID's inste
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v2: Included "Use GEN12 RPSTAT register" patch
v3:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v4:
- Included "drm/i915/gt: Change RC6 resi
== Series Details ==
Series: drm/i915/pvc: Update forcewake domain for CCS register ranges
URL : https://patchwork.freedesktop.org/series/109734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109734v1_full
===
== Series Details ==
Series: drm/i915/pvc: Update forcewake domain for CCS register ranges
URL : https://patchwork.freedesktop.org/series/109734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109734v1
Sum
On 10/13/2022 13:32, Daniele Ceraolo Spurio wrote:
We're observing sporadic HuC delayed load timeouts in CI, due to mei_pxp
binding completing later than we expected. HuC is still loaded when the
bind occurs, but in the meantime i915 has started allowing submission to
the VCS engines even if HuC
On Wed, Oct 12, 2022 at 05:03:32PM -0700, Daniele Ceraolo Spurio wrote:
> The render and media GuCs share the same interrupt enable register, so
> we can no longer disable interrupts when we disable communication for
> one of the GuCs as this would impact the other GuC. Instead, we keep the
> inter
== Series Details ==
Series: drm/i915/pvc: Update forcewake domain for CCS register ranges
URL : https://patchwork.freedesktop.org/series/109734/
State : warning
== Summary ==
Error: dim checkpatch failed
2c301df9c083 drm/i915/pvc: Update forcewake domain for CCS register ranges
-:31: WARNING:
== Series Details ==
Series: Explicit MCR handling and MTL steering (rev4)
URL : https://patchwork.freedesktop.org/series/108755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_108755v4
Summary
---
The bspec was just updated with a correction to the forcewake domain
required when accessing registers in the CCS engine ranges (0x1a000 -
0x1 and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
the RENDER domain, not the GT domain.
Bspec: 67609
Signed-off-by: Matt Roper
---
driver
== Series Details ==
Series: Explicit MCR handling and MTL steering (rev4)
URL : https://patchwork.freedesktop.org/series/108755/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Explicit MCR handling and MTL steering (rev4)
URL : https://patchwork.freedesktop.org/series/108755/
State : warning
== Summary ==
Error: dim checkpatch failed
830513957fa8 drm/i915/gen8: Create separate reg definitions for new MCR
registers
dbdc6927367f drm/i915/
Xe_HP has some MCR registers that need to be polled for completion of
operations like TLB invalidation. Those registers are in the GAM range,
which rolls up the status from each unit into the 'primary' instance's
value. This makes it useful to have a dedicated 'wait for register'
function that ha
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give u
We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond. In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
v2:
- Add TLB invalidation registers
v3:
- Switch more uncore operations in mmio_invalidate_full() to MCR
operations for X
Rather than using the same _MMIO() macro to define MCR registers as
singleton registers, let's use a new MCR_REG() macro to make it clear
that these registers are special and should be handled accordingly. For
now MCR_REG() will still generate an i915_reg_t with the given offset,
but we'll change
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered). There are some registers that transitioned from
singleton behavior to multicast during the gen7 -> gen8 transition;
let's duplicate the reg
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 433 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 263 insertions(+), 174 deletions(-)
di
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
he
On Xe_HP the fault registers are now in a multicast register range.
However as part of the GAM these registers follow special rules and we
need only read from the "primary" GAM's instance to get the information
we need. So a single intel_gt_mcr_read_any() (which will automatically
steer to the pri
Starting in Xe_HP, several registers our driver works with have been
converted from singleton registers into replicated registers with
multicast behavior. Although the registers are still located at the
same MMIO offsets as on previous platforms, let's duplicate the register
definitions in prepara
MTL's graphics IP (Xe_LPG) once again changes the multicast register
types and steering details. Key changes from past platforms:
* The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
according to the MTL subplatform and cannot be read from fuse
registers. However steerin
There are cases where we wish to read from any non-terminated MCR
register instance (or the primary instance in the case of GAM ranges),
clear/set some bits, and then write the value back out to the register
in a multicast manner. Adding a "multicast RMW" will avoid the need to
open-code this.
v2
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
drivers/gpu
MTL's media IP (Xe_LPM+) only has a single type of steering ("OAADDRM")
which selects between media slice 0 and media slice 1. We'll always
steer to media slice 0 unless it is fused off (which is the case when
VD0, VE0, and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by: Matt R
On Fri, Oct 14, 2022 at 09:32:55PM +0530, Balasubramani Vivekanandan wrote:
> On 30.09.2022 17:45, Matt Roper wrote:
> > MTL once again changes the multicast register types and steering
> > details. Key changes from past platforms:
> > * The number of instances of some MCR types (NODE, OAAL2, and
On Tue, Oct 11, 2022 at 08:38:51AM -0700, Radhakrishna Sripada wrote:
Platforms prior to MTL do not have a separate media and graphics version.
On platforms where GMD id is not supported, reuse the graphics ip version,
release info for media.
The rest of the IP graphics, display versions would b
On Thu, Oct 13, 2022 at 06:23:07PM +, Jose Souza wrote:
missed the "drm/" in the subject 😛
with that, Reviewed-by: Lucas De Marchi
Lucas De Marchi
On Thu, 2022-10-13 at 11:14 -0700, José Roberto de Souza wrote:
BSpec: 54369
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/
On 10/13/2022 09:14, Andrzej Hajda wrote:
In case of catastrophic errors GuC is able to initate engine
reset immediately, instead of waiting for timeout.
Signed-off-by: Andrzej Hajda
---
Hi all,
I am new in the subject, so please be polite if this is mistake.
Tests shows that it allows to save
== Series Details ==
Series: drm/i915: Print return value on error (rev2)
URL : https://patchwork.freedesktop.org/series/109722/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109722v2_full
Summary
--
On Thu, Oct 06, 2022 at 06:32:00PM +0200, Andrzej Hajda wrote:
> There is special helper for register read/modify/write.
>
> Signed-off-by: Andrzej Hajda
> Reviewed-by: Andi Shyti
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 9 +-
> drivers/gpu/drm/i915/i915_irq.c | 227 +
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/109723/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109723v1_full
Summary
---
**FAILURE**
On 14/10/2022 17:51, Jordan Justen wrote:
On 2022-10-14 03:58:12, Matthew Auld wrote:
On 14/10/2022 08:20, Jordan Justen wrote:
Acked-by: Jordan Justen
Thanks. Can I take that as ack for merging the series from Mesa POV? I
think Lionel was going to test this, but I think keeps getting swampe
== Series Details ==
Series: drm/i915: Print return value on error (rev2)
URL : https://patchwork.freedesktop.org/series/109722/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109722v2
Summary
---
*
From: Patchwork
Sent: Thursday, October 13, 2022 9:57 PM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display:
Do both crawl and squash when changing cdclk
Patch Details
Series:
series starting with [1/2] drm/i9
On 2022-10-14 03:58:12, Matthew Auld wrote:
> On 14/10/2022 08:20, Jordan Justen wrote:
> > Acked-by: Jordan Justen
>
> Thanks. Can I take that as ack for merging the series from Mesa POV? I
> think Lionel was going to test this, but I think keeps getting swamped
> with other stuff. We kind of
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/109723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109723v1
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/109723/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/109723/
State : warning
== Summary ==
Error: dim checkpatch failed
d1480828fe68 drm/i915/dp: Check if DSC supports the given output_format
f7cf4b8cf10a drm/i915: Adding the new registers for DS
== Series Details ==
Series: drm/i915: Refactor ttm ghost obj detection
URL : https://patchwork.freedesktop.org/series/109715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109715v1_full
Summary
== Series Details ==
Series: drm/i915: Print return value on error
URL : https://patchwork.freedesktop.org/series/109722/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109722v1
Summary
---
**SUCCES
On 30.09.2022 17:45, Matt Roper wrote:
> MTL once again changes the multicast register types and steering
> details. Key changes from past platforms:
> * The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
>according to the MTL subplatform and cannot be read from fuse
>r
== Series Details ==
Series: drm/i915: Fix simulated GPU reset wrt. encoder HW readout
URL : https://patchwork.freedesktop.org/series/109480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12225_full -> Patchwork_109480v1_full
===
Print returned error code for better debuggability.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7211
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i
On 10/14/2022 5:38 PM, Jani Nikula wrote:
On Fri, 14 Oct 2022, Nirmoy Das wrote:
Print returned error code for better debuggability.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7211
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +++---
1 f
On Fri, 14 Oct 2022, Nirmoy Das wrote:
> Print returned error code for better debuggability.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/7211
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 dele
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
From: "Suraj Kandpal"
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vd
From: "Suraj Kandpal"
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
i
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i91
Print returned error code for better debuggability.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7211
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i
On 10/14/2022 4:58 PM, Matthew Auld wrote:
On 14/10/2022 14:14, Nirmoy Das wrote:
Currently i915_ttm_to_gem() returns NULL for ttm ghost
object which makes it unclear when we should add a NULL
check for a caller of i915_ttm_to_gem() as ttm ghost
objects are expected behaviour for certain cases
On 14/10/2022 14:14, Nirmoy Das wrote:
Currently i915_ttm_to_gem() returns NULL for ttm ghost
object which makes it unclear when we should add a NULL
check for a caller of i915_ttm_to_gem() as ttm ghost
objects are expected behaviour for certain cases.
Create a separate function to detect ttm gh
Hi Matt,
On Fri, Oct 14, 2022 at 10:44:11AM +0100, Matthew Auld wrote:
> On 14/10/2022 09:56, Andi Shyti wrote:
> > On Fri, Oct 14, 2022 at 09:39:52AM +0100, Matthew Auld wrote:
> > > On 13/10/2022 18:56, Jonathan Cavitt wrote:
> > > > i915_ttm_to_gem can return a NULL pointer, which is
> > > > de
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109714v1_full
Summary
-
== Series Details ==
Series: drm/i915: Refactor ttm ghost obj detection
URL : https://patchwork.freedesktop.org/series/109715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109715v1
Summary
---
**S
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109714v1
Summary
---
**SU
Currently i915_ttm_to_gem() returns NULL for ttm ghost
object which makes it unclear when we should add a NULL
check for a caller of i915_ttm_to_gem() as ttm ghost
objects are expected behaviour for certain cases.
Create a separate function to detect ttm ghost object and
use that in places where w
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim checkpatch failed
17498f64790a drm/i915/mtl: Initial DDI port setup
c7a2fc56a9d0 drm/i915/mtl: Add DP rates
919c8b25d4b3 drm/i9
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
dr
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 31 -
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 4 +++
.../drm/i915/display/in
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
Signed-off-b
From: Radhakrishna Sripada
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: M
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/int
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
3 files changed, 33 insertions(+), 5 deletions(-)
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions(-)
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 139 insertion
From: Radhakrishna Sripada
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_c
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: J
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to us
Create a separate file to store registers for PICA chips
C10 and C20.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/int
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/int
PHY programming support for C10 and C20 Type-C chips. This series
includes fixes for previously sent C10 series.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Gustavo Sousa (1):
drm/i915/mtl:
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b
> -Original Message-
> From: Jani Nikula
> Sent: Friday, September 30, 2022 12:32 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Add support for C10 phy
> programming
>
> On Thu, 29 Sep 2022, Mika Kahola wrote:
> > From: Radha
== Series Details ==
Series: drm/i915/dgfx: Temporary hammer to keep autosuspend control 'on' (rev2)
URL : https://patchwork.freedesktop.org/series/109612/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109612v2
===
DGFX platforms has lmem and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)
Bot
On 14/10/2022 08:20, Jordan Justen wrote:
Acked-by: Jordan Justen
Thanks. Can I take that as ack for merging the series from Mesa POV? I
think Lionel was going to test this, but I think keeps getting swamped
with other stuff. We kind of urgently need to land this series.
On 2022-10-04 04
On 10/14/2022 12:52 PM, Matthew Auld wrote:
On 14/10/2022 11:38, Das, Nirmoy wrote:
Hi Matt,
On 10/14/2022 12:13 PM, Matthew Auld wrote:
On 14/10/2022 10:27, Das, Nirmoy wrote:
Hi Matt
On 10/14/2022 10:39 AM, Matthew Auld wrote:
On 13/10/2022 18:56, Jonathan Cavitt wrote:
i915_ttm_to_gem
On 14/10/2022 11:38, Das, Nirmoy wrote:
Hi Matt,
On 10/14/2022 12:13 PM, Matthew Auld wrote:
On 14/10/2022 10:27, Das, Nirmoy wrote:
Hi Matt
On 10/14/2022 10:39 AM, Matthew Auld wrote:
On 13/10/2022 18:56, Jonathan Cavitt wrote:
i915_ttm_to_gem can return a NULL pointer, which is
dereferenc
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