Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2022-06-23:
Multiple fixes in sun4i for suspend, DDC, DMA setup; A rework of vc4 to
properly split the driver between hardware capabilities that wasn't done
properly causing multiple crashes; and a panel quirk for Aya Neo
== Series Details ==
Series: drm/i915/guc: Don't update engine busyness stats too frequently
URL : https://patchwork.freedesktop.org/series/105525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11795 -> Patchwork_105525v1
S
== Series Details ==
Series: drm/i915/guc: Don't update engine busyness stats too frequently
URL : https://patchwork.freedesktop.org/series/105525/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc/slpc: Use non-blocking H2G for waitboost (rev3)
URL : https://patchwork.freedesktop.org/series/103598/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11795 -> Patchwork_103598v3
Summ
Using two different types of workoads, it was observed that
guc_update_engine_gt_clks was being called too frequently and/or
causing a CPU-to-lmem bandwidth hit over PCIE. Details on
the workloads and numbers are in the notes below.
Background: At the moment, guc_update_engine_gt_clks can be invok
This change ensures we don't resample GuC busyness stat
counters too soon after the last sample.
Prior receipts of rvb's:
Umesh Nerlige Ramappa
Changes from prior revs:
v3: - Added Umesh's Rvb into patch
v2: - Align the name of last_stat_jiffies (Tvrtko)
- Use 32-bit jiffes (Tvrtk
== Series Details ==
Series: drm/doc/rfc: i915 VM_BIND feature design + uapi
URL : https://patchwork.freedesktop.org/series/105513/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/
This change ensures we don't resample GuC busyness stat
counters too soon after the last sample.
Changes from prior revs:
v2: - Align the name of last_stat_jiffies (Tvrtko)
- Use 32-bit jiffes (Tvrtko)
- use time_after() macro (Tvrtko)
- change from ">> 1" to "/ 2" for ping
Using two different types of workoads, it was observed that
guc_update_engine_gt_clks was being called too frequently and/or
causing a CPU-to-lmem bandwidth hit over PCIE. Details on
the workloads and numbers are in the notes below.
Background: At the moment, guc_update_engine_gt_clks can be invok
== Series Details ==
Series: drm/i915/dg2: Add performance workaround 18019455067
URL : https://patchwork.freedesktop.org/series/105512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11795 -> Patchwork_105512v1
Summary
== Series Details ==
Series: drm/i915/dg2: Add performance workaround 18019455067
URL : https://patchwork.freedesktop.org/series/105512/
State : warning
== Summary ==
Error: dim checkpatch failed
aaa694cf2d6b drm/i915/dg2: Add performance workaround 18019455067
-:33: ERROR:CODE_INDENT: code in
On Wed, 22 Jun 2022 17:32:25 -0700, Vinay Belgaumkar wrote:
>
> @@ -208,12 +232,14 @@ static int slpc_force_min_freq(struct intel_guc_slpc
> *slpc, u32 freq)
>*/
>
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> - ret = slpc_set_param(slpc,
> -
== Series Details ==
Series: drm/i915: tweak the ordering in cpu_write_needs_clflush
URL : https://patchwork.freedesktop.org/series/105503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11795 -> Patchwork_105503v1
Summary
-
SLPC min/max frequency updates require H2G calls. We are seeing
timeouts when GuC channel is backed up and it is unable to respond
in a timely fashion causing warnings and affecting CI.
This is seen when waitboosting happens during a stress test.
this patch updates the waitboost path to use a non-
> > + /**
> > +* @last_jiffies: jiffies at last actual stats collection time
> > +* We use this timestamp to ensure we don't oversample the
> > +* stats because runtime power management events can trigger
> > +* stats collection at much hi
Thanks Umesh. As per offline - i will address Tvrtko's comments too.
...alan
On Wed, 2022-06-22 at 16:00 -0700, Nerlige Ramappa, Umesh wrote:
> On Fri, Jun 17, 2022 at 10:43:45PM -0700, Alan Previn wrote:
> > Using igt's gem-create and with additional patches to track object
> > creation time, it
== Series Details ==
Series: drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/90164/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_90164v3
Summary
---
On Fri, Jun 17, 2022 at 10:43:45PM -0700, Alan Previn wrote:
Using igt's gem-create and with additional patches to track object
creation time, it was measured that guc_update_engine_gt_clks was
getting called over 188 thousand times in the span of 15 seconds
(running the test three times).
Get a
On Fri, Jun 17, 2022 at 04:05:58PM -0700, Lucas De Marchi wrote:
Exporting the symbols like intel_gtt_* creates some confusion inside
i915 that has symbols named similarly. In an attempt to isolate
platforms needing intel-gtt.ko, commit 7a5c922377b4 ("drm/i915/gt: Split
intel-gtt functions by arc
On Mon, Jun 20, 2022 at 09:46:30AM +0100, Tvrtko Ursulin wrote:
On 18/06/2022 06:43, Alan Previn wrote:
Using igt's gem-create and with additional patches to track object
creation time, it was measured that guc_update_engine_gt_clks was
getting called over 188 thousand times in the span of 15 s
== Series Details ==
Series: drm/i915/selftests: Increase timeout for live_parallel_switch
URL : https://patchwork.freedesktop.org/series/105490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_105490v1
Sum
On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> > > Gem buffers could still be in use by display after i915_gem_suspend()
> > > is executed so there is ch
== Series Details ==
Series: drm/edid: expand on struct drm_edid usage (rev4)
URL : https://patchwork.freedesktop.org/series/104309/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_104309v4
Summary
---
== Series Details ==
Series: drm/i915/dsi: add payload receiving code (rev6)
URL : https://patchwork.freedesktop.org/series/105096/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_105096v6
Summary
---
On Wed, 22 Jun 2022 13:30:23 -0700, Belgaumkar, Vinay wrote:
> On 6/21/2022 5:26 PM, Dixit, Ashutosh wrote:
> > On Sat, 14 May 2022 23:05:06 -0700, Vinay Belgaumkar wrote:
> > The issue I have is what happens when we de-boost (restore min freq to its
> > previous value in intel_guc_slpc_dec_waiters
== Series Details ==
Series: drm/edid: expand on struct drm_edid usage (rev4)
URL : https://patchwork.freedesktop.org/series/104309/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/edid: expand on struct drm_edid usage (rev4)
URL : https://patchwork.freedesktop.org/series/104309/
State : warning
== Summary ==
Error: dim checkpatch failed
7563c369133d drm/edid: move drm_connector_update_edid_property() to drm_edid.c
2f2c0140ebb5 drm/edid:
On Wed, Jun 22, 2022 at 09:38:36PM +0300, Lionel Landwerlin wrote:
This is the recommended value for optimal performance.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
On Wed, Jun 22, 2022 at 09:38:36PM +0300, Lionel Landwerlin wrote:
> This is the recommended value for optimal performance.
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 2 files changed,
== Series Details ==
Series: drm/i915/dsi: add payload receiving code (rev6)
URL : https://patchwork.freedesktop.org/series/105096/
State : warning
== Summary ==
Error: dim checkpatch failed
b22f538d9671 drm/i915/dsi: add payload receiving code
-:111: CHECK:BRACES: Blank lines aren't necessary
== Series Details ==
Series: drm/i915: i915_irq - drop unexpected word "the" in the comments
URL : https://patchwork.freedesktop.org/series/105477/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_105477v1
S
Hi Zdenek,
On Wed, Jun 22, 2022 at 01:18:42PM +0200, Zdenek Kabelac wrote:
> Hello
>
> While somewhat oldish hw (T61, 4G, C2D) - I've now witnessed new crash with
> Xorg:
>
> (happened while reopening iconified Firefox window - running 'standard'
> rawhide -nodebug kernel 5.19.0-0.rc2.21.fc3
On Wed, Jun 22, 2022 at 03:55:03PM +0300, Jani Nikula wrote:
> On Tue, 21 Jun 2022, "Tangudu, Tilak" wrote:
> >> -Original Message-
> >> From: Gupta, Anshuman
> >> Sent: Tuesday, June 21, 2022 7:47 PM
> >> To: Tangudu, Tilak ;
> >> intel-gfx@lists.freedesktop.org;
> >> Ewins, Jon ; Vivi,
== Series Details ==
Series: drm/i915: i915_irq - drop unexpected word "the" in the comments
URL : https://patchwork.freedesktop.org/series/105477/
State : warning
== Summary ==
Error: dim checkpatch failed
d92af542e2e9 drm/i915: i915_irq - drop unexpected word "the" in the comments
-:11: WARN
On Fri, 10 Jun 2022 16:47:12 -0700, Vinay Belgaumkar wrote:
>
> This test will validate we can achieve actual frequency of RP0. Pcode
> grants frequencies based on what GuC is requesting. However, thermal
> throttling can limit what is being granted. Add a test to request for
> max, but don't fail
On 6/21/2022 5:26 PM, Dixit, Ashutosh wrote:
On Sat, 14 May 2022 23:05:06 -0700, Vinay Belgaumkar wrote:
SLPC min/max frequency updates require H2G calls. We are seeing
timeouts when GuC channel is backed up and it is unable to respond
in a timely fashion causing warnings and affecting CI.
Th
== Series Details ==
Series: small BAR uapi bits (rev3)
URL : https://patchwork.freedesktop.org/series/104369/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_104369v3
Summary
---
**FAILURE**
Seri
== Series Details ==
Series: small BAR uapi bits (rev3)
URL : https://patchwork.freedesktop.org/series/104369/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: small BAR uapi bits (rev3)
URL : https://patchwork.freedesktop.org/series/104369/
State : warning
== Summary ==
Error: dim checkpatch failed
1f41c0228c1d drm/doc: add rfc section for small BAR uapi
-:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), d
== Series Details ==
Series: drm/i915/guc: ADL-N should use the same GuC FW as ADL-S
URL : https://patchwork.freedesktop.org/series/105444/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11794 -> Patchwork_105444v1
Summary
-
Hi Dave and Daniel,
Here goes the first pull request targeting 5.20.
Kudos to Jani and Ville for a good driver clean-up.
And many other fixes and improvements from the team.
drm-intel-next-2022-06-22:
- General driver clean-up (Jani, Ville, Julia)
- DG2 enabling (Anusha, Vandita)
- Fix sparse wa
== Series Details ==
Series: drm/doc/rfc: i915 VM_BIND feature design + uapi
URL : https://patchwork.freedesktop.org/series/105452/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Thursday, April 14, 2022 12:56 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915: Eliminate PIPECONF RMWs from
> .color_commit()
>
> From: Ville Syrjälä
>
> Eliminate the PIPECO
On Wed, Jun 22, 2022 at 09:44:47AM -0700, Niranjana Vishwanathapura wrote:
On Wed, Jun 22, 2022 at 04:57:17PM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 16:12, Niranjana Vishwanathapura wrote:
On Wed, Jun 22, 2022 at 09:10:07AM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 04:56, Niranjana Vish
VM_BIND and related uapi definitions
v2: Reduce the scope to simple Mesa use case.
v3: Expand VM_UNBIND documentation and add
I915_GEM_VM_BIND/UNBIND_FENCE_VALID
and I915_GEM_VM_BIND_TLB_FLUSH flags.
v4: Remove I915_GEM_VM_BIND_TLB_FLUSH flag and add additional
documentation for vm_bin
Add some missing i915 upai documentation which the new
i915 VM_BIND feature documentation will be refer to.
Signed-off-by: Niranjana Vishwanathapura
Reviewed-by: Matthew Auld
---
include/uapi/drm/i915_drm.h | 205
1 file changed, 160 insertions(+), 45 deleti
VM_BIND design document with description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
v3: Expand documentation on dma-resv usage, TLB flushing and
execbuf3.
v4: Remove vm_bind tlb flush request support.
Signed-off-by: Niranjana Vishwanathapura
---
Documentation/gpu/r
This is the i915 driver VM_BIND feature design RFC patch series along
with the required uapi definition and description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
Remove all compute related uapi, vm_bind/unbind queue support and
only support a timeline out fence i
This is the recommended value for optimal performance.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/
Reviewed-by: Alan Previn
On Thu, 2022-06-09 at 16:19 -0700, Ceraolo Spurio, Daniele wrote:
> The fw name is different and we need to record the fact that the blob is
> gsc-loaded, so add a new macro to help.
>
> Note: A-step DG2 G10 does not support HuC loading via GSC and would
> require a sepa
Reviewed-by: Alan Previn
On Thu, 2022-06-09 at 16:19 -0700, Ceraolo Spurio, Daniele wrote:
> The fw name is different and we need to record the fact that the blob is
> gsc-loaded, so add a new macro to help.
>
> Note: A-step DG2 G10 does not support HuC loading via GSC and would
> require a sepa
On Wed, Jun 22, 2022 at 04:57:17PM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 16:12, Niranjana Vishwanathapura wrote:
On Wed, Jun 22, 2022 at 09:10:07AM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 04:56, Niranjana Vishwanathapura wrote:
VM_BIND and related uapi definitions
v2: Reduce the sco
For imported dma-buf objects we leave the object as cache_coherent = 0
across all platforms, which is reasonable given that have no clue what
the memory underneath is, and its not like the driver can ever manually
clflush the pages anyway (like with i915_gem_clflush_object) for such
objects. Howeve
On 22/06/2022 16:12, Niranjana Vishwanathapura wrote:
On Wed, Jun 22, 2022 at 09:10:07AM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 04:56, Niranjana Vishwanathapura wrote:
VM_BIND and related uapi definitions
v2: Reduce the scope to simple Mesa use case.
v3: Expand VM_UNBIND documentation a
From: Ville Syrjälä
The watermark code for ctg/elk has been atomic ready for a long time
so let's just flip the switch now that some of the last CxSR issues
have been sorted out (which granted was a problem for vlv/chv as well
despite them already having atomic enabled by default).
Signed-off-by
From: Ville Syrjälä
We've excluded gmch platforms from writing the final watermarks
for any disabled pipe. IIRC the reason was perhaps some lingering
issue with the watermark merging across the pipes. But I can't
really see any reason for this anymore, so let's unify this behaviour.
The main bene
From: Ville Syrjälä
Like most other plane control register bits, the pipe gamma
enable bit is also blocked by CxSR. So make sure we kick the
machine out of CxSR before trying to change that bit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 4
1 file change
From: Ville Syrjälä
On g4x/vlv/chv the hardware seems incapable of changing the pixel
format, rotation, or YUV->RGB CSC matrix while in CxSR.
Additionally on VLV/CHV the sprites seem incapable of tiling
changes while in CxSR. On g4x CxSR is not even possible with
the sprite enabled. Curiously th
From: Ville Syrjälä
Let's not forget to mark the unused watermark levels as invalid
after the readout. The vlv/chv codepath has this but the g4x
didn't for some reason.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/driver
From: Ville Syrjälä
Split vlv_compute_pipe_wm() into two halves. The first half computes
the new raw watermarks, and the second half munges those up into real
watermarks for the particular pipe.
We can reuse the second half for watermark sanitation as well.
Signed-off-by: Ville Syrjälä
---
dr
From: Ville Syrjälä
We can simplify the vlv watermark sanitation by reusing the
second half of vlv_compute_pipe_wm() to convert the sanitized
raw watermarks into the proper form to be used as the
optimal/intermediate watermarks.
Also to be consistent with normal watermark computation the sanitiz
From: Ville Syrjälä
We can simplify the g4x watermark sanitation by reusing the
second half of g4x_compute_pipe_wm() to convert the sanitized
raw watermarks into the proper form to be used as the
optimal/intermediate watermarks.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
Split g4x_compute_pipe_wm() into two halves. The first half computes
the new raw watermarks, and the second half munges those up into real
watermarks for the particular pipe.
We can reuse the second half for watermark sanitation as well.
Reviewed-by: Stanislav Lisovskiy
Sig
From: Ville Syrjälä
Fix some remaining issues around plane updates vs. CxSR on
gmch platforms. Also throw in a few watermark fixes/cleanups,
and finally flip on atomic for g4x since everything is ready.
v2: Just rebase from a year ago
Ville Syrjälä (9):
drm/i915: Split g4x_compute_pipe_wm() i
On Wed, Jun 22, 2022 at 01:59:19PM +0300, Jani Nikula wrote:
> Add a new function drm_edid_connector_update() to replace the
> combination of calls drm_connector_update_edid_property() and
> drm_add_edid_modes(). Usually they are called in the drivers in this
> order, however the former needs infor
On Wed, Jun 22, 2022 at 09:10:07AM +0100, Tvrtko Ursulin wrote:
On 22/06/2022 04:56, Niranjana Vishwanathapura wrote:
VM_BIND and related uapi definitions
v2: Reduce the scope to simple Mesa use case.
v3: Expand VM_UNBIND documentation and add
I915_GEM_VM_BIND/UNBIND_FENCE_VALID
and I9
On Wed, Jun 22, 2022 at 01:59:22PM +0300, Jani Nikula wrote:
> @@ -948,27 +948,30 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
>* preferred mode is the right one.
>*/
> mutex_lock(&dev->mode_config.mutex);
> - if (vga_switcheroo_handler_flags() & VGA_SWITCHER
On Wed, Jun 22, 2022 at 01:59:18PM +0300, Jani Nikula wrote:
> Add functions drm_edid_override_set() and drm_edid_override_reset() to
> support "edid_override" connector debugfs, and to hide the details about
> it in drm_edid.c. No functional changes at this time.
>
> Also note in the connector.ov
On Wed, Jun 22, 2022 at 01:59:17PM +0300, Jani Nikula wrote:
> Bail out on all errors, debug log all errors, and convert to drm device
> based debug logging.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_edid.c | 41 ++
> 1 file changed, 28 insert
On Wed, Jun 22, 2022 at 01:59:16PM +0300, Jani Nikula wrote:
> Make drm_connector_update_edid_property() a thin wrapper around a struct
> drm_edid based version of the same.
>
> This lets us remove the legacy drm_update_tile_info() and
> drm_add_display_info() functions altogether.
>
> Signed-off
On Wed, Jun 22, 2022 at 01:59:15PM +0300, Jani Nikula wrote:
> The function needs access to drm_edid.c internals more than
> drm_connector.c. We can make drm_reset_display_info(),
> drm_add_display_info() and drm_update_tile_info() static. There will be
> more benefits with follow-up struct drm_edi
On Tue, 2022-06-21 at 11:44 +0100, Matthew Auld wrote:
> We should always be explicit and allocate a fence slot before adding
> a
> new fence.
>
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Lionel Landwerlin
> Cc: Tvrtko Ursulin
> Cc: Jon Bloomfield
> Cc: Daniel Vetter
> Cc: Jo
On Tue, 2022-06-21 at 11:44 +0100, Matthew Auld wrote:
> Vulkan would like to have a rough measure of how much device memory
> can
> in theory be allocated. Also add unallocated_cpu_visible_size to
> track
> the visible portion, in case the device is using small BAR. Also
> tweak
> the locking so w
On Wed, 22 Jun 2022 at 15:11, Matthew Auld wrote:
>
> From: Akeem G Abodunrin
>
> With GuC submission, it takes a little bit longer switching contexts
> among all available engines simultaneously, when running
> live_parallel_switch subtest. Increase the timeout.
>
> Closes: https://gitlab.freede
From: Akeem G Abodunrin
With GuC submission, it takes a little bit longer switching contexts
among all available engines simultaneously, when running
live_parallel_switch subtest. Increase the timeout.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5885
Signed-off-by: Akeem G Abodunri
On Wed, Jun 22, 2022 at 11:04:51AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> On Tue, 21 Jun 2022 10:48:17 +0300 Ville Syrjälä
> wrote:
> >
> > On Tue, Jun 21, 2022 at 12:36:56PM +1000, Stephen Rothwell wrote:
> > >
> > > After merging the drm-misc tree, today's linux-next build (x86_64
> > >
On Tue, 21 Jun 2022, "Tangudu, Tilak" wrote:
>> -Original Message-
>> From: Gupta, Anshuman
>> Sent: Tuesday, June 21, 2022 7:47 PM
>> To: Tangudu, Tilak ;
>> intel-gfx@lists.freedesktop.org;
>> Ewins, Jon ; Vivi, Rodrigo ;
>> Belgaumkar, Vinay ; Wilson, Chris P
>> ; Dixit, Ashutosh ;
>>
On Tue, 21 Jun 2022, Tilak Tangudu wrote:
> Guard rpm helpers in gt_sanitize and intel_gt_set_wedged
> with is_intel_rpm_allowed
>
> Acquire rpm wakeref for higherlevel function i915_gem_resume
>
> Signed-off-by: Tilak Tangudu
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 12 ++--
> dr
Hi, Bob,
On Tue, 2022-06-21 at 20:00 +, Robert Beckett wrote:
> add callbacks for alloc and free.
> this allows region creators to allocate any extra storage they may
> require.
>
> Signed-off-by: Robert Beckett
I think the correct solution here would be to, similar to ttm, export
an alloc_
Hi Dave & Daniel -
drm-intel-fixes-2022-06-22:
drm/i915 fixes for v5.19-rc4:
- Revert low voltage SKU check removal to fix display issues
- Apply PLL DCO fraction workaround for ADL-S
- Don't show engine classes not present in client fdinfo
BR,
Jani.
The following changes since commit a111daf0
On Tue, 2022-06-21 at 20:00 +, Robert Beckett wrote:
> During testing make can_mmap consider whether the region is private.
>
> Signed-off-by: Robert Beckett
LGTM.
Reviewed-by: Thomas Hellström
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
> 1 file changed, 3 insert
Hello
While somewhat oldish hw (T61, 4G, C2D) - I've now witnessed new crash with
Xorg:
(happened while reopening iconified Firefox window - running 'standard'
rawhide -nodebug kernel 5.19.0-0.rc2.21.fc37.x86_64)
page:577758b3 refcount:0 mapcount:0 mapping:
index:0
We need to stop duplicating EDID validation and parsing all over the
subsystem in various broken ways.
v2: Update to reflect drm_connector_helper_get_modes()
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
Documentation/gpu/todo.rst | 25 +
1 file cha
Take the HF-EEODB extension count override into account.
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fa3a3e294560..bbc25e3b72
HDMI 2.1 section 10.3.6 defines an HDMI Forum EDID Extension Override
Data Block, which may contain a different extension count than the base
block claims. Add support for reading more EDID data if available. The
extra blocks aren't parsed yet, though.
Hard-coding the EEODB parsing instead of usin
Rewrite edid_filter_invalid_blocks() to filter invalid blocks
in-place. The main motivation is to not rely on passed in information on
invalid block count or the allocation size, which will be helpful in
follow-up work on HF-EEODB.
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drive
Try to use struct drm_edid where possible, even if having to fall back
to looking into struct edid down low via drm_edid_raw().
v2: Rebase
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 ++-
drivers/gpu/drm/i915/display/
Convert all the connectors that use cached connector edid and
detect_edid to drm_edid.
v2: Don't leak opregion fallback EDID (Ville)
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_connector.c| 4 +-
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/
Unfortunately, there are still plenty of interfaces around that require
a struct edid pointer, and it's impossible to change them all at
once. Add an accessor to the raw EDID data to help the transition.
While there are no such cases now, be defensive against raw EDID
extension count indicating bi
Add a helper function to be used as the "default" .get_modes()
hook. This also works as an example of what the driver .get_modes()
hooks are supposed to do regarding the new drm_edid_read*() and
drm_edid_connector_update() calls.
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers
Add a new function drm_edid_connector_update() to replace the
combination of calls drm_connector_update_edid_property() and
drm_add_edid_modes(). Usually they are called in the drivers in this
order, however the former needs information from the latter.
Since the new drm_edid_read*() functions no
Add functions drm_edid_override_set() and drm_edid_override_reset() to
support "edid_override" connector debugfs, and to hide the details about
it in drm_edid.c. No functional changes at this time.
Also note in the connector.override_edid flag kernel-doc that this is
only supposed to be modified b
Bail out on all errors, debug log all errors, and convert to drm device
based debug logging.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 41 ++
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers
Make drm_connector_update_edid_property() a thin wrapper around a struct
drm_edid based version of the same.
This lets us remove the legacy drm_update_tile_info() and
drm_add_display_info() functions altogether.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 81
The function needs access to drm_edid.c internals more than
drm_connector.c. We can make drm_reset_display_info(),
drm_add_display_info() and drm_update_tile_info() static. There will be
more benefits with follow-up struct drm_edid refactoring.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_
v3 of [1], addressing review comments. I'm adding some code movement and
refactoring in the beginning to reuse code between
drm_connector_update_edid_property() and drm_edid_connector_update()
which was a concern Ville raised [2].
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/104309/
[2
On 6/21/22 22:00, Robert Beckett wrote:
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now
On 6/21/22 22:00, Robert Beckett wrote:
i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.
Signed-off-by: Robert Beckett
LGTM.
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
1 file changed, 6 insertions(+), 1
On 6/21/22 22:00, Robert Beckett wrote:
Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.
TTM movement code came along and decided that it could make that
decisi
On Tue, 21 Jun 2022 at 19:38, Juha-Pekka Heikkila
wrote:
>
> On 21.6.2022 13.53, Matthew Auld wrote:
> > On Mon, 20 Jun 2022 at 10:38, Juha-Pekka Heikkila
> > wrote:
> >>
> >> On 10.6.2022 20.43, Matthew Auld wrote:
> >>> On Fri, 10 Jun 2022 at 15:53, Matthew Auld
> >>> wrote:
>
> On F
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