Issue is part of https://gitlab.freedesktop.org/drm/intel/-/issues/4890.
Filter is updated to include all tests.
Lakshmi.
-Original Message-
From: Roper, Matthew D
Sent: Friday, May 20, 2022 4:11 PM
To: intel-gfx@lists.freedesktop.org
Cc: Srivatsa, Anusha ; Vudum, Lakshminarayana
Subj
== Series Details ==
Series: drm/i915/dg2: Enable DC5
URL : https://patchwork.freedesktop.org/series/104233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11681 -> Patchwork_104233v1
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11682 -> Patchwork_104244v1
Summary
---
**FAILURE**
Ser
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim checkpatch failed
715c882f826e drm/i915/xehp: Use separate sseu init function
194ba3678abd drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM
On Fri, May 20, 2022 at 05:11:22PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Enable DC5
> URL : https://patchwork.freedesktop.org/series/104233/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11681 -> Patchwork_104233v1
> ===
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
prepare for future platforms where the masks will need to grow in size.
One key idea of this series is that although we have a fixed ABI to
convey SSEU dat
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will be
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose be
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add has_xeh
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditio
On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote:
>
> On 17/05/2022 04:20, Matt Roper wrote:
> > Slice/subslice/EU information should be obtained via the topology
> > queries provided by the I915_QUERY interface; let's turn off support for
> > the old GETPARAM lookups on Xe_HP and be
On Wed, May 11, 2022 at 02:01:21PM +0530, Ankit Nautiyal wrote:
> From: Vandita Kulkarni
>
> This patch adds a fix to support 297MHz of dot clock by calculating
> the pll values using synopsis algorithm.
> This will help to support 4k@30 mode for HDMI monitors on DG2.
>
> Signed-off-by: Vandita
== Series Details ==
Series: drm/i915/dg2: Enable DC5
URL : https://patchwork.freedesktop.org/series/104233/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11681 -> Patchwork_104233v1
Summary
---
**FAILURE**
Seriou
On Fri, May 20, 2022 at 12:46:00PM +0300, Jani Nikula wrote:
> The VBT send packet port selection was never updated for ICL+ where the
> 2nd link is on port B instead of port C as in VLV+ DSI.
>
> First, single link DSI needs to use the configured port instead of
> relying on the VBT sequence bloc
Enable DC5 on dg2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
ind
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for ICL+
URL : https://patchwork.freedesktop.org/series/104220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11681_full -> Patchwork_104220v1_full
===
Hello Jose,
Thank you for your comments, see my response below.
On Thu, 2022-05-19 at 13:47 +, Souza, Jose wrote:
> On Thu, 2022-05-19 at 12:17 +, Hogander, Jouni wrote:
> > On Wed, 2022-05-18 at 20:00 +, Souza, Jose wrote:
> > > On Wed, 2022-05-18 at 10:45 +0300, Jouni Högander wrot
== Series Details ==
Series: drm/i915/dsi: fix VBT send packet port selection for ICL+
URL : https://patchwork.freedesktop.org/series/104220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11681 -> Patchwork_104220v1
Summary
On Fri, 20 May 2022 at 12:23, Juha-Pekka Heikkilä
wrote:
>
>
>
> Matthew Auld kirjoitti 11.5.2022 klo 13.41:
> > On Fri, 6 May 2022 at 14:11, Juha-Pekka Heikkila
> > wrote:
> >>
> >> Add fallback smem allocation for dpt if stolen memory allocation failed.
> >>
> >> Signed-off-by: Juha-Pekka Heikk
Matthew Auld kirjoitti 11.5.2022 klo 13.41:
On Fri, 6 May 2022 at 14:11, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 16
1 file cha
Hi all,
This is for Tvrtko to pull to cross-merge sync drm-intel-next to
drm-intel-gt-next.
Dave, Daniel, IIUC this is what you prefer over having topic branches
for all the small things that are needed between drm-intel branches. I
don't think we've done this direct cross-merge before, so deci
On 17/05/2022 16:15, Matt Roper wrote:
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly
The VBT send packet port selection was never updated for ICL+ where the
2nd link is on port B instead of port C as in VLV+ DSI.
First, single link DSI needs to use the configured port instead of
relying on the VBT sequence block port. Remove the hard-coded port C
check here and make it generic. Fo
On 17/05/2022 04:20, Matt Roper wrote:
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation t
On 17/05/2022 04:20, Matt Roper wrote:
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can
On 17/05/2022 04:20, Matt Roper wrote:
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meani
This is early warning about GFX-CI going down for maintenance
on next week weekend Fri 27.5. to Sun 29.5.
GFX-CI will be migrating to new hardware starting Friday 27.5. and
estimated downtime is at least 48h (CIBuglog database dump/import).
During downtime, no new builds are done and no testing is
Jani Nikula wrote on pią [2022-maj-20 10:40:01
+0300]:
> On Thu, 20 Jan 2022, "Piorkowski, Piotr" wrote:
> > From: Piotr Piórkowski
> >
> > For proper operation of i915 we need usable PCI BARs:
> > - GTTMMADDR BAR 0 (1 for GEN2)
> > - GFXMEM BAR 2.
> > Lets check before we start the i915 prob
On Thu, 20 Jan 2022, "Piorkowski, Piotr" wrote:
> From: Piotr Piórkowski
>
> For proper operation of i915 we need usable PCI BARs:
> - GTTMMADDR BAR 0 (1 for GEN2)
> - GFXMEM BAR 2.
> Lets check before we start the i915 probe that these BARs are set,
> and that they have a size greater than 0.
Hi Imre,
> On Wed, May 18, 2022 at 10:04:14AM +0300, Kasireddy, Vivek wrote:
> > Hi Imre,
> >
> > > On Mon, May 16, 2022 at 01:54:02AM -0700, Vivek Kasireddy wrote:
> > > > Although, doing a modeset on any disconnected connector might be futile,
> > > > it can be particularly problematic if the co
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2022-05-20:
Fix for a memory leak in dp_mst, a (userspace) build fix for
DMA_BUF_SET_NAME defines and a directory name generation fix for dmabuf
stats
The following changes since commit 6fed53de560768bde6d701a7c79c253b45b2
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