Re-reported and few comments below.
-Original Message-
From: Dixit, Ashutosh
Sent: Friday, April 29, 2022 5:45 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Media freq factor and per-gt
enhancements/fixes (rev4)
On Fri,
On Fri, 29 Apr 2022 16:38:35 -0700, Patchwork wrote:
>
> Possible regressions
>
> * igt@gem_eio@in-flight-suspend:
>
> * shard-skl: PASS -> INCOMPLETE
This failure in unrelated.
>
> * {igt@i915_pm_disag_freq@media-freq@gt0} (NEW):
>
> * shard-iclb: NOTRUN -> SKIP
>
> * shard-tglb: NOTRUN -> SK
> -Original Message-
> From: De Marchi, Lucas
> Sent: Friday, April 29, 2022 1:50 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Fri, Apr 29, 2022 at 01:39:03PM -0700, Anus
On Fri, 29 Apr 2022 14:31:49 -0300
Jason Gunthorpe wrote:
> On Thu, Apr 21, 2022 at 01:28:31PM -0300, Jason Gunthorpe wrote:
> > Prior series have transformed other parts of VFIO from working on struct
> > device or struct vfio_group into working directly on struct
> > vfio_device. Based on that
On Thu, Apr 28, 2022 at 06:18:41AM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Turn on compute engine support (rev4)
> URL : https://patchwork.freedesktop.org/series/103011/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11550_full -> Patchwork_10
I did some light testing with our anvil (Vulkan) and iris (OpenGL)
Mesa drivers after applying these patches on top of drm-tip tagged
intel/CI_DRM_11574. All the unit tests that I tried passed. I also ran
the gl_manhattan31 benchmark which used the compute engine for iris
compute shader ops.
Serie
On Fri, 2022-04-29 at 19:00 +0300, Ville Syrjälä wrote:
> On Thu, Apr 28, 2022 at 02:10:56PM -0700, José Roberto de Souza wrote:
> > Frontbuffer updates were scheduling the execution of DRRS work thread
> > even if DRRS is not active.
> > There was no issues with it because intel_drrs_downclock_wor
== Series Details ==
Series: drm/i915: Media freq factor and per-gt enhancements/fixes (rev4)
URL : https://patchwork.freedesktop.org/series/102665/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11583 -> Patchwork_102665v4
On Fri, Apr 29, 2022 at 01:39:03PM -0700, Anusha Srivatsa wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Tuesday, April 26, 2022 10:42 PM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restric
> -Original Message-
> From: De Marchi, Lucas
> Sent: Tuesday, April 26, 2022 10:42 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Tue, Apr 26, 2022 at 05:35:09PM -0700, An
== Series Details ==
Series: drm/i915: Media freq factor and per-gt enhancements/fixes (rev4)
URL : https://patchwork.freedesktop.org/series/102665/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Media freq factor and per-gt enhancements/fixes (rev4)
URL : https://patchwork.freedesktop.org/series/102665/
State : warning
== Summary ==
Error: dim checkpatch failed
720f593ecbb4 drm/i915: Introduce has_media_ratio_mode
3c55d72952c7 drm/i915/gt: Add me
On Thu, 21 Apr 2022 13:28:38 -0300
Jason Gunthorpe wrote:
> When the open_device() op is called the container_users is incremented and
> held incremented until close_device(). Thus, so long as drivers call
> functions within their open_device()/close_device() region they do not
> need to worry ab
Each gt contains an independent instance of pcode. Extend pcode functions
to interface with pcode on different gt's. To avoid creating dependency of
display functionality on intel_gt, pcode function interfaces are exposed in
terms of uncore rather than intel_gt. Callers have been converted to pass
All kmalloc'd kobjects need a kobject_put() to free memory. For example in
previous code, kobj_gt_release() never gets called. The requirement of
kobject_put() now results in a slightly different code organization.
v2: s/gtn/gt/ (Andi)
Cc: Andi Shyti
Cc: Andrzej Hajda
Fixes: b770bcfae9ad ("drm/
Add the following sysfs file to gt/gtN/.defaults:
* media_freq_factor
Cc: Joonas Lahtinen
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 18 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h| 1 +
drivers/gpu/drm/i915/gt
Expose new sysfs to program and retrieve media freq factor. Factor values
of 0 (dynamic), 0.5 and 1.0 are supported via a u8.8 fixed point
representation (corresponding to integer values of 0, 128 and 256
respectively).
Media freq factor is converted to media_ratio_mode for GuC. It is
programmed i
From: Dale B Stimson
Some dGfx pcode commands take additional sub-commands and parameters. Add a
couple of helpers to help formatting these commands to improve code
readability.
v2: Fixed commit author (Rodrigo)
v3: Function rename and convert to new uncore interface for pcode functions
Remo
From: Dale B Stimson
Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt
sysfs. This patch adds the following files to gt/gtN sysfs:
* media_RP0_freq_mhz
* media_RPn_freq_mhz
v2: Fixed commit author (Rodrigo)
v3: Convert to new uncore interface for pcode functions
v4: Adapt t
Media ratio mode (the ability for media IP to work at a different frequency
from the GT) is available for a subset of dGfx platforms supporting
GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to
identify these platforms and set it for XEHPSDV and DG2/ATS-M.
Signed-off-by: Ashu
Create a gt/gtN/.defaults directory (similar to
engine//.defaults) to expose default parameter values for each
gt in sysfs. Populate the .defaults directory with RPS parameter default
values in order to allow userspace to revert to default values when needed.
This patch adds the following sysfs fi
Some recent Intel dGfx platforms allow media IP to work at a different
frequency from the base GT. This patch series exposes sysfs controls for
this functionality in the new per-gt sysfs. Some enhancements and fixes to
previous per-gt functionality are also included to complete the new
functionalit
== Series Details ==
Series: drm/i915: ttm for stolen region (rev6)
URL : https://patchwork.freedesktop.org/series/102540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_102540v6
Summary
---
**FAILU
== Series Details ==
Series: Handle predicate programming
URL : https://patchwork.freedesktop.org/series/103084/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11550_full -> Patchwork_103084v1_full
Summary
---
**FAILU
== Series Details ==
Series: drm/i915: ttm for stolen region (rev6)
URL : https://patchwork.freedesktop.org/series/102540/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Reviewed-by: Alan Previn
On Tue, 2022-04-26 at 17:26 -0700, Daniele Ceraolo Spurio wrote:
> HuC loading via GSC is performed via a PXP command sent through the mei
> modules, so we need both MEI_GSC and MEI_PXP to be available. Given that
> the GSC will do both the transfer and the authenticatio
== Series Details ==
Series: lrc selftest fixes (rev5)
URL : https://patchwork.freedesktop.org/series/101353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_101353v5
Summary
---
**FAILURE**
Serio
minor nit: not sure if its worth mentioning in commit msg that "loaded_via_gsc"
is zero-init-ed as fw_def macros we havent added fw_defs for gsc-loaded-huc-bins
which explains why "loaded_via_gsc" not getting set anywhere in this series.
Reviewed-by: Alan Previn
On Tue, 2022-04-26 at 17:26 -070
== Series Details ==
Series: drm/i915: move tons of power well initializers to rodata
URL : https://patchwork.freedesktop.org/series/103340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11582_full -> Patchwork_103340v1_full
== Series Details ==
Series: Handle predicate programming
URL : https://patchwork.freedesktop.org/series/103084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11550 -> Patchwork_103084v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915: Change semantics of context isolation reporting to UM (rev2)
URL : https://patchwork.freedesktop.org/series/103343/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_103343v2
== Series Details ==
Series: lrc selftest fixes (rev5)
URL : https://patchwork.freedesktop.org/series/101353/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:2
On Fri, Apr 29, 2022 at 05:21:40PM +0300, Jani Nikula wrote:
> Using compound literals for initialization can be tricky. Lacking a
> const qualifier, they won't end up in rodata, which is probably not
> expected or intended. Add const to move a whopping 136 initializers to
> rodata.
>
> Compare:
>
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUS
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
Cc: CQ Tang
cc: Joonas Lahtinen
Signed-off-b
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
v2:
Extend it for gen8.
Signed-of
Few bug fixes for lrc selftest.
v3:
Extending the first patch for gen8
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Always cancel semaphore on error
drm/i915/selftest: Cl
== Series Details ==
Series: drm/i915: remove unnecessary spin_lock_irq
URL : https://patchwork.freedesktop.org/series/103344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_103344v1
Summary
---
**F
== Series Details ==
Series: drm/i915: Change semantics of context isolation reporting to UM (rev2)
URL : https://patchwork.freedesktop.org/series/103343/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 2022-04-25 at 16:44:14 +, Patchwork wrote:
> == Series Details ==
>
> Series: Handle predicate programming
> URL : https://patchwork.freedesktop.org/series/103084/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11550 -> Patchwork_103084v1
>
This code will not be called by interrupt handler,
so change it to spin_lock.
Signed-off-by: Zhenneng Li
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.
I915_PARAM_HAS_CONTEXT_ISOLATION was already being used as a boolean by
both Iris and Vulkan , and stood for the guarantee that, when creating a
new context, all state set by it will not leak to any other context.
However the actual return value was a bitmask where every bit stood for an
initialis
I915_PARAM_HAS_CONTEXT_ISOLATION was already being used as a boolean by
both Iris and Vulkan , and stood for the guarantee that, when creating a
new context, all state set by it will not leak to any other context.
However the actual return value was a bitmask where every bit stood for an
initialis
== Series Details ==
Series: drm/i915: move tons of power well initializers to rodata
URL : https://patchwork.freedesktop.org/series/103340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_103340v1
Summary
On Thu, Apr 28, 2022 at 02:10:56PM -0700, José Roberto de Souza wrote:
> Frontbuffer updates were scheduling the execution of DRRS work thread
> even if DRRS is not active.
> There was no issues with it because intel_drrs_downclock_work() checks
> if DRRS is active but there is no reason to keep sc
== Series Details ==
Series: drm/i915: Fix assert in i915_ggtt_pin
URL : https://patchwork.freedesktop.org/series/103339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11582 -> Patchwork_103339v1
Summary
---
**FAILUR
== Series Details ==
Series: drm/i915: move tons of power well initializers to rodata
URL : https://patchwork.freedesktop.org/series/103340/
State : warning
== Summary ==
Error: dim checkpatch failed
82d7c7816f0f drm/i915: move tons of power well initializers to rodata
-:16: WARNING:COMMIT_LOG
On Fri, Apr 29, 2022 at 11:23:51AM +0100, Mauro Carvalho Chehab wrote:
Em Fri, 29 Apr 2022 12:10:07 +0200
Greg KH escreveu:
On Fri, Apr 29, 2022 at 10:15:03AM +0100, Mauro Carvalho Chehab wrote:
> HI Greg,
>
> Em Fri, 29 Apr 2022 10:30:33 +0200
> Greg KH escreveu:
>
> > On Fri, Apr 29, 2022 a
On Fri, 29 Apr 2022 05:58:21 -0700, Rodrigo Vivi wrote:
>
> > @@ -1251,7 +1251,7 @@ static int i915_drm_resume(struct drm_device *dev)
> >
> > disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> >
> > - ret = intel_pcode_init(dev_priv);
> > + ret = intel_gt_pcode_init(dev_priv);
>
> I did
== Series Details ==
Series: drm/i915: remove superfluous string helper include (rev3)
URL : https://patchwork.freedesktop.org/series/103086/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11581 -> Patchwork_103086v3
Summary
> -Original Message-
> From: Intel-gfx On Behalf Of
> Bhanuprakash Modem
> Sent: Monday, April 11, 2022 3:21 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; jani.nik...@linux.intel.com;
> ville.syrj...@linux.intel.com; harry.
> +static int output_bpc_show(struct seq_file *m, void *data) {
Can we have a meaningful name instead of 'm' ?
Upon changing this parameter name, you can have my
Reviewed-By: Arun R Murthy
Thanks and Regards,
Arun R Murthy
Using compound literals for initialization can be tricky. Lacking a
const qualifier, they won't end up in rodata, which is probably not
expected or intended. Add const to move a whopping 136 initializers to
rodata.
Compare:
$ objdump --syms drivers/gpu/drm/i915/display/intel_display_power_map.o |
From: Tvrtko Ursulin
Use lockdep_assert_not_held to simplify and correct the code. Otherwise
false positive are hit if lock state is uknown like after a previous
taint.
Signed-off-by: Tvrtko Ursulin
Reported-by: Ville Syrjälä
Reviewed-by: Ville Syrjälä
---
It's not pretty but it fired again a
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable THP on Icelake and beyond
URL : https://patchwork.freedesktop.org/series/103330/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11580 -> Patchwork_103330v1
=
On Mon, 25 Apr 2022 at 16:22, Ramalingam C wrote:
>
> From: Chris Wilson
>
> Userspace may leave predication enabled upon return from the batch
> buffer, which has the consequent of preventing all operation from the
> ring from being executed, including all the synchronisation, coherency
> contro
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable THP on Icelake and beyond
URL : https://patchwork.freedesktop.org/series/103330/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Apr 28, 2022 at 05:39:37PM -0700, Ashutosh Dixit wrote:
> Each gt contains an independent instance of pcode. Extend pcode functions
> to interface with pcode on different gt's. To avoid creating dependency of
> display functionality on intel_gt, new pcode function interfaces are
> exposed i
On Thu, Apr 28, 2022 at 05:39:43PM -0700, Ashutosh Dixit wrote:
> Add the following sysfs file to gt/gtN/.defaults:
> * media_freq_factor
>
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
On Thu, Apr 28, 2022 at 05:39:42PM -0700, Ashutosh Dixit wrote:
> Create a gt/gtN/.defaults directory (similar to
> engine//.defaults) to expose default parameter values for each
> gt in sysfs. Populate the .defaults directory with RPS parameter default
> values in order to allow userspace to rever
On Mon, 25 Apr 2022 at 16:22, Ramalingam C wrote:
>
> From: Chris Wilson
>
> When predication is enabled all commands baring a few (such as MI_BB_END)
> are nop'ed. If we accidentally enable predication while poisoning the
> context, not only is the rest of the poisoning skipped (thus disabling
>
On Mon, 25 Apr 2022 at 16:22, Ramalingam C wrote:
>
> From: Akeem G Abodunrin
>
> When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on tgl+
> devices, HW does not care about certain register address offsets, but
> instead check the following for valid address ranges on specific engine
On Tue, 26 Apr 2022, Jani Nikula wrote:
> Fix the below drm/edid kernel-doc warnings:
>
> drivers/gpu/drm/drm_edid.c:1589: warning: Function parameter or member
> '_edid' not described in 'drm_edid_header_is_valid'
> drivers/gpu/drm/drm_edid.c:1589: warning: Excess function parameter
> 'raw_edid
On Thu, 28 Apr 2022, "Wang, Zhi A" wrote:
> Hi folks:
>
> Here is the pull of gvt-next which fixes the compilation error and warnings
> for the the GVT-g refactor patches:
>
> - Fix a compiling warning of non-static function only having one caller.
> - Fix a potential NULL pointer reference in th
On Fri, Apr 29, 2022 at 11:23:51AM +0100, Mauro Carvalho Chehab wrote:
> Em Fri, 29 Apr 2022 12:10:07 +0200
> Greg KH escreveu:
>
> > On Fri, Apr 29, 2022 at 10:15:03AM +0100, Mauro Carvalho Chehab wrote:
> > > HI Greg,
> > >
> > > Em Fri, 29 Apr 2022 10:30:33 +0200
> > > Greg KH escreveu:
> >
Em Fri, 29 Apr 2022 12:10:07 +0200
Greg KH escreveu:
> On Fri, Apr 29, 2022 at 10:15:03AM +0100, Mauro Carvalho Chehab wrote:
> > HI Greg,
> >
> > Em Fri, 29 Apr 2022 10:30:33 +0200
> > Greg KH escreveu:
> >
> > > On Fri, Apr 29, 2022 at 09:07:57AM +0100, Mauro Carvalho Chehab wrote:
> > >
On Fri, Apr 29, 2022 at 10:15:03AM +0100, Mauro Carvalho Chehab wrote:
> HI Greg,
>
> Em Fri, 29 Apr 2022 10:30:33 +0200
> Greg KH escreveu:
>
> > On Fri, Apr 29, 2022 at 09:07:57AM +0100, Mauro Carvalho Chehab wrote:
> > > Hi Daniel,
> > >
> > > Em Fri, 29 Apr 2022 09:54:10 +0200
> > > Daniel
From: Tvrtko Ursulin
If i915 does not want to use huge pages there is a) no point in setting up
the private mount and b) should former fail, it is misleading to log THP
support is disabled in the caller, which does not even know if callee
tried to enable it.
Fix both by restructuring the flow in
From: Tvrtko Ursulin
We have a statement from HW designers that the GPU read regression when
using 2M pages was fixed from Icelake onwards, which was also confirmed
by bencharking Eero did last year:
"""
When IOMMU is disabled, enabling THP causes following perf changes on
TGL-H (GT1):
10-1
HI Greg,
Em Fri, 29 Apr 2022 10:30:33 +0200
Greg KH escreveu:
> On Fri, Apr 29, 2022 at 09:07:57AM +0100, Mauro Carvalho Chehab wrote:
> > Hi Daniel,
> >
> > Em Fri, 29 Apr 2022 09:54:10 +0200
> > Daniel Vetter escreveu:
> >
> > > On Fri, Apr 29, 2022 at 07:31:15AM +0100, Mauro Carvalho Che
On 27/04/2022 12:34, Adrian Larumbe wrote:
This patch is an attempt at eliminating the old shmem memory region and GEM
object backend, in favour of a TTM-based one that is able to manage objects
placed on both system and local memory.
Known issues:
Many GPU hungs in machines of GEN <= 5. My a
On 28.04.2022 19:43, Siva Mullati wrote:
>
> On 14/04/22 17:41, Balasubramani Vivekanandan wrote:
> > On 04.04.2022 15:01, Mullati Siva wrote:
> >> From: Siva Mullati
> >>
> >> Convert CT commands and descriptors to use iosys_map rather
> >> than plain pointer and save it in the intel_guc_ct_buff
== Series Details ==
Series: Let userspace know when snd-hda-intel needs i915
URL : https://patchwork.freedesktop.org/series/103315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11550_full -> Patchwork_103315v1_full
Summar
On Fri, Apr 29, 2022 at 09:07:57AM +0100, Mauro Carvalho Chehab wrote:
> Hi Daniel,
>
> Em Fri, 29 Apr 2022 09:54:10 +0200
> Daniel Vetter escreveu:
>
> > On Fri, Apr 29, 2022 at 07:31:15AM +0100, Mauro Carvalho Chehab wrote:
> > > Sometimes, device drivers are bound using indirect references,
>
Hi Daniel,
Em Fri, 29 Apr 2022 09:54:10 +0200
Daniel Vetter escreveu:
> On Fri, Apr 29, 2022 at 07:31:15AM +0100, Mauro Carvalho Chehab wrote:
> > Sometimes, device drivers are bound using indirect references,
> > which is not visible when looking at /proc/modules or lsmod.
> >
> > Add a functi
On Fri, Apr 29, 2022 at 07:31:15AM +0100, Mauro Carvalho Chehab wrote:
> Sometimes, device drivers are bound using indirect references,
> which is not visible when looking at /proc/modules or lsmod.
>
> Add a function to allow setting up module references for such
> cases.
>
> Reviewed-by: Dan Wi
== Series Details ==
Series: Let userspace know when snd-hda-intel needs i915
URL : https://patchwork.freedesktop.org/series/103315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11550 -> Patchwork_103315v1
Summary
---
== Series Details ==
Series: Let userspace know when snd-hda-intel needs i915
URL : https://patchwork.freedesktop.org/series/103315/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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