== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev7)
URL : https://patchwork.freedesktop.org/series/100772/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22606
Summary
---
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for e
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm/i91
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 2
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt/
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 ++
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global, engi
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cau
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to w
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse t
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev6)
URL : https://patchwork.freedesktop.org/series/100772/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22605
Summary
---
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101520/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11379_full -> Patchwork_22603_full
Summary
---
**FAILURE**
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev6)
URL : https://patchwork.freedesktop.org/series/100772/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d9e840b8dd7a drm/i915: avoid concurrent writes to aux_inv
-:81: CHECK:BRACES: braces {} should b
== Series Details ==
Series: i915 writeback private framework (rev4)
URL : https://patchwork.freedesktop.org/series/101425/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22604
Summary
---
**SUCCESS
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101023/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11379_full -> Patchwork_22602_full
=
== Series Details ==
Series: i915 writeback private framework (rev4)
URL : https://patchwork.freedesktop.org/series/101425/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915 writeback private framework (rev4)
URL : https://patchwork.freedesktop.org/series/101425/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
224406362f12 drm/i915: Creating writeback pipeline to bypass drm_writeback
framework
-:52: WARNING:FILE_PAT
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 89 +-
drive
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 ++
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files chang
Changes to create a i915 private pipeline to enable the WD transcoder
without relying on the current drm_writeback framework.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 4 +
.../gpu/drm/i915/display/in
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11379 -> Patchwork_22603
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11379 -> Patchwork_22602
Summa
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101520/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101520/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c8d744572c07 drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
bccf33639b42 drm/i915/gt: add gt_is_root() help
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev4)
URL : https://patchwork.freedesktop.org/series/101496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11378_full -> Patchwork_22601_full
Summary
--
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
432adfb1abe5 drm/i915/dg2: Add preemption changes for Wa_14015141709
-:48: CHECK:MACR
From: Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes:
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
- throttle_re
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378_full -> Patchwork_22598_full
Summary
---
**SUCCESS
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├──
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to t
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.h | 5
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and the
From: Akeem G Abodunrin
Starting with DG2, preemption can no longer be controlled using userspace
on a per-context basis. Instead, the hardware only allows us to enable or
disable preemption in a global, system-wide basis. Also, we lose the
ability to specify the preemption granularity (such as
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11378_full -> Patchwork_22597_full
Summary
---
**FAILURE**
S
Hi all,
On Fri, 18 Mar 2022 11:55:44 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm tree got a conflict in:
>
> drivers/gpu/drm/bridge/Kconfig
>
> between commit:
>
> 3c3384050d68 ("drm: Don't make DRM_PANEL_BRIDGE dependent on
> DRM_KMS_HELPERS")
>
> from the drm
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/bridge/Kconfig
between commit:
3c3384050d68 ("drm: Don't make DRM_PANEL_BRIDGE dependent on DRM_KMS_HELPERS")
from the drm-misc-fixes tree and commit:
803abfd8dda5 ("drm: bridge: fix unmet dependency on
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev4)
URL : https://patchwork.freedesktop.org/series/101496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378 -> Patchwork_22601
Summary
---
*
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev4)
URL : https://patchwork.freedesktop.org/series/101496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev4)
URL : https://patchwork.freedesktop.org/series/101496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72f9ed8364ec drm/i915/bios: Extract struct lvds_lfp_data_ptr_table
8d0061ecd718 drm/i915/bios: Make
From: Ville Syrjälä
Modern VBTs (seem at least on TGL with VBT version 240) no
longer contain the LFP data table pointers block (42). We
are expecting to have one in order to be able to parse the
LFP data block (41), so let's make one up.
Since the fp_timing table has variable size we must someh
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev3)
URL : https://patchwork.freedesktop.org/series/101496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378 -> Patchwork_22599
Summary
---
*
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/dg2: Add preemption changes for
Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101070/
State : failure
== Summary ==
Applying: drm/i915/dg2: Add preemption changes for Wa_14015141709
Applying: drm/i915/d
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378 -> Patchwork_22598
Summary
---
**SUCCESS**
No r
On Thu, Mar 17, 2022 at 09:02:46PM +0200, Jani Nikula wrote:
> On Thu, 17 Mar 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make a copy of each VB data block with a guaranteed minimum
> > size. The extra (if any) will just be left zeroed.
>
> *VBT
>
> >
> > This means we don't have
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev3)
URL : https://patchwork.freedesktop.org/series/101496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling (rev3)
URL : https://patchwork.freedesktop.org/series/101496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f78f0208e580 drm/i915/bios: Extract struct lvds_lfp_data_ptr_table
b9aaa74b14b4 drm/i915/bios: Make
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101503/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101503/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eaf2d6ffbe31 drm/i915/guc: Update GuC ADS size for error capture lists
-:40: WARNING:FILE_PATH_CHANGES: added, moved o
== Series Details ==
Series: drm/i915/sdvo: prefer __packed over __attribute__((packed))
URL : https://patchwork.freedesktop.org/series/101497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11376_full -> Patchwork_22596_full
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378 -> Patchwork_22597
Summary
---
**SUCCESS**
No regressi
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
148ae63a423d drm/i915/dmc: simplify intel_dmc_load_program() conditions
f5b3417a7183 drm/i915/dmc: move assert_dmc_loaded() t
From: Ville Syrjälä
Currently get_lvds_fp_timing() still returns a pointer to the original
data block rather than our copy. Let's convert the data pointer offsets
to be relative to the data block rather than the whole BDB. With that
we can make get_lvds_fp_timing() return a pointer to the copy.
From: Ville Syrjälä
Make a copy of each VB data block with a guaranteed minimum
size. The extra (if any) will just be left zeroed.
This means we don't have to worry about going out of bounds
when accessing any of the structure members. Otherwise that
could easliy happen if we simply get the vers
== Series Details ==
Series: drm/i915/bios: Rework BDB block handling
URL : https://patchwork.freedesktop.org/series/101496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11376_full -> Patchwork_22595_full
Summary
---
On Thu, Mar 17, 2022 at 10:04:13PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 09:10:37PM +0200, Jani Nikula wrote:
> > On Thu, 17 Mar 2022, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Currently get_lvds_fp_timing() still returns a pointer to the original
> > > data block
On Thu, Mar 17, 2022 at 09:10:37PM +0200, Jani Nikula wrote:
> On Thu, 17 Mar 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently get_lvds_fp_timing() still returns a pointer to the original
> > data block rather than our copy. Let's convert the data pointer offsets
> > to be rel
On Thu, Mar 17, 2022 at 08:36:20PM +0200, Jani Nikula wrote:
Clean up the massive i915_reg.h a bit with this isolated set of
registers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++
driv
On Thu, Mar 17, 2022 at 08:36:19PM +0200, Jani Nikula wrote:
The macros are now only needed within intel_dmc.c, so move them there.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
Lucas De Marchi
On Thu, Mar 17, 2022 at 08:36:18PM +0200, Jani Nikula wrote:
Only intel_dmc.c should be accessing dmc details directly.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
Lucas De Marchi
On Thu, Mar 17, 2022 at 08:36:17PM +0200, Jani Nikula wrote:
Register the DMC debugfs file only on platforms that support
DMC. There's no point in having a no-op debugfs file.
It seems this would not change much the behavior (fail on open vs fail
on read). But the code in igt is suspicious:
On Thu, Mar 17, 2022 at 08:36:16PM +0200, Jani Nikula wrote:
i915_reg_t is supposed to be a somewhat opaque data type, not to be
looked inside.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
but maybe also already clean up the remaining one?
$ git grep "i915_reg_t.*= *{ *}"
drive
== Series Details ==
Series: Add DP MST DSC support to i915
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11376_full -> Patchwork_22594_full
Summary
---
**SUCCES
On Thu, Mar 17, 2022 at 08:36:15PM +0200, Jani Nikula wrote:
Continue localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
Lucas De Marchi
On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
Start localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12
drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++
driv
On Thu, Mar 17, 2022 at 08:36:13PM +0200, Jani Nikula wrote:
intel_dmc_load_program() is only ever called when
intel_dmc_has_payload() is true. Move the condition within
intel_dmc_load_program() to let it be called directly.
Also note that intel_dmc_has_payload() will always return false when
HA
On Thu, 17 Mar 2022, "Navare, Manasi" wrote:
> On Thu, Mar 17, 2022 at 11:28:03AM -0700, Navare, Manasi wrote:
>> On Thu, Mar 17, 2022 at 05:35:43PM +0200, Jani Nikula wrote:
>> > On Wed, 16 Mar 2022, "Navare, Manasi" wrote:
>> > > On Wed, Mar 16, 2022 at 09:48:17AM +0200, Jani Nikula wrote:
>> >
On Thu, Mar 17, 2022 at 12:05:47PM -0700, Navare, Manasi wrote:
> On Thu, Mar 17, 2022 at 08:52:52PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 15, 2022 at 04:38:56PM -0700, Manasi Navare wrote:
> > > This patch abstracts pieces of hsw_crtc_enable corresponding to different
> > > Bspec enable sequ
On Thu, 17 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently get_lvds_fp_timing() still returns a pointer to the original
> data block rather than our copy. Let's convert the data pointer offsets
> to be relative to the data block rather than the whole BDB. With that
> we can mak
On Thu, Mar 17, 2022 at 08:52:52PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 15, 2022 at 04:38:56PM -0700, Manasi Navare wrote:
> > This patch abstracts pieces of hsw_crtc_enable corresponding to different
> > Bspec enable sequence steps into separate functions.
> > This helps to call them in a spe
== Series Details ==
Series: drm/i915/sdvo: prefer __packed over __attribute__((packed))
URL : https://patchwork.freedesktop.org/series/101497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11376 -> Patchwork_22596
Summary
On Thu, 17 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make a copy of each VB data block with a guaranteed minimum
> size. The extra (if any) will just be left zeroed.
*VBT
>
> This means we don't have to worry about going out of bounds
> when accessing any of the structure members
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cau
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm/i91
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 ++
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to w
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse t
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 2
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for e
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt/
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global, engi
On Tue, Mar 15, 2022 at 04:38:56PM -0700, Manasi Navare wrote:
> This patch abstracts pieces of hsw_crtc_enable corresponding to different
> Bspec enable sequence steps into separate functions.
> This helps to call them in a specific order for bigjoiner master/slave
> in a cleaner fashion.
>
> Cc:
Clean up the massive i915_reg.h a bit with this isolated set of
registers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gp
The macros are now only needed within intel_dmc.c, so move them there.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4
drivers/gpu/drm/i915/display/intel_dmc.h | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/
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