On Thu, Mar 10, 2022 at 12:26:12PM +, Tvrtko Ursulin wrote:
>
> On 10/03/2022 05:18, Matt Atwood wrote:
> > Newer platforms have DSS that aren't necessarily available for both
> > geometry and compute, two queries will need to exist. This introduces
> > the first, when passing a valid engine c
== Series Details ==
Series: drm/i915: Reject unsupported TMDS rates on ICL+ (rev2)
URL : https://patchwork.freedesktop.org/series/101304/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11353_full -> Patchwork_22550_full
Sum
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/sseu: Don't overallocate
subslice storage
URL : https://patchwork.freedesktop.org/series/101305/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353_full -> Patchwork_22549_full
==
On Fri, Mar 11, 2022 at 12:06 PM Jason Baron wrote:
>
>
>
> On 3/10/22 23:47, Jim Cromie wrote:
> > DRM defines/uses 10 enum drm_debug_category's to create exclusive
> > classes of debug messages. To support this directly in dynamic-debug,
> > add the following:
> >
> > - struct _ddebug.class_id:
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev3)
URL : https://patchwork.freedesktop.org/series/101222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353_full -> Patchwork_22547_full
==
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101307/
State : failure
== Summary ==
Applying: drm/i915/guc: Update GuC ADS size for error capture lists
Applying: drm/i915/guc: Add XE_LP static registers for GuC error capture.
Applying
== Series Details ==
Series: drm/i915: Reject unsupported TMDS rates on ICL+ (rev2)
URL : https://patchwork.freedesktop.org/series/101304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22550
Summary
-
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cau
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse t
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm/i91
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to w
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global, engi
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for e
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 2
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 ++
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt/
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
== Series Details ==
Series: drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()
URL : https://patchwork.freedesktop.org/series/101301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353_full -> Patchwork_22546_full
On Fri, Mar 11, 2022 at 09:22:14AM +0800, Lee Shawn C wrote:
> drm_find_cea_extension() always look for a top level CEA block. Pass
> ext_index from caller then this function to search next available
> CEA ext block from a specific EDID block pointer.
>
> v2: save proper extension block index if C
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/sseu: Don't overallocate
subslice storage
URL : https://patchwork.freedesktop.org/series/101305/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22549
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/sseu: Don't overallocate
subslice storage
URL : https://patchwork.freedesktop.org/series/101305/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be che
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/sseu: Don't overallocate
subslice storage
URL : https://patchwork.freedesktop.org/series/101305/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0bb362f30a14 drm/i915/sseu: Don't overallocate subslice storage
-:
== Series Details ==
Series: drm/i915: Reject unsupported TMDS rates on ICL+
URL : https://patchwork.freedesktop.org/series/101304/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22548
Summary
---
*
When running on Xe_HP or beyond, let's use an updated format for
describing topology in our error state dumps and debugfs to give a
more accurate view of the hardware:
- Just report DSS directly without the legacy "slice0" output that's no
longer meaningful.
- Indicate whether each DSS is acc
Xe_HP removed "slice" as a first-class unit in the hardware design.
Instead we now have a single pool of subslices (which are now referred
to as "DSS") that different hardware units have different ways of
grouping ("compute slices," "geometry slices," etc.). For the purposes
of topology representa
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev3)
URL : https://patchwork.freedesktop.org/series/101222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22547
Summar
Thanks Umesh for reviewing and for the conditional Rb ... a follow up
on the conditions for #1 below (as per our offline conversation)... and
i will fix #2 as expected.
On 3/11/2022 10:16 AM, Umesh Nerlige Ramappa wrote:
On Sat, Feb 26, 2022 at 01:55:38AM -0800, Alan Previn wrote: +static int
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev3)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev3)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9d0ea3d28235 drm/i915/dsi: Pass fixed_mode to *_dsi_add_properties()
1c936de54ac4 drm/
== Series Details ==
Series: drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()
URL : https://patchwork.freedesktop.org/series/101301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22546
Summ
From: Ville Syrjälä
ICL+ PLLs can't genenerate certain frequencies. Running the PLL
algorithms through for all frequencies 25-594MHz we see a gap just
above 500 MHz. Specifically 500-522.8MHZ for TC PLLs, and 500-533.2
MHz for combo PHY PLLs. Reject those frequencies hdmi_port_clock_valid()
so th
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Fix HPD short pulse
handling for eDP
URL : https://patchwork.freedesktop.org/series/101299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11353 -> Patchwork_22545
On Fri, Mar 11, 2022 at 11:01:01PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> > On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> > >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> > >> On Fri, Mar 11, 2022 at 11:00:09A
On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> >> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> >> > On Thu, Mar 10, 2022 at 10:15:42
On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > Xe_HP removed "slice" as a first-class unit i
On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > > Instead we now have a single
On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > Instead we now have a single pool of subslices (which are now referred
> > to as "DSS") that dif
From: Ville Syrjälä
Store the fixed_mode and downclock_mode as a real list,
in preparation for exposing other supported modes as well.
v2: Init the list in intel_sdvo_connector_alloc() too
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_connector.c| 2 +
.../drm/i915/disp
Because VLV_GT_RENDER_RC6 == GEN6_GT_GFX_RC6, the IS_VALLEYVIEW() check is
not needed. Neither is the check present in other code paths which call
intel_rc6_residency_ns() (in functions gen6_drpc(), rc6_residency() and
rc6_residency_ms_show()).
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i
On Thu, Mar 10, 2022 at 10:15:43PM -0800, Matt Roper wrote:
When running on Xe_HP or beyond, let's use an updated format for
describing topology in our error state dumps and debugfs to give a
more accurate view of the hardware:
- Just report DSS directly without the legacy "slice0" output that's
Thanks for reviewing and for the Rvb Umesh. ... will fix
guc_capture_alloc_one_node as per below.
...alan
On 3/11/2022 11:40 AM, Umesh Nerlige Ramappa wrote:
On Sat, Feb 26, 2022 at 01:55:39AM -0800, Alan Previn wrote:
In the rare but possible scenario where we are in the midst of
multiple Gu
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev2)
URL : https://patchwork.freedesktop.org/series/101222/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11352 -> Patchwork_22544
Summar
On Sat, Feb 26, 2022 at 01:55:39AM -0800, Alan Previn wrote:
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset
drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: warning: symbol
'intel_sseu_get_geometry_subslices' was not declared. Should it be static?
Reported-by: kernel test robot
Signed-off-by: kernel test robot
---
drivers/gpu/drm/i915/gt/intel_sseu.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-
ce-storage/20220311-141705
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-rhel-8.3-kselftests
(https://download.01.org/0day-ci/archive/20220312/202203120322.okxcdfs7-...@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
reproduce:
# apt-get inst
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev2)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev2)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dda13ef0a9df drm/i915/dsi: Pass fixed_mode to *_dsi_add_properties()
e17b931fdd3c drm/
On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
Xe_HP removed "slice" as a first-class unit in the hardware design.
Instead we now have a single pool of subslices (which are now referred
to as "DSS") that different hardware units have different ways of
grouping ("compute slices," "geo
If a error happens and sink_not_reliable is set, PSR should be disabled
for good but that is not happening.
It would be disabled by the function handling the PSR error but then
on the next fastset it would be enabled again in
_intel_psr_post_plane_update().
It would only be disabled for good in the
Commit 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel
powered off") completely broke short pulse handling for eDP as it is
usually generated by sink when it is displaying image and there is
some error or status that source needs to handle.
When power panel is enabled, this state is eno
On Tue, Mar 08, 2022 at 10:17:42PM +0530, Balasubramani Vivekanandan wrote:
This patch is continuation of the effort to move all pointers in i915,
which at any point may be pointing to device memory or system memory, to
iosys_map interface.
More details about the need of this change is explained
On Tue, Mar 08, 2022 at 10:17:42PM +0530, Balasubramani Vivekanandan wrote:
This patch is continuation of the effort to move all pointers in i915,
which at any point may be pointing to device memory or system memory, to
iosys_map interface.
More details about the need of this change is explained
On Sat, Feb 26, 2022 at 01:55:38AM -0800, Alan Previn wrote:
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 reg
From: Ville Syrjälä
Store the fixed_mode and downclock_mode as a real list,
in preparation for exposing other supported modes as well.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_connector.c| 2 +
.../drm/i915/display/intel_display_debugfs.c | 9 +-
.../drm/i915/disp
From: Ville Syrjälä
Let's start supporting static DRRS by trying to match the refresh
rate the user has requested, assuming the panel supports suitable
timings.
For now we stick to just our current two timings:
- fixed_mode: the panel's preferred mode
- downclock_mode: the lowest refresh rate mo
From: Ville Syrjälä
No reason to keep the DRRS enable/disable hidden insider the encoder
hooks. Let's just move them all the way up into platform independent
code so that all platforms get to use them. These are nops when
the state computation doesn't think DRRS is possible.
Reviewed-by: Jani Ni
From: Ville Syrjälä
Nothing special about ivb+ here, if DRRS works on ivb+ port A
it should work just as well on ilk/snb. So let's enable
that.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ---
drivers/gpu/drm/i915/display/
From: Ville Syrjälä
Ger rid of one more ugly crtc->config usage by storing the DRRS
state under intel_crtc. intel_drrs_enable() copies what it needs
from the crtc state, after which DRRS can be blissfully ignorant
of anything going on around it.
This also lets multiple pipes do DRRS simultanousl
From: Ville Syrjälä
The DRRS code has no use for the intel_dp, replace it with
just a crtc pointer. This is just an intermediate step towards
making DRRS truly per-crtc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +-
.../drm/i915/display/intel_display_d
From: Ville Syrjälä
Add helper to get the drrs type as a string, and use it
in a couple of places. Also pimp the debugfs output a bit
while at it.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 19 +++
drivers/gpu/drm/i915/display/intel_drrs.c
From: Ville Syrjälä
Add a helper to determine which type of DRRS the panel supports.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_drrs.c | 10 +++---
drivers/gpu/drm/i915/display/intel_panel.c | 10 ++
drivers/gpu/drm/i915/display/intel_panel.h | 2 ++
3 fi
From: Ville Syrjälä
There are a couple of cases where we essentially just want to
get/check the preferred fixed mode of the panel. Add a small
helper for that to abstract away the direct pointer lookup.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c| 3 ++-
driver
From: Ville Syrjälä
Several connectors want to return the fixed_mode from .get_modes(),
add a helper to do that (and hide the details inside intel_panel.c).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c| 13 ++---
drivers/gpu/drm/i915/display/intel_dsi.c
From: Ville Syrjälä
Abstract away the details on where we store the fixed/downclock
modes, and also how we select them. Will be useful for static
DRRS (aka. allowing the user to select the refresh rate for the
panel).
We pass in the user requested mode to intel_panel_fixed_mode()
so that in the
From: Ville Syrjälä
When we found a downclock mode dev_priv->drrs.type is just a
straight copy of dev_priv->vbt.drrs_type. And in case we
couldn't find a downclock mode can_enable_drrs() won't let
us enable DRRS anyway so the minor distinction between the
two is irrelevant. So let's just nuke dev
From: Ville Syrjälä
No need for all this connector type special casing. If the
connector has a fixed mode just print it, otherwise don't.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_debugfs.c | 24 +++
1 file changed, 9 insertions(+), 15 deletions(-)
d
From: Ville Syrjälä
We want to eventually get rid of the connector->panel.fixed_mode
pointer so avoid using it during LVDS setup. Since this all
happens during the encoder init we already have the fixed_mode
around, just pass that in.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/displ
From: Ville Syrjälä
We want to stop using connector->panel.fixed_mode directtly.
In order to look it up in the future we'll need to have the
requested mode around, so pass that in fully (instead of just
passing bits of it).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sd
From: Ville Syrjälä
Fix/clean up the DRRS code sufficiently that I feel
comfortable enabling it on all ilk+ CPU eDP ports.
PCH ports still need a bit of work.
The other thing I slapped on top is the beginnings of
static DRRS support (ie. actually changing the refresh
rate based on what the user
From: Ville Syrjälä
We want to eventually get rid of the connector->panel.fixed_mode
pointer so avoid using it during DSI property setup. Since this
all happens during the encoder init we already have the fixed_mode
around, just pass that in.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i9
On Fri, Mar 11, 2022 at 01:05:49PM +, Souza, Jose wrote:
> On Thu, 2022-03-10 at 23:52 +0200, Ville Syrjälä wrote:
> > On Thu, Mar 10, 2022 at 12:05:17PM -0800, José Roberto de Souza wrote:
> > > Commit 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel
> > > powered off") completely br
On Fri, Mar 11, 2022 at 10:12:56AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Remove GEN12_SFC_DONE_MAX from register defs header
> URL : https://patchwork.freedesktop.org/series/101270/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11350
On Fri, Mar 11, 2022 at 12:06:38PM +0200, Jani Nikula wrote:
> early-quirks.c is the only user of drm/i915_drm.h that also needs
> drm/i915_pciids.h. Include the masses of PCI ID macros only where
> needed.
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Cc: x...@kernel.org
> Signed-off-b
== Series Details ==
Series: series starting with [1/3] drm/i915/pciids: add common
INTEL_VGA_DEVICE_INIT macro
URL : https://patchwork.freedesktop.org/series/101280/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11351_full -> Patchwork_22542_full
applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-1
ce-storage/20220311-141705
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-debian-10.3
(https://download.01.org/0day-ci/archive/20220311/202203112245.edvnthye-...@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
reproduce (this is a W=1 build):
== Series Details ==
Series: drm/i915: Avoid explicit IRQ-off sections.
URL : https://patchwork.freedesktop.org/series/101288/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11351 -> Patchwork_22543
Summary
---
**FAIL
== Series Details ==
Series: series starting with [1/3] drm/i915/pciids: add common
INTEL_VGA_DEVICE_INIT macro
URL : https://patchwork.freedesktop.org/series/101280/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11351 -> Patchwork_22542
==
On Thu, 2022-03-10 at 23:52 +0200, Ville Syrjälä wrote:
> On Thu, Mar 10, 2022 at 12:05:17PM -0800, José Roberto de Souza wrote:
> > Commit 13ea6db2cf24 ("drm/i915/edp: Ignore short pulse when panel
> > powered off") completely broke short pulse handling for eDP as it is
> > usually generated by si
== Series Details ==
Series: series starting with [1/3] drm/i915/pciids: add common
INTEL_VGA_DEVICE_INIT macro
URL : https://patchwork.freedesktop.org/series/101280/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be c
Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired
The !irqs_disabled() check triggers on PREEMPT_RT even with
i915_sched_engine::lock acquired. The reason is the lock is transformed
into a sleeping lock on PREEMPT_RT and does not disable interrupts.
There is no need to check for disabled interrupts. The lockdep
annotation below already check if t
Hi,
these two patches are from the RT queue. They avoid IRQ-off checks and
IRQ-off regions which are not valid/ possible on PREEMPT_RT and are not
needed on !PREEMPT_RT.
Sebastian
== Series Details ==
Series: series starting with [1/2] x86/gpu: include drm/i915_pciids.h directly
in early quirks
URL : https://patchwork.freedesktop.org/series/101279/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11350_full -> Patchwork_22541_full
On Thu, 10 Mar 2022 at 12:28, Matthew Auld wrote:
>
> From: CQ Tang
>
> When system does not have mappable aperture, ggtt->mappable_end=0. In
> this case if we pass PIN_MAPPABLE when pinning vma, the pinning code
> will return -ENOSPC. So conditionally set PIN_MAPPABLE if HAS_GMCH().
>
> Suggeste
== Series Details ==
Series: series starting with [1/2] x86/gpu: include drm/i915_pciids.h directly
in early quirks
URL : https://patchwork.freedesktop.org/series/101279/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11350 -> Patchwork_22541
==
The series is Acked-by: Nirmoy Das
On 10/03/2022 13:27, Matthew Auld wrote:
The leftover bits around dealing with stolen-local memory + small BAR, plus
some related fixes.
v2: some tweaks based on feedback from Ville
On 11/03/2022 10:07, Tvrtko Ursulin wrote:
On 10/03/2022 20:24, John Harrison wrote:
On 3/10/2022 01:27, Tvrtko Ursulin wrote:
On 09/03/2022 21:16, John Harrison wrote:
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A w
On Wed, 9 Mar 2022 at 11:46, Matthew Auld wrote:
>
> On 09/03/2022 11:19, Katragadda, MastanX wrote:
> > Hi,
> >
> > can we have ack? or we need to do anything further to get r-o-b.
>
> There was just the potential strangeness around len <= 0, and exactly
> how we are meant to handle that, but if
== Series Details ==
Series: series starting with [1/2] x86/gpu: include drm/i915_pciids.h directly
in early quirks
URL : https://patchwork.freedesktop.org/series/101279/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
Redefine INTEL_VGA_DEVICE_INIT() instead of INTEL_VGA_DEVICE() for
subplatform init. This is only for completeness as we don't use
subplatforms for Quanta devices.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
Use designated initializers for struct pci_device_id to avoid the
dependency on struct pci_device_id remaining unchanged. Recently, commit
343b7258687e ("PCI: Add 'override_only' field to struct pci_device_id")
added a new member leading to warnings about missing field initializers.
Any userspace
Add a shared abstraction for the initialization to help follow-up
changes.
Signed-off-by: Jani Nikula
---
include/drm/i915_pciids.h | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 3609f3254f
On 3/9/2022 9:30 PM, Matthew Brost wrote:
On Sat, Feb 26, 2022 at 01:55:29AM -0800, Alan Previn wrote:
+intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type,
u32 classid,
+ struct file **fileoutptr)
+{
+ struct __guc_state_capture_priv *gc = guc->
== Series Details ==
Series: drm/i915/gt: Remove GEN12_SFC_DONE_MAX from register defs header
URL : https://patchwork.freedesktop.org/series/101270/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11350_full -> Patchwork_22539_full
===
On 10/03/2022 20:24, John Harrison wrote:
On 3/10/2022 01:27, Tvrtko Ursulin wrote:
On 09/03/2022 21:16, John Harrison wrote:
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow Op
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