On Thu, Feb 17, 2022 at 06:09:53PM +, Matthew Auld wrote:
On Thu, 17 Feb 2022 at 17:55, Lucas De Marchi wrote:
This was useful for early development of lmem, but it's not used
anymore, so remove it.
v2: Remove unneeded fields from struct intel_memory_region
Cc: Chris Wilson
Cc: Matthew
On Fri, Feb 18, 2022 at 01:08:36PM +, Patchwork wrote:
== Series Details ==
Series: drm/i915: Kill the fake lmem support (rev2)
URL : https://patchwork.freedesktop.org/series/100276/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22319_full
===
== Series Details ==
Series: drm: Review of mode copies
URL : https://patchwork.freedesktop.org/series/100394/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11248_full -> Patchwork_22330_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/dg2: Add relocation exception
URL : https://patchwork.freedesktop.org/series/100433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11254 -> Patchwork_22338
Summary
---
**SUCCESS*
On Fri, Feb 18, 2022 at 01:54:36AM -0800, Lucas De Marchi wrote:
This is an alternative to
https://patchwork.freedesktop.org/series/100151/
("drm/i915/dg2: 5th Display output").
After talking with Matt Roper, it seems the issue calibrating the phy
happens sporadically on any phy. So, there isn'
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads
URL : https://patchwork.freedesktop.org/series/100428/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11254 -> Patchwork_22337
Summary
---
== Series Details ==
Series: drm/i915/dg2: Do not use phy E
URL : https://patchwork.freedesktop.org/series/100390/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11248_full -> Patchwork_22329_full
Summary
---
**FAILUR
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads
URL : https://patchwork.freedesktop.org/series/100428/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/ttm: fixup the mock_bo (rev2)
URL : https://patchwork.freedesktop.org/series/100255/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11248_full -> Patchwork_22328_full
Summary
---
On Sat, Feb 19, 2022 at 12:17:52AM +0530, Ramalingam C wrote:
> From: Ayaz A Siddiqui
>
> Xe-HP and latest devices support Flat CCS which reserved a portion of
> the device memory to store compression metadata, during the clearing of
> device memory buffer object we also need to clear the associa
On 2/14/2022 17:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
safe to call the GuC context clean
On Thu, Jan 06, 2022 at 04:55:36PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.
Example of the
On Fri, 18 Feb 2022 14:38:53 -0800, Lucas De Marchi wrote:
>
> The move to softpin in igt is ongoing and should land soon.
> Meanwhile, like was done for ADL and RKL, add an exception to allow
> running the igt display tests before that conversion is complete
> so we can unblock CI.
One example fa
== Series Details ==
Series: drm/i915/rps/tgl+: Remove RPS interrupt support
URL : https://patchwork.freedesktop.org/series/100426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11253 -> Patchwork_22336
Summary
---
*
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev3)
URL : https://patchwork.freedesktop.org/series/1/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11253 -> Patchwork_22335
Summary
---
**FAILURE**
> -Original Message-
> From: Intel-gfx On Behalf Of Tejas
> Upadhyay
> Sent: Thursday, January 27, 2022 2:35 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/adl-n: Add PCH Support for Alder Lake
> N
>
> Add the PCH ID for ADL-N.
>
> Signed-off-by: Teja
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev3)
URL : https://patchwork.freedesktop.org/series/1/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev3)
URL : https://patchwork.freedesktop.org/series/1/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c5741d746ef drm_cache: Add logic for wbvind_on_all_cpus
-:34: WARNING:INCLUDE_LINUX: Use #include instead of
The move to softpin in igt is ongoing and should land soon.
Meanwhile, like was done for ADL and RKL, add an exception to allow
running the igt display tests before that conversion is complete
so we can unblock CI.
Cc: Zbigniew Kempczynski
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Jason Ekstrand
C
On Thu, Feb 17, 2022 at 05:40:51PM +0800, kernel test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b
commit: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b [1/1] drm/i915: Add DG2 PCI IDs
config: x86_64-randconfig-a011
(h
+Daniele, +Rodrigo
On Tue, Feb 08, 2022 at 11:14:57PM -0800, Lucas De Marchi wrote:
On Mon, Feb 07, 2022 at 12:36:42PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Cera
On Wed, Feb 16, 2022 at 09:41:41AM -0800, Lucas De Marchi wrote:
> Use the saved ads_map to prepare the golden context. One difference from
> the init context is that this function can be called before there is a
> gem object (and thus the guc->ads_map) to calculare the size of the
> golden context
From: John Harrison
Compute workloads are inherantly not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled. This is undesirable with GuC
submission as it prevents per engine reset of hung contexts. Hence t
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset of the hung engine.
However, this does not work well in G
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 seconds. Rather than allowing the user to set higher values and
From: John Harrison
Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang detection was left to the heartbeat
and its (longer) timeout. This is undesirable with GuC submission
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
grep confirmed those are the only places we use the pool that wa
On Wed, Feb 16, 2022 at 09:41:47AM -0800, Lucas De Marchi wrote:
> Now we have the access to content of GuC ADS either using iosys_map
> API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
> be updates using the bare pointer anymore.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query help
On Wed, Feb 16, 2022 at 09:41:46AM -0800, Lucas De Marchi wrote:
> Now that all the called functions from __guc_ads_init() are converted to
> use ads_map, stop using ads_blob in __guc_ads_init().
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Br
On Wed, Feb 16, 2022 at 09:41:45AM -0800, Lucas De Marchi wrote:
> Now that the regset list is prepared, convert guc_mmio_reg_state_init()
> to use iosys_map to copy the array to the final location and
> initialize additional fields in ads.reg_state_list.
>
> v2: Just use an offset instead of temp
TGL+ and newer platforms don't support RPS up and low interruption
limits.
It is not used for broadwell and newer plaforms that supports
execlist but here making sure that it is explicit not used even in
debug scenarios.
BSpec: 33301
BSpec: 52069
BSpec: 9520
HSD: 1405911647
Cc: Vinay Belgaumkar
S
On Wed, Feb 16, 2022 at 09:41:44AM -0800, Lucas De Marchi wrote:
> Use iosys_map to write the fields ads.capture_*.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Lucas De Marchi
Reviewed-b
Quoting Janusz Krzysztofik (2022-02-18 17:08:41)
> Hi Chris,
>
> On Friday, 18 February 2022 17:03:01 CET Chris Wilson wrote:
> > Quoting Janusz Krzysztofik (2022-02-18 15:19:35)
> > > @@ -206,15 +229,19 @@ static struct pci_device
> > > *__igt_device_get_pci_device(int fd)
> > >
On Wed, Feb 16, 2022 at 09:41:43AM -0800, Lucas De Marchi wrote:
> Use iosys_map to write the fields system_info.mapping_table[][].
> Since we already have the info_map around where needed, just use it
> instead of going through guc->ads_map.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Danie
On Wed, Feb 16, 2022 at 09:41:42AM -0800, Lucas De Marchi wrote:
> In the other places in this function, guc->ads_map is being protected
> from access when it's not yet set. However the last check is actually
> about guc->ads_golden_ctxt_size been set before. These checks should
> always match as
On Wed, Feb 16, 2022 at 09:41:40AM -0800, Lucas De Marchi wrote:
> Use iosys_map_memset() to zero the private data as ADS may be either
> on system or IO memory.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
On Thu, Feb 17, 2022 at 06:02:23PM +0530, Tejas Upadhyay wrote:
> We dont need to implement reset_domain in intel_engine
> _setup(), but can be done as a helper. Implemented as
> engine->reset_domain = get_reset_domain().
>
> Cc: Rodrigo Vivi
> Signed-off-by: Tejas Upadhyay
it is a good non-fun
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use iosys_map (rev4)
URL : https://patchwork.freedesktop.org/series/99711/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11250 -> Patchwork_22334
Summary
---
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use iosys_map (rev4)
URL : https://patchwork.freedesktop.org/series/99711/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use iosys_map (rev4)
URL : https://patchwork.freedesktop.org/series/99711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
554203971464 iosys-map: Add offset to iosys_map_memcpy_to()
5a68a5465b0a iosys-map: Add a f
Ramalingam C writes:
> On 2022-02-18 at 18:06:00 +, Robert Beckett wrote:
>>
>> If desired, we can make the wording clearer, maybe something like:
>>
>> "To keep things simple for userland, we mandate that any GTT mappings
>> must be aligned to 2MB. The kernel will internally pad them out t
== Series Details ==
Series: drm/i915: Enable DG2
URL : https://patchwork.freedesktop.org/series/100419/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11250 -> Patchwork_22333
Summary
---
**SUCCESS**
No regression
On 2/18/2022 10:47 AM, Ramalingam C wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
== Series Details ==
Series: drm/i915: Enable DG2
URL : https://patchwork.freedesktop.org/series/100419/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Enable DG2
URL : https://patchwork.freedesktop.org/series/100419/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecf3a6aabe11 drm/i915/dg2: Define GuC firmware version for DG2
9d7f9f8a3467 drm/i915: Fix for PHY_MISC_TC1 offset
-:49: CHECK:M
Just a note here. To enable the dg2 with basic support sooner on CI we
have taken a subset of this series separtely at
https://patchwork.freedesktop.org/series/100419/
Remaining patches will be pursued on top the above series. Thanks for
the review comments. We will fix them working with reviewers
== Series Details ==
Series: drm/i915: SAGV fixes (rev3)
URL : https://patchwork.freedesktop.org/series/100091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22327_full
Summary
---
**SUCCESS**
On 2022-02-18 at 18:06:00 +, Robert Beckett wrote:
>
>
> On 18/02/2022 13:47, Ramalingam C wrote:
> > On 2022-02-17 at 20:57:35 -0800, Jordan Justen wrote:
> > > Robert Beckett writes:
> > >
> > > > From: Matthew Auld
> > > >
> > > > On discrete platforms like DG2, we need to support a mi
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Ad
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
v4: Kdoc modification.
v3: fix typos and less emphasis
v2: Fixed su
From: CQ Tang
Platforms of XeHP and beyond support 3D surface (buffer) compression and
various compression formats. This is accomplished by an additional
compression control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of
From: Matthew Auld
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
v2(Ram)
- Document the ppGTT layout and add a better description for the
different windows.
Signed-off-by: Matthew Aul
Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.
With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.
v6:
* minor doc formatting
S
From: Matthew Auld
On some platforms we have alignment restrictions when accessing LMEM
from the GTT. In the next few patches we need to be able to modify the
page-tables directly via the GTT itself.
Suggested-by: Ramalingam C
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
From: Matthew Auld
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed
From: Robert Beckett
add test to check handling of misaligned offsets and sizes
v4:
* remove spurious blank lines
* explicitly cast intel_region_id to intel_memory_type in misaligned_pin
Reported-by: kernel test robot
v6:
* use NEEDS_COMPACT_PT instead of hard coding for
From: Matthew Auld
discrete cards optimise 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no long
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Si
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
availa
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/g
Enabling the Dg2 on drm/i915.
This series adds support for 64k pagesize and documents the uapi
impacts. And also adds basic flat-ccs enabling patches to
support the local memory initialization and object creation. Kdoc is
added to document the Flat-ccs support.
Flat-ccs modifiers will be enabled
== Series Details ==
Series: drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaround
(rev2)
URL : https://patchwork.freedesktop.org/series/100404/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11250 -> Patchwork_22332
===
On Fri, Feb 18, 2022 at 11:22:41AM +, Matthew Auld wrote:
We already completed the steps for this.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
I was indeed wondering why
== Series Details ==
Series: drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaround
(rev2)
URL : https://patchwork.freedesktop.org/series/100404/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checke
On 18/02/2022 13:47, Ramalingam C wrote:
On 2022-02-17 at 20:57:35 -0800, Jordan Justen wrote:
Robert Beckett writes:
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various r
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL : https://patchwork.freedesktop.org/series/100373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22326_full
Hi Ville,
Thank you for the patch.
On Fri, Feb 18, 2022 at 12:03:47PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> struct drm_display_mode embeds a list head, so overwriting
> the full struct with another one will corrupt the list
> (if the destination mode is on a list). Use drm_mode_
Hi Chris,
On Friday, 18 February 2022 17:03:01 CET Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2022-02-18 15:19:35)
> > @@ -206,15 +229,19 @@ static struct pci_device
> > *__igt_device_get_pci_device(int fd)
> > igt_warn("Couldn't find PCI device %04x:%02x:%02x:%02x\n",
> >
== Series Details ==
Series: Prep work for next GuC release (rev2)
URL : https://patchwork.freedesktop.org/series/99805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22325_full
Summary
---
**
On Fri, 2022-02-18 at 01:54 -0800, Lucas De Marchi wrote:
> PORT_TC1 is still not being initialized - that is the port that uses phy
> E. However the intel_phy_is_snps() reports that phy as being present,
> which causes warnings about unclaimed access to the PHY_MISC register.
> Even with some bas
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video
transfer mode from register values
URL : https://patchwork.freedesktop.org/series/100368/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22324_full
=
Quoting Janusz Krzysztofik (2022-02-18 15:19:35)
> @@ -206,15 +229,19 @@ static struct pci_device
> *__igt_device_get_pci_device(int fd)
> igt_warn("Couldn't find PCI device %04x:%02x:%02x:%02x\n",
> pci_addr.domain, pci_addr.bus,
>
On 2022-02-18 07:12, Simon Ser wrote:
> On Friday, February 18th, 2022 at 12:54, Hans de Goede
> wrote:
>
>> On 2/18/22 12:39, Simon Ser wrote:
>>> On Friday, February 18th, 2022 at 11:38, Hans de Goede
>>> wrote:
>>>
What I'm reading in the above is that it is being considered to allow
>
On Fri, Feb 18, 2022 at 7:13 AM Simon Ser wrote:
>
> On Friday, February 18th, 2022 at 12:54, Hans de Goede
> wrote:
>
> > On 2/18/22 12:39, Simon Ser wrote:
> > > On Friday, February 18th, 2022 at 11:38, Hans de Goede
> > > wrote:
> > >
> > >> What I'm reading in the above is that it is being
The library provides igt_device_get_pci_device() function that allows to
get access to a PCI device from an open DRM device file descriptor. It
can be used on VF devices as long as a DRM driver is bound to them.
However, SR-IOV tests may want to exercise VF PCI devices created by a PF
without bind
== Series Details ==
Series: drm/i915/guc: Fix flag query helper function to not modify state
URL : https://patchwork.freedesktop.org/series/100364/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22323_full
===
On Fri, 2022-02-11 at 00:04 +, Patchwork wrote:
Patch Details
Series: series starting with [1/2] drm/i915/display: Group PSR2 prog sequences
and workarounds
URL:https://patchwork.freedesktop.org/series/99989/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwo
== Series Details ==
Series: doc/rfc for small BAR support
URL : https://patchwork.freedesktop.org/series/100399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11248 -> Patchwork_22331
Summary
---
**SUCCESS**
No r
== Series Details ==
Series: drm/i915/guc/slpc: Use wrapper for reading RP_STATE_CAP (rev2)
URL : https://patchwork.freedesktop.org/series/100217/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22321_full
=
== Series Details ==
Series: drm: Review of mode copies
URL : https://patchwork.freedesktop.org/series/100394/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11248 -> Patchwork_22330
Summary
---
**SUCCESS**
No regr
== Series Details ==
Series: doc/rfc for small BAR support
URL : https://patchwork.freedesktop.org/series/100399/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b54660c8b559 drm/doc: remove rfc section for dg1
-:20: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), doe
== Series Details ==
Series: drm/i915/dg2: 5th Display output (rev3)
URL : https://patchwork.freedesktop.org/series/100151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22320_full
Summary
---
On 2022-02-17 at 20:57:35 -0800, Jordan Justen wrote:
> Robert Beckett writes:
>
> > From: Matthew Auld
> >
> > On discrete platforms like DG2, we need to support a minimum page size
> > of 64K when dealing with device local-memory. This is quite tricky for
> > various reasons, so try to documen
== Series Details ==
Series: drm: Review of mode copies
URL : https://patchwork.freedesktop.org/series/100394/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/amd/amdgpu/../amdgp
Reviewed-by: Jouni Högander
for both patches.
On Thu, 2022-02-10 at 10:52 -0800, José Roberto de Souza wrote:
> Grouping inside of the same if all the programing sequences and
> workarounds of PSR2.
> The order of programing changed in intel_psr_enable_source() but
> it will not affect PSR2 as a
On Wed, 2022-02-16 at 13:48 +, Souza, Jose wrote:
> On Tue, 2022-02-15 at 12:31 +, Hogander, Jouni wrote:
> > On Thu, 2022-02-10 at 10:52 -0800, José Roberto de Souza wrote:
> > > PSR2 workaround required when mode has delayed vblank.
> > >
> > > BSpec: 52890
> > > BSpec: 49421
> > > Cc: J
== Series Details ==
Series: drm/i915: Kill the fake lmem support (rev2)
URL : https://patchwork.freedesktop.org/series/100276/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22319_full
Summary
--
== Series Details ==
Series: drm/i915/dg2: Do not use phy E
URL : https://patchwork.freedesktop.org/series/100390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11248 -> Patchwork_22329
Summary
---
**SUCCESS**
No
On Fri, Feb 18, 2022 at 02:38:37PM +0200, Juha-Pekka Heikkila wrote:
> This patch set look all ok. That failed cursor test in ci run seem to be
> flip flopping on other runs too on same icl box.
Yeah, some of those tests seem a bit flaky on the icls.
Not sure what's causing that.
>
> Reviewed-
This patch set look all ok. That failed cursor test in ci run seem to be
flip flopping on other runs too on same icl box.
Reviewed-by: Juha-Pekka Heikkila
On 2.2.2022 13.16, Ville Syrjala wrote:
From: Ville Syrjälä
We don't want any RMWs in the part of the commit that happens
under vblank e
== Series Details ==
Series: drm/i915/dg2: Do not use phy E
URL : https://patchwork.freedesktop.org/series/100390/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58e2625786ba drm/i915/dg2: Drop 38.4 MHz MPLLB tables
a0ab07a6c339 drm/i915/dg2: Do not use phy E
-:11: WARNING:COMMI
Add display workaround # 1309179469 , which fixes a PHY hang when
switching from TBT mode to DP-alt/legacy mode. The workaround also
requires an IFWI/PHY firmware change, before that this change has no
effect (the DKL_PCS_DW5/SOFTRESET flag is always cleared).
HSDES: 18018237866
HSDES: 16014473319
== Series Details ==
Series: drm/i915/ttm: fixup the mock_bo (rev2)
URL : https://patchwork.freedesktop.org/series/100255/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11248 -> Patchwork_22328
Summary
---
**SUCCESS*
Add display workaround # 1309179469 , which fixes a PHY hang when
switching from TBT mode to DP-alt/legacy mode. The workaround also
requires an IFWI/PHY firmware change, before that this change has no
effect (the DKL_PCS_DW5/SOFTRESET flag is always cleared).
HSDES: 18018237866
HSDES: 16014473319
On 18.02.2022 12:56, Ville Syrjälä wrote:
On Fri, Feb 18, 2022 at 12:22:44PM +0100, Andrzej Hajda wrote:
On 18.02.2022 11:03, Ville Syrjala wrote:
From: Ville Syrjälä
Add a variant of drm_mode_copy() that explicitly clears out
the list head of the destination mode. Helpful to guarantee
we
On Friday, February 18th, 2022 at 12:54, Hans de Goede
wrote:
> On 2/18/22 12:39, Simon Ser wrote:
> > On Friday, February 18th, 2022 at 11:38, Hans de Goede
> > wrote:
> >
> >> What I'm reading in the above is that it is being considered to allow
> >> changing the panel-orientation value afte
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