On Tue, Feb 08, 2022 at 03:37:12PM +0800, Hsin-Yi Wang wrote:
> +int drm_connector_init_panel_orientation_property(
> + struct drm_connector *connector)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_property *prop;
> +
> + prop = drm_property_create_enum(dev, DRM_
== Series Details ==
Series: series starting with [v7,1/3] gpu: drm: separate panel orientation
property creating and value setting
URL : https://patchwork.freedesktop.org/series/99815/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, eac
== Series Details ==
Series: series starting with [v7,1/3] gpu: drm: separate panel orientation
property creating and value setting
URL : https://patchwork.freedesktop.org/series/99815/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
da6aee85bf29 gpu: drm: separate panel orienta
== Series Details ==
Series: drm/i915/guc: Use temporary memory for regset
URL : https://patchwork.freedesktop.org/series/99813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11199 -> Patchwork_22197
Summary
---
**SU
On Mon, Feb 07, 2022 at 08:43:28PM -0800, Bjorn Andersson wrote:
> The Qualcomm DisplayPort driver contains traces of the necessary
> plumbing to hook up USB HPD, in the form of the dp_hpd module and the
> dp_usbpd_cb struct. Use this as basis for implementing the
> oob_hotplug_event() callback, by
krane, kakadu, and kodama boards have a default panel rotation.
Signed-off-by: Hsin-Yi Wang
Reviewed-by: Enric Balletbo i Serra
Tested-by: Enric Balletbo i Serra
---
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/
Init panel orientation property after connector is initialized. Let the
panel driver decides the orientation value later.
Signed-off-by: Hsin-Yi Wang
Acked-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediate
drm_dev_register() sets connector->registration_state to
DRM_CONNECTOR_REGISTERED and dev->registered to true. If
drm_connector_set_panel_orientation() is first called after
drm_dev_register(), it will fail several checks and results in following
warning.
Add a function to create panel orientation
== Series Details ==
Series: drm/i915/guc: Use temporary memory for regset
URL : https://patchwork.freedesktop.org/series/99813/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Currently guc_mmio_reg_add() relies on having enough memory available in
the array to add a new slot. It uses
`GEM_BUG_ON(count >= regset->size);` to protect going above the
threshold.
In order to allow guc_mmio_reg_add() to handle the memory allocation by
itself, it must return an error in case o
The ADS initialitazion was using 2 passes to calculate the regset sent
to GuC to initialize each engine: the first pass to just have the final
object size and the second to set each register in place in the final
gem object.
However in order to maintain an ordered set of registers to pass to guc,
Extract the 2 commits not related to iosys_map from
drm/i915/guc: Refactor ADS access to use iosys_map
(https://patchwork.freedesktop.org/series/99711/). The conversion of the
rest of ADS initializon will take more time to review. So let's take
these by themselves as suggested by Daniele.
Lucas De
== Series Details ==
Series: drm/i915/guc: Fix flag query to not modify state
URL : https://patchwork.freedesktop.org/series/99803/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11199_full -> Patchwork_22195_full
Summary
--
On Tue, Feb 08, 2022 at 05:10:42AM +, Kasireddy, Vivek wrote:
> Hi Tvrtko, Ville,
>
> > On 07/02/2022 13:24, Ville Syrjälä wrote:
> > > On Mon, Feb 07, 2022 at 11:47:16AM +, Tvrtko Ursulin wrote:
> > >>
> > >> On 07/02/2022 10:58, Ville Syrjälä wrote:
> > >>> On Thu, Feb 03, 2022 at 05:22:
Hi Tvrtko, Ville,
> On 07/02/2022 13:24, Ville Syrjälä wrote:
> > On Mon, Feb 07, 2022 at 11:47:16AM +, Tvrtko Ursulin wrote:
> >>
> >> On 07/02/2022 10:58, Ville Syrjälä wrote:
> >>> On Thu, Feb 03, 2022 at 05:22:10PM -0800, Vivek Kasireddy wrote:
> On platforms capable of allowing 8K (7
Hi Michael,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Hi Michael,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next v5.17-rc3 next-20220207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
== Series Details ==
Series: Prep work for next GuC release
URL : https://patchwork.freedesktop.org/series/99805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11199 -> Patchwork_22196
Summary
---
**FAILURE**
Seri
== Series Details ==
Series: Prep work for next GuC release
URL : https://patchwork.freedesktop.org/series/99805/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gt/uc/intel_guc.h:233: warning: Function parameter or
member 'submission_initiali
== Series Details ==
Series: Prep work for next GuC release
URL : https://patchwork.freedesktop.org/series/99805/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc: Fix flag query to not modify state
URL : https://patchwork.freedesktop.org/series/99803/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11199 -> Patchwork_22195
Summary
---
*
== Series Details ==
Series: drm/i915/psr: Disable PSR2 selective fetch for all TGL steps
URL : https://patchwork.freedesktop.org/series/99796/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11198_full -> Patchwork_22194_full
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
1
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
regis
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
dif
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available.
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c |
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++-
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +---
From: John Harrison
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really h
== Series Details ==
Series: drm/i915/guc: Fix flag query to not modify state
URL : https://patchwork.freedesktop.org/series/99803/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
98f0397a8054 drm/i915/guc: Fix flag query to not modify state
-:30: CHECK:FROM_SIGN_OFF_MISMATCH: Fr
From: John Harrison
A flag query helper was actually writing to the flags word rather than
just reading. Fix that. Also update the function's comment as it was
out of date.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/
== Series Details ==
Series: drm/i915/dg2: Define GuC firmware version for DG2
URL : https://patchwork.freedesktop.org/series/99793/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11198_full -> Patchwork_22193_full
Summary
-
Hi Jordan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc3 next-20220207]
[cannot apply to airlied/drm-next]
[If your
On Mon, Feb 07, 2022 at 09:31:19AM +0200, Ville Syrjälä wrote:
> On Fri, Feb 04, 2022 at 03:58:29PM -0800, Navare, Manasi wrote:
> > On Thu, Feb 03, 2022 at 08:38:23PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Get rid of the inflexible bigjoiner_linked_crtc pointer thing
>
== Series Details ==
Series: drm/i915/psr: Disable PSR2 selective fetch for all TGL steps
URL : https://patchwork.freedesktop.org/series/99796/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11198 -> Patchwork_22194
Summary
Hi Jordan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc3 next-20220207]
[cannot apply to airlied/drm-next]
[If your
== Series Details ==
Series: drm/i915/dg2: Define GuC firmware version for DG2
URL : https://patchwork.freedesktop.org/series/99793/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11198 -> Patchwork_22193
Summary
---
Hi Jordan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc3 next-20220207]
[cannot apply to airlied/drm-next
Hi Jordan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc3 next-20220207]
[If your patch is applied to the
On Wed, Jan 26, 2022 at 02:48:22AM -0800, Alan Previn wrote:
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multipl
As we've unfortunately started to come to expect from PSR on Intel
platforms, PSR2 selective fetch is not at all ready to be enabled on
Tigerlake as it results in severe flickering issues - at least on this
ThinkPad X1 Carbon 9th generation. The easiest way I've found of
reproducing these issues is
Hmm, this is actually v1 not v3! Had something stale when posting.
John.
On 2/7/2022 12:36, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev5)
URL : https://patchwork.freedesktop.org/series/99450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11197 -> Patchwork_22192
Summary
---
**FAILU
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/g
On Fri, Feb 04, 2022 at 08:15:12PM +0100, Thomas Zimmermann wrote:
Hi
Am 04.02.22 um 18:44 schrieb Lucas De Marchi:
Add a variant of shmem_read() that takes a iosys_map pointer rather
than a plain pointer as argument. It's mostly a copy __shmem_rw() but
adapting the api and removing the write s
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev5)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev5)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
01334f06e3af drm/i915/gt: Re-work intel_write_status_page
5f2ab439de24 drm/i915/gt: Drop invalidate_csb_en
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
arm64 platforms. Using flush_tlb_kernel_range will:
1. Make sure prior page-table updates have been completed
2. Invalidate the TLB
3. Check if the TLB invalidation has been completed
Signed-off-by: Michael Cheng
---
drivers/gpu
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range.
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-of
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/driv
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11197_full -> Patchwork_22190_full
Summary
--
The following changes since commit eb8ea1b46893c42edbd516f971a93b4d097730ab:
Merge branch 'v1.1.7' of https://github.com/irui-wang/linux_fw_vpu_v1.1.7
into main (2022-01-24 06:49:52 -0500)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_guc_v69.0.3
== Series Details ==
Series: GuC HWCONFIG with documentation
URL : https://patchwork.freedesktop.org/series/99787/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/
Signed-off-by: Jordan Justen
---
.../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index ce6088f112d4..695ef7a8f519 100644
--- a/
Also, document DRM_I915_QUERY_HWCONFIG_BLOB with this struct.
Cc: Daniel Vetter
Signed-off-by: Jordan Justen
---
include/uapi/drm/i915_drm.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 069d2fadfbd9
From: Rodrigo Vivi
The DRM_I915_QUERY_HWCONFIG_BLOB query item returns a blob of data
which it receives from the GuC software. This blob provides some
useful data about the hardware for drivers.
Although the blob is not fully documented at this time, the basic
format is an array of u32 values. T
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
This is John/Rodrigo's 2 patches with some minor changes, and I added
2 patches.
"drm/i915/uapi: Add query for hwconfig blob" was changed:
* Rename DRM_I915_QUERY_HWCONFIG_TABLE to DRM_I915_QUERY_HWCONFIG_BLOB
as requested by Joonas.
* Reword commit message
* I added Acked-by to this patc
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Wed, Jan 26, 2022 at 02:48:16AM -0800, Alan Previn wrote:
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_g
Ah, sorry thanks for pointing that out. We did discuss previously. I
will go ahead and change it.
On 2022-02-07 3:57 a.m., Tvrtko Ursulin wrote:
On 04/02/2022 16:37, Michael Cheng wrote:
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function ca
== Series Details ==
Series: series starting with [1/2] drm/i195: Fix dbuf slice config lookup
URL : https://patchwork.freedesktop.org/series/99764/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11196_full -> Patchwork_22188_full
===
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11197 -> Patchwork_22190
Summary
---
**SUC
== Series Details ==
Series: Add fallback inside memcpy_from_wc functions
URL : https://patchwork.freedesktop.org/series/99774/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915
On 1/28/2022 10:52 AM, Ramalingam C wrote:
From: Stuart Summers
The driver is set currently to fail modprobe when GuC is disabled
(enable_guc=0) after GuC has been loaded on a previous modprobe.
For GuC deprivilege, the BIOS is setting the locked bit, so the
driver always considers the GuC t
On Mon, Feb 07, 2022 at 03:26:59PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently I totally fumbled the loop condition when I
> removed the ARRAY_SIZE() stuff from the dbuf slice config
> lookup. Comparing the loop index with the active_pipes bitmask
> is utter nonsense, what we
memcpy_from_wc functions can fail if SSE4.1 is not supported or the
supplied addresses are not 16-byte aligned. It was then upto to the
caller to use memcpy as fallback.
Now fallback to memcpy is implemented inside memcpy_from_wc functions
relieving the user from checking the return value of i915_m
Fallback function implemented inside memcpy_from_wc functions when
copying using accelerated read is not possible.
v2: Fixed Sparse warnings
Balasubramani Vivekanandan (1):
drm/i915: Add fallback inside memcpy_from_wc functions
drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 +-
drivers/gpu/d
== Series Details ==
Series: series starting with [1/2] drm/i195: Fix dbuf slice config lookup
URL : https://patchwork.freedesktop.org/series/99764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11196 -> Patchwork_22188
Sum
== Series Details ==
Series: My patch queue
URL : https://patchwork.freedesktop.org/series/99770/
State : failure
== Summary ==
Applying: KVM: x86: SVM: don't passthrough SMAP/SMEP/PKE bits in !NPT &&
!gCR0.PG case
error: sha1 information is lacking or useless (arch/x86/kvm/svm/svm.c).
error:
On 20/01/2022 22:16, Casey Bowman wrote:
In this RFC I would like to ask the community their thoughts
on how we can best handle splitting architecture-specific
calls.
I would like to address the following:
1. How do we want to split architecture calls? Different object files
per platform? Sep
As it turned out this request isn't really needed,
and it complicates the nested migration.
In theory this patch can break userspace if
userspace relies on updating KVM's memslots
after setting nested state but there is little reason
for it to rely on this.
However this is undocumented and there
All exceptions are supported. Some bugs might remain in regard to KVM own
interception of #PF but since this is strictly
debug feature this should be OK.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/vmx/nested.c | 8 +++
arch/x86/kvm/vmx/vmcs.h | 6 +
arch/x86/kvm/vmx/vmx.c| 47
Currently #TS interception is only done once.
Also exception interception is not enabled for SEV guests.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/include/uapi/asm/kvm.h | 1 +
arch/x86/kvm/svm/svm.c | 92 -
arch/
This parameter will be used by VMX and SVM code to force
interception of a set of exceptions, given by a bitmask
for guest debug and/or kvm debug.
This is based on an idea first shown here:
https://patchwork.kernel.org/project/kvm/patch/20160301192822.gd22...@pd.tnic/
CC: Borislav Petkov
Signed-
In case L1 enables vGIF for L2, the L2 cannot affect L1's GIF, regardless
of STGI/CLGI intercepts, and since VM entry enables GIF, this means
that L1's GIF is always 1 while L2 is running.
Thus in this case leave L1's vGIF in vmcb01, while letting L2
control the vGIF thus implementing nested vGIF.
On 2022-02-07 at 20:52:33 +0530, Hellstrom, Thomas wrote:
> On Mon, 2022-02-07 at 20:44 +0530, Ramalingam C wrote:
> > On 2022-02-07 at 20:25:42 +0530, Hellstrom, Thomas wrote:
> > > Hi, Ram,
> > >
> > > A couple of quick questions before starting a more detailed review:
> > >
> > > 1) Does this al
Allow L1 to use these settings if L0 disables PAUSE interception
(AKA cpu_pm=on)
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 6 ++
arch/x86/kvm/svm/svm.c| 17 +
arch/x86/kvm/svm/svm.h| 2 ++
3 files changed, 25 insertions(+)
diff --git a/arch/x86/
This was tested by booting L1,L2,L3 (all Linux) and checking
that no VMLOAD/VMSAVE vmexits happened.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 35 +--
arch/x86/kvm/svm/svm.c| 7 +++
arch/x86/kvm/svm/svm.h| 8 +++-
3 files chan
This was tested with kvm-unit-test that was developed
for this purpose.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 21 +++--
arch/x86/kvm/svm/svm.c| 8
arch/x86/kvm/svm/svm.h| 1 +
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git
When L2 is running without LBR virtualization, we should ensure
that L1's LBR msrs continue to update as usual.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/nested.c | 11 +
arch/x86/kvm/svm/svm.c| 98 +++
arch/x86/kvm/svm/svm.h| 2 +
3 file
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
drivers/gpu/dr
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
a
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
Add an (mostly debug) option to force KVM's shadow mmu
to never have unsync pages.
This is useful in some cases to debug it.
It is also useful for some legacy guest OSes which don't
flush TLBs correctly, and thus don't work on modern
CPUs which have speculative MMUs.
Using this option together w
It makes more sense to print new SPTE value than the
old value.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/mmu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 296f8723f9ae9..43c7abdd6b70f 100644
--- a/arch/x86/kv
Apparently on some systems AVIC is disabled in CPUID but still usable.
Allow the user to override the CPUID if the user is willing to
take the risk.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/
Now that KVM doesn't allow to change APIC ID in case AVIC is
enabled, remove buggy AVIC code that tried to do so.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/k
KVM allowed to set non boot apic id via setting apic state
if using older non x2apic 32 bit apic id userspace api.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/lapic.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lap
No normal guest has any reason to change physical APIC IDs, and
allowing this introduces bugs into APIC acceleration code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/lapic.c | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/lapic.c
Inhibit the AVIC of the vCPU that is running nested for the duration of the
nested run, so that all interrupts arriving from both its vCPU siblings
and from KVM are delivered using normal IPIs and cause that vCPU to vmexit.
Note that unlike normal AVIC inhibition, there is no need to
update the AV
Out of precation use vmcb01 when enabling host AVIC.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 4c2d622b3b9f0..c6072245f7fbb
If svm_deliver_avic_intr is called just after the target vcpu's AVIC got
inhibited, it might read a stale value of vcpu->arch.apicv_active
which can lead to the target vCPU not noticing the interrupt.
To fix this use load-acquire/store-release so that, if the target vCPU
is IN_GUEST_MODE, we're gu
asm/svm.h is the correct place for all values that are defined in
the SVM spec, and that includes AVIC.
Also add some values from the spec that were not defined before
and will be soon useful.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/svm.h
kvm_apic_update_apicv is called when AVIC is still active, thus IRR bits
can be set by the CPU after it is called, and don't cause the irr_pending
to be set to true.
Also logic in avic_kick_target_vcpu doesn't expect a race with this
function so to make it simple, just keep irr_pending set to true
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