From: Tejas Upadhyay
>From VBT, ddc pin info suggests the following mapping:
VBTDRIVER
DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9
DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa
DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb
On Thu, Dec 02, 2021 at 12:34:00PM -0800, Jakub Kicinski wrote:
> cgroup.h (therefore swap.h, therefore half of the universe)
> includes bpf.h which in turn includes module.h and slab.h.
> Since we're about to get rid of that dependency we need
> to clean things up.
>
> v2: drop the cpu.h include
Thanks, always good to see someone else helping to unwind our include
dependency mess..
Reviewed-by: Christoph Hellwig
Though, RPL-S is defined as subplatform of ADL-S, unlike
ADL-S, it has GuC submission by default.
v2: Remove extra parenthesis (Jani)
v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
Cc: dri-de...@lists.freedesktop.org
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Signed-off-by: Anusha Srivats
Add the PCH ID for RPL-S.
v2: Self contained commit message (Jani)
Cc: dri-de...@lists.freedesktop.org
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_pch.c | 1 +
drivers/gpu/drm/i915/in
Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).
Introduce RPL-S as a subplatform
of ADL-S. This patch adds PCI ids for RPL-S.
v2: Update PCI IDs.
- Add more description to commit message (Jani)
v3: s/IS_RAPTORLAKE/IS_A
Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).
The series introduces it as a subplatform
of ADL-S. The one difference is the GuC
submission which is default on RPL-S but
was not the case with ADL-S.
All patches are rev
add null ptr checks to prevent crash/exceptions.
Signed-off-by: Pallavi Mishra
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/
On Wed, Nov 17, 2021 at 04:50:33AM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Additional DG2 workarounds (rev3)
> URL : https://patchwork.freedesktop.org/series/96824/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10888_full -> Patchwork_21604_f
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev12)
URL : https://patchwork.freedesktop.org/series/97090/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10957 -> Patchwork_21736
Summary
--
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev12)
URL : https://patchwork.freedesktop.org/series/97090/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
11b7af9a808e drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE:
== Series Details ==
Series: Assorted fixes/tweaks to GuC support
URL : https://patchwork.freedesktop.org/series/97514/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10957_full -> Patchwork_21735_full
Summary
---
**F
== Series Details ==
Series: Assorted fixes/tweaks to GuC support
URL : https://patchwork.freedesktop.org/series/97514/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10957 -> Patchwork_21735
Summary
---
**SUCCESS**
The following changes since commit b0e898fbaf377c99a36aac6fdeb7250003648ca4:
linux-firmware: Update firmware file for Intel Bluetooth 9462 (2021-11-23
12:31:45 -0500)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware guc_v69
for you to fetch changes up
On Thu, Dec 02, 2021 at 04:06:23PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
== Series Details ==
Series: Assorted fixes/tweaks to GuC support
URL : https://patchwork.freedesktop.org/series/97514/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Assorted fixes/tweaks to GuC support
URL : https://patchwork.freedesktop.org/series/97514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
394709d4751f drm/i915/uc: Allow platforms to have GuC but not HuC
-:36: ERROR:COMPLEX_MACRO: Macros with complex
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_f
From: Vinay Belgaumkar
By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.
Signed-off-by: Vinay Belgaumkar
---
dr
From: John Harrison
Fix a potential null pointer dereference, improve debug crash reports,
improve code separation, improve GuC/HuC load performance.
Signed-off-by: John Harrison
John Harrison (3):
drm/i915/uc: Allow platforms to have GuC but not HuC
drm/i915/guc: Increase GuC log size f
From: John Harrison
Lots of testing is done with the DEBUG_GEM config option enabled but
not the DEBUG_GUC option. That means we only get teeny-tiny GuC logs
which are not hugely useful. Enabling full DEBUG_GUC also spews lots
of other detailed output that is not generally desired. However,
bigge
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 4 ++--
1 file changed
== Series Details ==
Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL : https://patchwork.freedesktop.org/series/97499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10956_full -> Patchwork_21731_full
===
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Matt Atwood
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insert
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context. We
Correct,
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2
steppings.
Bspec: 52698
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
1 file changed, 11 insertion
Looks correct.
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver real
== Series Details ==
Series: drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c
URL : https://patchwork.freedesktop.org/series/97498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10956_full -> Patchwork_21730_full
===
Hey Lakshmi,
I believe the following errors are unrelated to my change, could you please
help update the CI?
Thanks,
Michael Cheng
From: Patchwork
Sent: 02 December 2021 12:28
To: Cheng, Michael
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failur
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev11)
URL : https://patchwork.freedesktop.org/series/97090/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21734
Summary
--
On Wed, 2021-12-01 at 16:30 -0800, Lucas De Marchi wrote:
> PAT can be disabled on boot with "nopat" in the command line. Replace
> one x86-ism with another, which is slightly more correct to prepare for
> supporting other architectures.
Reviewed-by: José Roberto de Souza
>
> Cc: Matt Roper
>
On Thu, Dec 02, 2021 at 04:44:56PM +0200, Jani Nikula wrote:
> The mode set sequence for 128b/132b requires setting the div32 version
> of MPLLB clock.
>
> Bspec: 53880, 54128
Weird place for that information when all the other bits are listed
in the clock programming section :/
> Signed-off-by:
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev11)
URL : https://patchwork.freedesktop.org/series/97090/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
13238fd0ba2e drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE:
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-12-02:
- Fixing a regression where the backlight brightness control stopped working.
- Fix the Intel HDR backlight support detection.
- Reverting a w/a to fix a gpu Hang in TGL. The w/a itself was also
for a hang, but in a much rarer scenario.
== Series Details ==
Series: drm/i915: Fix possible null ptr dereferences
URL : https://patchwork.freedesktop.org/series/97496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10955_full -> Patchwork_21729_full
Summary
--
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev10)
URL : https://patchwork.freedesktop.org/series/97090/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21732
Summary
--
== Series Details ==
Series: series starting with [1/8] drm/i915/migrate: don't check the scratch
page
URL : https://patchwork.freedesktop.org/series/97504/
State : failure
== Summary ==
Applying: drm/i915/migrate: don't check the scratch page
Applying: drm/i915/gtt: add xehpsdv_ppgtt_insert_
== Series Details ==
Series: drm/i915: Re-use i915 macros for checking PTEs (rev10)
URL : https://patchwork.freedesktop.org/series/97090/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ccb569c471b6 drm/i915: Re-use i915 macros for checking PTEs
-:6: WARNING:COMMIT_LOG_LONG_LINE:
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a804c57b61df..0da27ec808dc 100644
--- a/dri
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 186 +++-
Ensure we account for any object rounding due to min_page_size
restrictions.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
b/driver
No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1 insertio
Ensure we add the engine base only after we calculate the qword offset
into the PTE window.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/
With object clearing/copying we need to be able to modify the PTEs on
the fly via some batch buffer, which means we need to be able to map the
paging structures(or at the very least the PT, but being able to also
map the PD might also be useful at some point) into the GTT. And since
the paging stru
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_mig
== Series Details ==
Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL : https://patchwork.freedesktop.org/series/97499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21731
Summary
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 6:37 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas wr
== Series Details ==
Series: drm/i915/snps: use div32 version of MPLLB word clock for UHBR
URL : https://patchwork.freedesktop.org/series/97499/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL : https://patchwork.freedesktop.org/series/97053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10954_full -> Patchwork_21728_full
==
== Series Details ==
Series: drm: get rid of DRM_DEBUG_* log calls in drm core, files drm_a*.c
URL : https://patchwork.freedesktop.org/series/97498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10956 -> Patchwork_21730
Sum
== Series Details ==
Series: drm/i915: Fix possible null ptr dereferences
URL : https://patchwork.freedesktop.org/series/97496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10955 -> Patchwork_21729
Summary
---
**SUC
The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.
Bspec: 53880, 54128
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/driv
Andi Shyti writes:
> Change functions that always return '0' to be void type.
>
> Signed-off-by: Andi Shyti
> Cc: Maciej Patelczyk
> ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c| 7 ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.h| 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_
On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Add the PCH ID for RPL-S.
>
> v2: Self contained commit message (Jani)
Reviewed-by: José Roberto de Souza
>
> Cc: Jani Nikula
> Cc: Swathi Dhanavanthri
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_pch.c | 1
On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Raptor Lake S(RPL-S) is a version 12
> Display, Media and Render. For all i915
> purposes it is the same as Alder Lake S (ADL-S).
>
> Introduce RPL-S as a subplatform
> of ADL-S. This patch adds PCI ids for RPL-S.
>
> v2: Update PCI IDs.
On Wed, 2021-12-01 at 02:33 -0800, Anusha Srivatsa wrote:
> Though, RPL-S is defined as subplatform of ADL-S, unlike
> ADL-S, it has GuC submission by default.
>
> v2: Remove extra parenthesis (Jani)
> v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
>
Reviewed-by: José Roberto de Souza
> Cc: Jani Niku
From: Claudio Suarez
igt_check_plane_state test crashes in drm_atomic_helper_check_plane_state
when trying to de-reference drm_plane_state->plane->dev
due to the lack of a struct drm_plane in the mock struct drm_plane_state.
Since drm_plane_state always should contain a plane, the mock also
needs
Am 01.12.21 um 17:39 schrieb Arunpravin:
Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename "i915" string with "drm" string wherever applicable
- Rename "I915" string with "DRM" string wherever applicable
- Fix heade
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL : https://patchwork.freedesktop.org/series/97053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10954 -> Patchwork_21728
Summar
On Thu, Dec 02, 2021 at 04:38:36PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with NV
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev9)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30dac13d1d1c drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:41: CHECK:PARENTHE
On Wed, Dec 01, 2021 at 05:26:50PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Polish the skl+ universal plane register defines by
> > using REG_BIT() & co.
> >
> > The defines are also currently spread around in some
> > se
On Wed, Dec 01, 2021 at 05:18:54PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Replace the "sizes are 0 based" stuff with just straight
> > up -1 where needed. Less confusing all around.
> >
> > Signed-off-by: Ville Syrjälä
On Wed, Dec 01, 2021 at 05:14:39PM +, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Rename the YUV byte order bits to be a bit more consistent.
>
> Why rename bits not used? Would be better already nuke it.
> Anyways up to you.
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21727_full
Summary
---
add null ptr checks to prevent crash/exceptions.
Signed-off-by: Pallavi Mishra
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 4:43 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 11:10:37AM +
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
On Thu, Dec 02, 2021 at 11:10:37AM +, Srinivas, Vidya wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Thursday, December 2, 2021 4:26 PM
> > To: Srinivas, Vidya
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> >
> > Subject: Re: [PATCH] drm/i915: Ad
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 2, 2021 4:26 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Thu, Dec 02, 2021 at 03:25:34AM +
On Thu, Dec 02, 2021 at 03:25:34AM +, Srinivas, Vidya wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Wednesday, December 1, 2021 8:33 PM
> > To: Srinivas, Vidya
> > Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> >
> > Subject: Re: [PATCH] drm/i915: A
== Series Details ==
Series: drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer()
(rev4)
URL : https://patchwork.freedesktop.org/series/96969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21725_full
=
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21727
Summary
---
**
== Series Details ==
Series: Replace VT-d workaround with guard pages (rev2)
URL : https://patchwork.freedesktop.org/series/97492/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: static analysis failure
URL : https://patchwork.freedesktop.org/series/97486/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953_full -> Patchwork_21724_full
Summary
---
**SUCCESS**
N
== Series Details ==
Series: Replace VT-d workaround with guard pages
URL : https://patchwork.freedesktop.org/series/97492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21726
Summary
---
**SUCCESS
From: Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Curr
From: Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surr
From: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_n
Replace filling the GGTT entirely with scratch pages to avoid invalid
accesses from VT-d overfetch of scanout by only surrounding scanout vma
with guard pages. This eliminates the 100+ms delay in resume where we
have to repopulate the GGTT with scratch.
This should also help in avoiding slow suspe
== Series Details ==
Series: Replace VT-d workaround with guard pages
URL : https://patchwork.freedesktop.org/series/97492/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Replace VT-d workaround with guard pages
URL : https://patchwork.freedesktop.org/series/97492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9f65b4ead78d drm/i915: Wrap all access to i915_vma.node.start|size
aab382a940c6 drm/i915: Introduce guard pa
On 12/2/21 05:38, Pallavi Mishra wrote:
fix for null ptr dereferences.
Please describe the change as per the patch submission guidelines:
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
In particular, describe the *real* problems and the fixes, a
Hi,
On 12/2/21 05:38, Pallavi Mishra wrote:
fix for null ptr dereferences
Pallavi Mishra (1):
static analysis failure
No need for cover letter for a single patch.
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
2 files cha
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2021-12-02:
Switch back to drm_poll for virtio, multiple fixes (memory leak,
improper error check, some functional fixes too) for vc4, memory leak
fix in dma-buf,
The following changes since commit e048834c209a02e3776bcc47
From: Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
Curr
From: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the drm_mm_n
From: Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and aft. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that surr
Replace filling the GGTT entirely with scratch pages to avoid invalid
accesses from VT-d overfetch of scanout by only surrounding scanout vma
with guard pages. This eliminates the 100+ms delay in resume where we
have to repopulate the GGTT with scratch.
This should also help in avoiding slow suspe
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