== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev8)
URL : https://patchwork.freedesktop.org/series/97053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10948_full -> Patchwork_21710_full
==
== Series Details ==
Series: Introduce Raptor Lake S (rev3)
URL : https://patchwork.freedesktop.org/series/96869/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/g
Though, RPL-S is defined as subplatform of ADL-S, unlike
ADL-S, it has GuC submission by default.
v2: Remove extra parenthesis (Jani)
v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani)
Cc: Jani Nikula
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
Add the PCH ID for RPL-S.
v2: Self contained commit message (Jani)
Cc: Jani Nikula
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_pch.c | 1 +
drivers/gpu/drm/i915/intel_pch.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/int
Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).
Introduce RPL-S as a subplatform
of ADL-S. This patch adds PCI ids for RPL-S.
v2: Update PCI IDs.
- Add more description to commit message (Jani)
v3: s/IS_RAPTORLAKE/IS_A
Raptor Lake S(RPL-S) is a version 12
Display, Media and Render. For all i915
purposes it is the same as Alder Lake S (ADL-S).
The series introduces it as a subplatform
of ADL-S. The one difference is the GuC
submission which is default on RPL-S but
was not the case with ADL-S.
Anusha Srivatsa (3)
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev8)
URL : https://patchwork.freedesktop.org/series/97053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10948 -> Patchwork_21710
Summar
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev7)
URL : https://patchwork.freedesktop.org/series/97053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10948 -> Patchwork_21709
Summar
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev8)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dd6fd0244481 drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:42: CHECK:PARENTHE
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev7)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
24b77f8800af drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:38: CHECK:PARENTHE
On 11/23/2021 06:45, ravitejax.goud.ta...@intel.com wrote:
From: raviteja goud talla
Bspec page says "Reset: BUS", Accordingly moving w/a's:
Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init()
Which will resolve guc enabling error
Cc: John Harrison
Signed-off-by: raviteja
On Fri, 2021-11-19 at 12:59 +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Adding a cross-check with ABI config name space and not just relying
> on
> sysfs names.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Dmitry Rogozhkin
> ---
> tools/intel_gpu_top.c | 6 ++
> 1 file changed, 6 i
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 11:40 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Tue, Nov 30, 20
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
On Thu, Nov 18, 2021 at 12:54:32PM -0800, Michael Cheng wrote:
Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check
bits 0 and 1 for PTEs. These macros are defined per architectures, and some
architectures do not have these defined (like arm64). This patch replaces these
== Series Details ==
Series: drm/i915/dp: Perform 30ms delay after source OUI write (rev3)
URL : https://patchwork.freedesktop.org/series/96871/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945_full -> Patchwork_21708_full
===
On Wed, Dec 01, 2021 at 12:41:08AM +0200, Andi Shyti wrote:
Hi Lucas,
fist of all thanks for taking a look at this, I was eagerly
waiting for reviewers.
On Tue, Nov 30, 2021 at 01:07:30PM -0800, Lucas De Marchi wrote:
On Sun, Nov 28, 2021 at 01:09:26PM +0200, Andi Shyti wrote:
> Starting from
Hi,
ping! (Lucas?)
> We now support a per-gt uncore, yet we're not able to infer which GT
> we're operating upon. Let's store a backpointer for now.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Matt Roper
> Reviewed-by: Andi Shyti
> Signed-off-by: Andi Shyti
can we merge this, mean
== Series Details ==
Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer
(rev5)
URL : https://patchwork.freedesktop.org/series/94924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945_full -> Patchwork_21706_full
=
On Fri, Nov 19, 2021 at 02:13:53PM +, Souza, Jose wrote:
> On Fri, 2021-11-19 at 06:09 -0800, José Roberto de Souza wrote:
> > This workarounds are causing hangs, because I missed the fact that it
> > needs to be enabled for all cases and disabled when doing a resolve
> > pass.
> >
> > So KMD
== Series Details ==
Series: lib/stackdepot: always do filter_irq_stacks() in stack_depot_save()
URL : https://patchwork.freedesktop.org/series/97422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945_full -> Patchwork_21703_full
=
Hi Lucas,
fist of all thanks for taking a look at this, I was eagerly
waiting for reviewers.
On Tue, Nov 30, 2021 at 01:07:30PM -0800, Lucas De Marchi wrote:
> On Sun, Nov 28, 2021 at 01:09:26PM +0200, Andi Shyti wrote:
> > Starting from a patch from Matt to_root_gt() returns the
> > reference to
== Series Details ==
Series: drm/i915/dp: Perform 30ms delay after source OUI write (rev3)
URL : https://patchwork.freedesktop.org/series/96871/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21708
Summary
== Series Details ==
Series: drm/i915/dp: Perform 30ms delay after source OUI write (rev3)
URL : https://patchwork.freedesktop.org/series/96871/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
While working on supporting the Intel HDR backlight interface, I noticed
that there's a couple of laptops that will very rarely manage to boot up
without detecting Intel HDR backlight support - even though it's supported
on the system. One example of such a laptop is the Lenovo P17 1st
generation.
On Sun, Nov 28, 2021 at 01:09:26PM +0200, Andi Shyti wrote:
Starting from a patch from Matt to_root_gt() returns the
reference to the root tile in order to abstract the root tile
from th callers.
Being the root tile identified as tile '0', embed the id in the
name so that i915->gt becomes i915->
Hi Maxime,
On Tue, 30 Nov 2021 09:58:31 +0100 Maxime Ripard wrote:
>
> Unfortunately the merge resolution isn't entirely correct :/
>
> There's multiple conflicts between those two branches on that file, but
> things went wrong between 16e101051f32 and 0c980a006d3f
>
> The first one changes the
On Tue, 2021-11-30 at 12:36 +0200, Jani Nikula wrote:
> On Mon, 29 Nov 2021, Lyude Paul wrote:
> > While working on supporting the Intel HDR backlight interface, I noticed
> > that there's a couple of laptops that will very rarely manage to boot up
> > without detecting Intel HDR backlight support
== Series Details ==
Series: drm/i915/gem: Fix a NULL pointer dereference in igt_request_rewind()
URL : https://patchwork.freedesktop.org/series/97421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10944_full -> Patchwork_21702_full
On Fri, Nov 26, 2021 at 02:14:24PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
With both integrated and discrete Intel GPUs in a system, the current
global check of intel_iommu_gfx_mapped, as done from intel_vtd_active()
may not be completely accurate.
In this patch we add i915 parameter
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev5)
URL : https://patchwork.freedesktop.org/series/97053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21707
Summar
On 11/30/21 19:12, Thomas Hellström wrote:
On Tue, 2021-11-30 at 16:02 +0100, Christian König wrote:
Am 30.11.21 um 15:35 schrieb Thomas Hellström:
On Tue, 2021-11-30 at 14:26 +0100, Christian König wrote:
Am 30.11.21 um 13:56 schrieb Thomas Hellström:
On 11/30/21 13:42, Christian König wro
On Mon, Nov 22, 2021 at 06:01:42PM +0530, Mullati Siva wrote:
From: Siva Mullati
Only hw that supports mappable aperture would hit this path
vm_fault_gtt/vm_fault_tmm, So we never hit this function
remap_io_mapping() in discrete, So skip this code for non-x86
architectures.
Signed-off-by: Siva
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev5)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
09f89f851e74 drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:34: CHECK:PARENTHE
== Series Details ==
Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer
(rev5)
URL : https://patchwork.freedesktop.org/series/94924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21706
===
On 30/11/2021 11:17, Maarten Lankhorst wrote:
On 30-11-2021 09:54, Tvrtko Ursulin wrote:
Hi,
On 29/11/2021 13:47, Maarten Lankhorst wrote:
New version of the series, with feedback from previous series added.
If there was a cover letter sent for this work in the past could you please
keep
== Series Details ==
Series: drm/i915/selftest: Disable IRQ for timestamp calculation (rev3)
URL : https://patchwork.freedesktop.org/series/96853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10943_full -> Patchwork_21701_full
=
== Series Details ==
Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer
(rev5)
URL : https://patchwork.freedesktop.org/series/94924/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked se
On Tue, 2021-11-30 at 16:02 +0100, Christian König wrote:
> Am 30.11.21 um 15:35 schrieb Thomas Hellström:
> > On Tue, 2021-11-30 at 14:26 +0100, Christian König wrote:
> > > Am 30.11.21 um 13:56 schrieb Thomas Hellström:
> > > > On 11/30/21 13:42, Christian König wrote:
> > > > > Am 30.11.21 um 13
== Series Details ==
Series: drm/i915: Drop stealing of bits from i915_sw_fence function pointer
(rev5)
URL : https://patchwork.freedesktop.org/series/94924/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6f01e9cabea1 drm/i915: Drop stealing of bits from i915_sw_fence function
On Tue, Nov 30, 2021 at 10:42:20PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with NV
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev4)
URL : https://patchwork.freedesktop.org/series/97053/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21705
Summar
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 10:00 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Tue, Nov 30, 20
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev4)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2930434c940d drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:30: CHECK:PARENTHE
== Series Details ==
Series: Attempt to avoid dma-fence-[chain|array] lockdep splats
URL : https://patchwork.freedesktop.org/series/97410/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10943_full -> Patchwork_21700_full
Sum
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed revi
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev2)
URL : https://patchwork.freedesktop.org/series/97053/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21704
Summar
== Series Details ==
Series: lib/stackdepot: always do filter_irq_stacks() in stack_depot_save()
URL : https://patchwork.freedesktop.org/series/97422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10945 -> Patchwork_21703
S
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev2)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Reject 5k on HDR planes for planar fb formats (rev2)
URL : https://patchwork.freedesktop.org/series/97053/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84c898254500 drm/i915: Add PLANE_CUS_CTL restriction in max_width
-:16: ERROR:GERRIT_C
I still think this goes into the wrong direction.
Something closer to your first version that also saves away the
gvt->mmio.mmio_attribute flags in the core i915 module, and which
splits the MMIO table into one that contains just the offset, size
and flags (core i915) and one that has the read-onl
Filed this issue and re-reported
https://gitlab.freedesktop.org/drm/intel/-/issues/4664
igt@kms_flip@busy-flip@b-edp1 - incomplete - No warnings/errors
Thanks,
Lakshmi.
From: Thomas Hellström
Sent: Monday, November 29, 2021 9:46 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Su
On 2021-11-19 17:04:00 [+0100], Daniel Vetter wrote:
> Yeah if we can simplify this with reverts then I'm all for this.
>
> Acked-by: Daniel Vetter
>
> I've asked drm/i915 maintainers to check&merge.
Thanks. Should I repost my queue (excluding this one) or should wait
until this one has been ta
On Tue, Nov 30, 2021 at 09:35:34PM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with NV
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, November 30, 2021 3:01 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Reject 5k on HDR planes for planar
> fb formats
>
> On Thu, Nov 18, 202
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
Signed-off-by: Vid
== Series Details ==
Series: drm/i915: Update error capture code to avoid using the current vma state
URL : https://patchwork.freedesktop.org/series/97385/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10939_full -> Patchwork_21696_full
== Series Details ==
Series: drm/i915/adl-n: Enable ADL-N platform
URL : https://patchwork.freedesktop.org/series/97406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10942_full -> Patchwork_21699_full
Summary
---
**
== Series Details ==
Series: drm/i915/gem: Fix a NULL pointer dereference in igt_request_rewind()
URL : https://patchwork.freedesktop.org/series/97421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10944 -> Patchwork_21702
Hi Dave & Daniel -
drm-intel-next-2021-11-30:
drm/i915 feature pull for v5.17:
Features and functionality:
- Implement per-lane DP drive settings for ICL+ (Ville)
- Enable runtime pm autosuspend by default (Tilak Tangudu)
- ADL-P DSI support (Vandita)
- Add support for pipe C and D DMC firmware
On 30/11/2021 14:15, Zhou Qingyang wrote:
In igt_request_rewind(), mock_context(i915, "A") is assigned to ctx[0]
and used in i915_gem_context_get_engine(). There is a dereference
of ctx[0] in i915_gem_context_get_engine(), which could lead to a NULL
pointer dereference on failure of mock_contex
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf. (rev2)
URL : https://patchwork.freedesktop.org/series/97371/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10942_full -> Patchwork_21698_full
Summa
On Tue, 2021-11-30 at 14:26 +0100, Christian König wrote:
> Am 30.11.21 um 13:56 schrieb Thomas Hellström:
> >
> > On 11/30/21 13:42, Christian König wrote:
> > > Am 30.11.21 um 13:31 schrieb Thomas Hellström:
> > > > [SNIP]
> > > > > Other than that, I didn't investigate the nesting fails
> > > >
== Series Details ==
Series: drm/i915/selftest: Disable IRQ for timestamp calculation (rev3)
URL : https://patchwork.freedesktop.org/series/96853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10943 -> Patchwork_21701
Summa
== Series Details ==
Series: Attempt to avoid dma-fence-[chain|array] lockdep splats
URL : https://patchwork.freedesktop.org/series/97410/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10943 -> Patchwork_21700
Summary
-
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate
> intel_fbc_override_cfb_stride()
>
> From: Ville Syrjälä
>
> Move intel_fbc
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from
> intel_fbc_state_cache
>
> From: Ville Syrjälä
>
> There's no
gt_pm selftest calculates engine ticks cycles and wall time
cycles by delta of respective engine elapsed TIMESTAMP and ktime
for period of 1000us.
It compares the engine ticks cycles with wall time cycles.
Disable local cpu interrupt so that interrupt handler does not
switch out the thread during
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to
> intel_fbc_min_limit()
>
> From: Ville Syrjälä
>
> No reas
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy
> intel_fbc_is_active() usage
>
> From: Ville Syrjälä
>
> The ilk fbc
== Series Details ==
Series: Attempt to avoid dma-fence-[chain|array] lockdep splats
URL : https://patchwork.freedesktop.org/series/97410/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 11/30/21 13:42, Christian König wrote:
Am 30.11.21 um 13:31 schrieb Thomas Hellström:
[SNIP]
Other than that, I didn't investigate the nesting fails enough to
say I can accurately review this. :)
Basically the problem is that within enable_signaling() which is
called with the dma_fence
== Series Details ==
Series: drm/i915/adl-n: Enable ADL-N platform
URL : https://patchwork.freedesktop.org/series/97406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10942 -> Patchwork_21699
Summary
---
**SUCCESS**
On 11/30/21 10:57, Marco Elver wrote:
> The non-interrupt portion of interrupt stack traces before interrupt
> entry is usually arbitrary. Therefore, saving stack traces of interrupts
> (that include entries before interrupt entry) to stack depot leads to
> unbounded stackdepot growth.
>
> As such
On 11/30/21 13:19, Thomas Hellström wrote:
The locking order for taking two fence locks is implicitly defined in
at least two ways in the code:
1) Fence containers first and other fences next, which is defined by
the enable_signaling() callbacks of dma_fence_chain and
dma_fence_array.
2) Rever
On 11/30/21 13:25, Maarten Lankhorst wrote:
On 30-11-2021 13:19, Thomas Hellström wrote:
The locking order for taking two fence locks is implicitly defined in
at least two ways in the code:
1) Fence containers first and other fences next, which is defined by
the enable_signaling() callbacks o
On 30-11-2021 13:19, Thomas Hellström wrote:
> The locking order for taking two fence locks is implicitly defined in
> at least two ways in the code:
>
> 1) Fence containers first and other fences next, which is defined by
> the enable_signaling() callbacks of dma_fence_chain and
> dma_fence_array.
Some dma-fence containers lock other fence's locks from their
enable_signaling() callbacks. We allow one level of nesting from
the dma_fence_add_callback_nested() function, but we would also like to
allow for example dma_fence_chain to point to a dma_fence_array and
vice versa, even though that wou
The locking order for taking two fence locks is implicitly defined in
at least two ways in the code:
1) Fence containers first and other fences next, which is defined by
the enable_signaling() callbacks of dma_fence_chain and
dma_fence_array.
2) Reverse signal order, which is used by __i915_active
Introducing more usage of dma-fence-chain and dma-fence-array in the
i915 driver we start to hit lockdep splats due to the recursive fence
locking in the dma-fence-chain and dma-fence-array containers.
This is a humble suggestion to try to establish a dma-fence locking order
(patch 1) and to avoid
== Series Details ==
Series: drm/i915/adl-n: Enable ADL-N platform
URL : https://patchwork.freedesktop.org/series/97406/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/adl-n: Enable ADL-N platform
URL : https://patchwork.freedesktop.org/series/97406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
39db60e0b083 drm/i915/adl-n: Enable ADL-N platform
-:98: ERROR:COMPLEX_MACRO: Macros with complex values should
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf. (rev2)
URL : https://patchwork.freedesktop.org/series/97371/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10942 -> Patchwork_21698
Summary
---
> From: Eric Farman
> Sent: Tuesday, November 30, 2021 1:18 AM
>
> On Wed, 2021-11-24 at 12:25 +, Liu, Yi L wrote:
> > > From: Jason Gunthorpe
> > > Sent: Fri, 1 Oct 2021 14:52:51 -0300
> > >
> > > The css_driver's main purpose is to create/destroy the mdev and
> > > relay the
> > > shutdown
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf. (rev2)
URL : https://patchwork.freedesktop.org/series/97371/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/i915_gem_evict.c:110: warning: Function parameter or
membe
On Tue, 30 Nov 2021, "Srivatsa, Anusha" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Monday, November 22, 2021 3:28 PM
>> To: Srivatsa, Anusha ; intel-
>> g...@lists.freedesktop.org; Tvrtko Ursulin ;
>> Syrjala, Ville ; Vivi, Rodrigo
>> ; Joonas Lahtinen
>>
>> Cc: Srivatsa,
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf. (rev2)
URL : https://patchwork.freedesktop.org/series/97371/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Remove short term pins from execbuf. (rev2)
URL : https://patchwork.freedesktop.org/series/97371/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d65c71e4c92c drm/i915: Remove unused bits of i915_vma/active api
fadb5f274a4c drm/i915: Change
On 30-11-2021 09:54, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 29/11/2021 13:47, Maarten Lankhorst wrote:
>> New version of the series, with feedback from previous series added.
>
> If there was a cover letter sent for this work in the past could you please
> keep attaching it? Or if there wasn't, coul
Adding PCI device ids and enabling ADL-N platform.
ADL-N from i915 point of view is subplatform of ADL-P.
BSpec: 68397
Signed-off-by: Tejas Upadhyay
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1
> -Original Message-
> From: Jani Nikula
> Sent: Monday, November 22, 2021 3:28 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org; Tvrtko Ursulin ;
> Syrjala, Ville ; Vivi, Rodrigo
> ; Joonas Lahtinen
>
> Cc: Srivatsa, Anusha ; Dhanavanthri, Swathi
>
> Subject: Re: [v2 3
On Mon, 29 Nov 2021, Lyude Paul wrote:
> While working on supporting the Intel HDR backlight interface, I noticed
> that there's a couple of laptops that will very rarely manage to boot up
> without detecting Intel HDR backlight support - even though it's supported
> on the system. One example of
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Monday, November 22, 2021 3:49 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [v2 1/3] drm/i915/rpl-s: Add PCI IDS for Raptor Lake
> S
>
>
> On 20/11/2021 00:29, Anusha Srivatsa wrote:
> >
On Tue, 30 Nov 2021, Ville Syrjälä wrote:
> On Mon, Nov 29, 2021 at 06:19:52PM +0200, Jani Nikula wrote:
>> On Fri, 26 Nov 2021, Uma Shankar wrote:
>> > Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
>> > to incorparate the extended lut size for XE_LPD.
>> >
>> > v2: Added a hel
On Fri, Nov 26, 2021 at 01:57:49AM +0530, Uma Shankar wrote:
> Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
> to incorparate the extended lut size for XE_LPD.
>
> v2: Added a helper for degamma lut size (Ville)
>
> Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
> --
On Fri, Nov 26, 2021 at 01:57:50AM +0530, Uma Shankar wrote:
> XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
> extended range. It has 511 entries for gamma with additional 2 entries
> for extended range.
>
> v2: Updated lut size for 10bit gamma, added lut_tests (Ville)
>
>
On Mon, Nov 29, 2021 at 06:19:52PM +0200, Jani Nikula wrote:
> On Fri, 26 Nov 2021, Uma Shankar wrote:
> > Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
> > to incorparate the extended lut size for XE_LPD.
> >
> > v2: Added a helper for degamma lut size (Ville)
> >
> > Signed-of
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