[Intel-gfx] [PATCH v2 2/2] HAX: drm/i915/selftest: Temporarily avoid tainting the kernel on engine reset failure

2021-11-04 Thread Thomas Hellström
The taint aborts the CI test runner. v2: Comment out GEM_TRACE_DUMP() also active_request_put(). Signed-off-by: Thomas Hellström --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c

[Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Thomas Hellström
Some selftests assume that nothing will attempt to grab these bitlocks while they are held by the selftests. With GuC, for example, that is not true because the hanging workloads may cause the GuC code to attempt to grab them for a global reset, and that may cause it to end up sleeping on the bit n

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Thomas Hellström
On 11/5/21 00:01, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks *URL:* https://patchwork.freedesktop.org/series/96593/ *State:*failure *Details:* https:

Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

2021-11-04 Thread Stephen Rothwell
Hi all, On Mon, 1 Nov 2021 19:42:23 +1100 Stephen Rothwell wrote: > > On Fri, 15 Oct 2021 20:26:48 +1100 Stephen Rothwell > wrote: > > > > After merging the drm-misc tree, today's linux-next build (arm > > multi_v7_defconfig) failed like this: > > > > drivers/gpu/drm/drm_modeset_lock.c:111:29

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3) URL : https://patchwork.freedesktop.org/series/94712/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10842 -> Patchwork_21522 Summary -

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3) URL : https://patchwork.freedesktop.org/series/94712/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +dri

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev3) URL : https://patchwork.freedesktop.org/series/94712/ State : warning == Summary == $ dim checkpatch origin/drm-tip 69ba418e519d drm/hdcp: Add drm_hdcp_atomic_check() -:11: WARNING:BAD_SIGN_OFF: Duplicate

[Intel-gfx] [PATCH v4 14/14] drm/msm: Implement HDCP 1.x using the new drm HDCP helpers

2021-11-04 Thread Sean Paul
From: Sean Paul This patch adds HDCP 1.x support to msm DP connectors using the new HDCP helpers. Cc: Stephen Boyd Cc: Abhinav Kumar Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-15-s...@poorly.run #v1 Link: https://patchwork.freedesktop.

[Intel-gfx] [PATCH v4 13/14] arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller

2021-11-04 Thread Sean Paul
From: Sean Paul This patch adds the register ranges required for HDCP key injection and HDCP TrustZone interaction as described in the dt-bindings for the sc7180 dp controller. Now that these are supported, change the compatible string to "dp-hdcp". Signed-off-by: Sean Paul Link: https://patch

[Intel-gfx] [PATCH v4 12/14] dt-bindings: msm/dp: Add bindings for HDCP registers

2021-11-04 Thread Sean Paul
From: Sean Paul This patch adds the bindings for the MSM DisplayPort HDCP registers which are required to write the HDCP key into the display controller as well as the registers to enable HDCP authentication/key exchange/encryption. We'll use a new compatible string for this since the fields are

[Intel-gfx] [PATCH v4 11/14] drm/msm/dp: Re-order dp_audio_put in deinit_sub_modules

2021-11-04 Thread Sean Paul
From: Sean Paul Audio is initialized last, it should be de-initialized first to match the order in dp_init_sub_modules(). Reviewed-by: Abhinav Kumar Reviewed-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/202109131

[Intel-gfx] [PATCH v4 10/14] drm/msm/dpu: Remove encoder->enable() hack

2021-11-04 Thread Sean Paul
From: Sean Paul encoder->commit() was being misused because there were some global resources which needed to be tweaked in encoder->enable() which were not accessible in dpu_encoder.c. That is no longer true and the redirect serves no purpose any longer. So remove the indirection. Tested-by: Ste

[Intel-gfx] [PATCH v4 09/14] drm/msm/dpu: Remove useless checks in dpu_encoder

2021-11-04 Thread Sean Paul
From: Sean Paul A couple more useless checks to remove in dpu_encoder. Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-10-s...@poorly.run #v1 Link: https://

[Intel-gfx] [PATCH v4 08/14] drm/msm/dpu_kms: Re-order dpu includes

2021-11-04 Thread Sean Paul
From: Sean Paul Make includes alphabetical in dpu_kms.c Reviewed-by: Abhinav Kumar Reviewed-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-9-s...@poorly.run #v1 Link: https://patchwork.freede

[Intel-gfx] [PATCH v4 07/14] drm/i915/hdcp: Use HDCP helpers for i915

2021-11-04 Thread Sean Paul
From: Sean Paul Now that all of the HDCP 1.x logic has been migrated to the central HDCP helpers, use it in the i915 driver. The majority of the driver code for HDCP 1.x will live in intel_hdcp.c, however there are a few helper hooks which are connector-specific and need to be partially or fully

[Intel-gfx] [PATCH v4 06/14] drm/i915/hdcp: Retain hdcp_capable return codes

2021-11-04 Thread Sean Paul
From: Sean Paul The shim functions return error codes, but they are discarded in intel_hdcp.c. This patch plumbs the return codes through so they are properly handled. Acked-by: Jani Nikula Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-7-s..

[Intel-gfx] [PATCH v4 05/14] drm/i915/hdcp: Consolidate HDCP setup/state cache

2021-11-04 Thread Sean Paul
From: Sean Paul Stick all of the setup for HDCP into a dedicated function. No functional change, but this will facilitate moving HDCP logic into helpers. Acked-by: Jani Nikula Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-6-s...@poorly.run

[Intel-gfx] [PATCH v4 04/14] drm/hdcp: Expand HDCP helper library for enable/disable/check

2021-11-04 Thread Sean Paul
From: Sean Paul This patch expands upon the HDCP helper library to manage HDCP enable, disable, and check. Previous to this patch, the majority of the state management and sink interaction is tucked inside the Intel driver with the understanding that once a new platform supported HDCP we could m

[Intel-gfx] [PATCH v4 03/14] drm/hdcp: Update property value on content type and user changes

2021-11-04 Thread Sean Paul
From: Sean Paul This patch updates the connector's property value in 2 cases which were previously missed: 1- Content type changes. The value should revert back to DESIRED from ENABLED in case the driver must re-authenticate the link due to the new content type. 2- Userspace sets value to

[Intel-gfx] [PATCH v4 02/14] drm/hdcp: Avoid changing crtc state in hdcp atomic check

2021-11-04 Thread Sean Paul
From: Sean Paul Instead of forcing a modeset in the hdcp atomic check, simply return true if the content protection value is changing and let the driver decide whether a modeset is required or not. Acked-by: Jani Nikula Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/ms

[Intel-gfx] [PATCH v4 01/14] drm/hdcp: Add drm_hdcp_atomic_check()

2021-11-04 Thread Sean Paul
From: Sean Paul This patch moves the hdcp atomic check from i915 to drm_hdcp so other drivers can use it. No functional changes, just cleaned up some of the code when moving it over. Acked-by: Jani Nikula Acked-by: Jani Nikula Reviewed-by: Abhinav Kumar Signed-off-by: Sean Paul Link: https:

[Intel-gfx] [PATCH v4 00/14] drm/hdcp: Pull HDCP auth/exchange/check into helpers

2021-11-04 Thread Sean Paul
From: Sean Paul Just me with another revision of HDCP support for msm. This v4 patch series is mostly a retread of v3 with the following changes: - rebased on Bjorn's displayport-controller register refactor - another change to the dt bindings to remove the compatible string added in v3 - update

Re: [Intel-gfx] linux-next: manual merge of the char-misc tree with the drm-intel tree

2021-11-04 Thread Stephen Rothwell
Hi all, On Thu, 28 Oct 2021 18:27:53 +1100 Stephen Rothwell wrote: > > Today's linux-next merge of the char-misc tree got a conflict in: > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > > between commit: > > 5740211ea442 ("drm/i915/dmabuf: fix broken build") > > from the drm-intel tree

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private URL : https://patchwork.freedesktop.org/series/96578/ State : success == Summary == CI Bug Log - changes from CI_DRM_10841_full -> Patchwork_21519_full ===

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Update memory bandwidth formulae (rev9)

2021-11-04 Thread Matt Roper
On Thu, Nov 04, 2021 at 11:43:31AM -0700, Sripada, Radhakrishna wrote: >Link: [1]File-List > >  > >  > >From: Patchwork >Sent: Friday, October 15, 2021 6:48 PM >To: Sripada, Radhakrishna >Cc: intel-gfx@lists.freedesktop.org >Subject: ✗ Fi.CI.IGT: failure for drm

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks URL : https://patchwork.freedesktop.org/series/96593/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10841 -> Patchwork_21521 =

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Prep work for multiple FBC instances

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Prep work for multiple FBC instances URL : https://patchwork.freedesktop.org/series/96574/ State : success == Summary == CI Bug Log - changes from CI_DRM_10841_full -> Patchwork_21518_full Summary

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks URL : https://patchwork.freedesktop.org/series/96593/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5a12af63b16e drm/i915/selftests: Use cl

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix synchronization of PMU callback with reset

2021-11-04 Thread Umesh Nerlige Ramappa
On Thu, Nov 04, 2021 at 05:37:37PM +, Tvrtko Ursulin wrote: On 03/11/2021 22:47, Umesh Nerlige Ramappa wrote: Since the PMU callback runs in irq context, it synchronizes with gt reset using the reset count. We could run into a case where the PMU callback could read the reset count before it

[Intel-gfx] [PATCH 2/2] HAX: drm/i915/selftest: Temporarily avoid tainting the kernel on engine reset failure

2021-11-04 Thread Thomas Hellström
Signed-off-by: Thomas Hellström --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 8590419be4c6..e57307f82cf0 100644 --- a/drivers

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Thomas Hellström
Some selftests assume that nothing will attempt to grab these bitlocks while they are held by the selftests. With GuC, for example, that is not true because the hanging workloads may cause the GuC code to attempt to grab them for a global reset, and that may cause it to end up sleeping on the bit n

Re: [Intel-gfx] [PATCH v5 2/3] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.

2021-11-04 Thread Ilia Mirkin
On Thu, Nov 4, 2021 at 4:03 PM Mark Yacoub wrote: > > From: Mark Yacoub > > [Why] > 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma > or Degamma props in the new CRTC state, allowing any invalid size to > be passed on. > 2. Each driver has its own LUT size, which could

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Javier Martinez Canillas
Hello Jani, On 11/4/21 20:57, Jani Nikula wrote: > On Thu, 04 Nov 2021, Javier Martinez Canillas wrote: >> +/** >> + * drm_drv_enabled - Checks if a DRM driver can be enabled >> + * @driver: DRM driver to check >> + * >> + * Checks whether a DRM driver can be enabled or not. This may be the case

[Intel-gfx] [PATCH v5 2/3] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.

2021-11-04 Thread Mark Yacoub
From: Mark Yacoub [Why] 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma or Degamma props in the new CRTC state, allowing any invalid size to be passed on. 2. Each driver has its own LUT size, which could also be different for legacy users. [How] 1. Create |degamma_lut_

[Intel-gfx] [PATCH v5 1/3] drm: Move drm_color_lut_check implementation internal to intel_color

2021-11-04 Thread Mark Yacoub
From: Mark Yacoub [Why] The tests of LUT_EQUAL_CHANNELS and LUT_NON_DECREASING are currently unique to i915 driver. Freeing up the function name for the more generic LUT checks to folllow Tested on Eldrid ChromeOS (TGL). v2: 1. Convert the enum to #define. 2. Add INTEL_COLOR_ prefix. v1: Stuff

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Jani Nikula
On Thu, 04 Nov 2021, Javier Martinez Canillas wrote: > +/** > + * drm_drv_enabled - Checks if a DRM driver can be enabled > + * @driver: DRM driver to check > + * > + * Checks whether a DRM driver can be enabled or not. This may be the case > + * if the "nomodeset" kernel command line parameter is

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Jani Nikula
On Thu, 04 Nov 2021, Sam Ravnborg wrote: > Hi Javier, > >> >> >>> >> >>> -if (vgacon_text_force() && i915_modparams.modeset == -1) >> >>> +ret = drm_drv_enabled(&driver); >> >> >> >> You pass the local driver variable here - which looks wrong as this is >> >> not the same as the

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private URL : https://patchwork.freedesktop.org/series/96578/ State : success == Summary == CI Bug Log - changes from CI_DRM_10841 -> Patchwork_21519 =

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Cleanups for the nomodeset kernel command line parameter logic (rev4)

2021-11-04 Thread Patchwork
== Series Details == Series: Cleanups for the nomodeset kernel command line parameter logic (rev4) URL : https://patchwork.freedesktop.org/series/96527/ State : failure == Summary == Applying: drm: Add a drm_drv_enabled() to check if drivers should be enabled error: sha1 information is lacking

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Sam Ravnborg
Hi Javier, > > >>> > >>> - if (vgacon_text_force() && i915_modparams.modeset == -1) > >>> + ret = drm_drv_enabled(&driver); > >> > >> You pass the local driver variable here - which looks wrong as this is > >> not the same as the driver variable declared in another file. > > > > Yes, Jani ment

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private URL : https://patchwork.freedesktop.org/series/96578/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private

2021-11-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private URL : https://patchwork.freedesktop.org/series/96578/ State : warning == Summary == $ dim checkpatch origin/drm-tip eaff73f1c59d drm/i915/audio: group audio under

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Prep work for multiple FBC instances

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Prep work for multiple FBC instances URL : https://patchwork.freedesktop.org/series/96574/ State : success == Summary == CI Bug Log - changes from CI_DRM_10841 -> Patchwork_21518 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks URL : https://patchwork.freedesktop.org/series/96571/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10840_full -> Patchwork_21517_full ==

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/fbc: Prep work for multiple FBC instances

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Prep work for multiple FBC instances URL : https://patchwork.freedesktop.org/series/96574/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter '

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: Prep work for multiple FBC instances

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Prep work for multiple FBC instances URL : https://patchwork.freedesktop.org/series/96574/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7fa3e082ea85 drm/i915/fbc: Exract snb_fbc_program_fence() e1a5292108ab drm/i915/fbc: Extract {skl,

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Javier Martinez Canillas
Hello Sam, On 11/4/21 18:57, Jani Nikula wrote: > On Thu, 04 Nov 2021, Sam Ravnborg wrote: >> Hi Javier, >> >> On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote: >>> Some DRM drivers check the vgacon_text_force() function return value as an >>> indication on whether they sh

[Intel-gfx] ✓ Fi.CI.IGT: success for kernel/locking: Add context to ww_mutex_trylock. (rev5)

2021-11-04 Thread Patchwork
== Series Details == Series: kernel/locking: Add context to ww_mutex_trylock. (rev5) URL : https://patchwork.freedesktop.org/series/94437/ State : success == Summary == CI Bug Log - changes from CI_DRM_10840_full -> Patchwork_21516_full Sum

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Jani Nikula
On Thu, 04 Nov 2021, Sam Ravnborg wrote: > Hi Javier, > > On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote: >> Some DRM drivers check the vgacon_text_force() function return value as an >> indication on whether they should be allowed to be enabled or not. >> >> This functi

Re: [Intel-gfx] [PATCH v3] drm/i915/display: Exit PSR when doing async flips

2021-11-04 Thread Souza, Jose
On Thu, 2021-11-04 at 16:10 +0200, Ville Syrjälä wrote: > On Tue, Nov 02, 2021 at 12:32:14PM -0700, José Roberto de Souza wrote: > > Changing the buffer in the middle of the scanout then entering an > > period of flip idleness will cause part of the previous buffer being > > diplayed to user when P

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Sam Ravnborg
Hi Javier, On Thu, Nov 04, 2021 at 05:07:06PM +0100, Javier Martinez Canillas wrote: > Some DRM drivers check the vgacon_text_force() function return value as an > indication on whether they should be allowed to be enabled or not. > > This function returns true if the nomodeset kernel command lin

Re: [Intel-gfx] [PATCH v4 1/3] drm: Move drm_color_lut_check implementation internal to intel_color

2021-11-04 Thread Jani Nikula
On Thu, 04 Nov 2021, Mark Yacoub wrote: > From: Mark Yacoub > > [Why] > The tests of LUT_EQUAL_CHANNELS and LUT_NON_DECREASING are currently > unique to i915 driver. > Freeing up the function name for the more generic LUT checks to folllow > > Tested on Eldrid ChromeOS (TGL). > > v1: > Stuff the

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix synchronization of PMU callback with reset

2021-11-04 Thread Tvrtko Ursulin
On 03/11/2021 22:47, Umesh Nerlige Ramappa wrote: Since the PMU callback runs in irq context, it synchronizes with gt reset using the reset count. We could run into a case where the PMU callback could read the reset count before it is updated. This has a potential of corrupting the busyness sta

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Failsafe migration blits (rev7)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits (rev7) URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10840_full -> Patchwork_21515_full Summary ---

[Intel-gfx] [PATCH v4 2/3] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.

2021-11-04 Thread Mark Yacoub
From: Mark Yacoub [Why] 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma or Degamma props in the new CRTC state, allowing any invalid size to be passed on. 2. Each driver has its own LUT size, which could also be different for legacy users. [How] 1. Create |degamma_lut_

[Intel-gfx] [PATCH v4 1/3] drm: Move drm_color_lut_check implementation internal to intel_color

2021-11-04 Thread Mark Yacoub
From: Mark Yacoub [Why] The tests of LUT_EQUAL_CHANNELS and LUT_NON_DECREASING are currently unique to i915 driver. Freeing up the function name for the more generic LUT checks to folllow Tested on Eldrid ChromeOS (TGL). v1: Stuff the test function from DRM to intel driver. Signed-off-by: Mark

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Javier Martinez Canillas
On 11/4/21 17:24, Jani Nikula wrote: [snip] >> index ab2295dd4500..45cb3e540eff 100644 >> --- a/drivers/gpu/drm/i915/i915_module.c >> +++ b/drivers/gpu/drm/i915/i915_module.c >> @@ -18,9 +18,12 @@ >> #include "i915_selftest.h" >> #include "i915_vma.h" >> >> +static const struct drm_driver dri

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks URL : https://patchwork.freedesktop.org/series/96571/ State : success == Summary == CI Bug Log - changes from CI_DRM_10840 -> Patchwork_21517

Re: [Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Jani Nikula
On Thu, 04 Nov 2021, Javier Martinez Canillas wrote: > Some DRM drivers check the vgacon_text_force() function return value as an > indication on whether they should be allowed to be enabled or not. > > This function returns true if the nomodeset kernel command line parameter > was set. But there

[Intel-gfx] [PATCH v3 6/6] drm/i915/audio: rename intel_init_audio_hooks to intel_audio_hooks_init

2021-11-04 Thread Jani Nikula
Follow the filename based prefix naming. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_audio.c | 4 ++-- drivers/gpu/drm/i915/display/intel_audio.h | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/

[Intel-gfx] [PATCH v3 5/6] drm/i915/audio: clean up LPE audio init/cleanup calls

2021-11-04 Thread Jani Nikula
Unify audio init/cleanup paths wrt LPE audio, and base the logic on the return values from LPE audio calls. Move the platform device check on cleanup to intel_lpe_audio.c, thereby limiting all audio.lpe substruct access to that file. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/in

[Intel-gfx] [PATCH v3 4/6] drm/i915/audio: move intel_audio_funcs internal to intel_audio.c

2021-11-04 Thread Jani Nikula
It's all internal to intel_audio.c. Cc: Dave Airlie Reviewed-by: Ville Syrjälä Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_audio.c | 9 + drivers/gpu/drm/i915/i915_drv.h| 10 +- 2 files changed, 10 insertions(+),

[Intel-gfx] [PATCH v3 3/6] drm/i915/audio: define the audio struct separately from drm_i915_private

2021-11-04 Thread Jani Nikula
Add a standalone definition of struct intel_audio_private, and note that all of it is private to intel_audio.c. v2: Rebase Cc: Dave Airlie Reviewed-by: Ville Syrjälä Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 45 ++---

[Intel-gfx] [PATCH v3 2/6] drm/i915/audio: name the audio sub-struct in drm_i915_private

2021-11-04 Thread Jani Nikula
Add name to the audio sub-struct in drm_i915_private, and remove the tautologies and other inconsistencies in the member names. v2: Call the mutex member mutex, not lock. (Ville) Cc: Dave Airlie Reviewed-by: Ville Syrjälä Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gp

[Intel-gfx] [PATCH v3 1/6] drm/i915/audio: group audio under anonymous struct in drm_i915_private

2021-11-04 Thread Jani Nikula
With an anonymous struct, this can be pure hierarchical organization without code changes. We'll follow up with adding a name to the sub-struct separately. Cc: Dave Airlie Reviewed-by: Ville Syrjälä Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h |

[Intel-gfx] [PATCH v2 2/2] drm: Move nomodeset kernel parameter to the DRM subsystem

2021-11-04 Thread Javier Martinez Canillas
The "nomodeset" kernel cmdline parameter is handled by the vgacon driver but the exported vgacon_text_force() symbol is only used by DRM drivers. It makes much more sense for the parameter logic to be in the subsystem of the drivers that are making use of it. Let's move the vgacon_text_force() fu

[Intel-gfx] [PATCH v2 1/2] drm: Add a drm_drv_enabled() to check if drivers should be enabled

2021-11-04 Thread Javier Martinez Canillas
Some DRM drivers check the vgacon_text_force() function return value as an indication on whether they should be allowed to be enabled or not. This function returns true if the nomodeset kernel command line parameter was set. But there may be other conditions besides this to determine if a driver s

[Intel-gfx] [PATCH v2 0/2] Cleanups for the nomodeset kernel command line parameter logic

2021-11-04 Thread Javier Martinez Canillas
There is a lot of historical baggage on this parameter. It is defined in the vgacon driver as nomodeset, but its set function is called text_mode() and the value queried with a function named vgacon_text_force(). All this implies that it's about forcing text mode for VGA, yet it is not used in nei

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Matthew Brost
On Thu, Nov 04, 2021 at 01:58:44PM +0100, Thomas Hellström wrote: > Some selftests assume that nothing will attempt to grab these bitlocks > while they are held by the selftests. With GuC, for example, that is > not true because the hanging workloads may cause the GuC code to attempt > to grab them

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Fix synchronization of PMU callback with reset

2021-11-04 Thread Matthew Brost
On Wed, Nov 03, 2021 at 03:47:08PM -0700, Umesh Nerlige Ramappa wrote: > Since the PMU callback runs in irq context, it synchronizes with gt > reset using the reset count. We could run into a case where the PMU > callback could read the reset count before it is updated. This has a > potential of co

[Intel-gfx] ✓ Fi.CI.BAT: success for kernel/locking: Add context to ww_mutex_trylock. (rev5)

2021-11-04 Thread Patchwork
== Series Details == Series: kernel/locking: Add context to ww_mutex_trylock. (rev5) URL : https://patchwork.freedesktop.org/series/94437/ State : success == Summary == CI Bug Log - changes from CI_DRM_10840 -> Patchwork_21516 Summary -

Re: [Intel-gfx] [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate

2021-11-04 Thread Ville Syrjälä
On Thu, Nov 04, 2021 at 09:48:41AM +0100, Maxime Ripard wrote: > Hi Ville, > > On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote: > > On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote: > > > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote: > > > > --- a/driver

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Failsafe migration blits (rev7)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits (rev7) URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10840 -> Patchwork_21515 Summary --- **SUCCES

Re: [Intel-gfx] refactor the i915 GVT support and move to the modern mdev API v2

2021-11-04 Thread Wang, Zhi A
Hi Joonas and Christoph: We were testing the patch series since Monday and planning to reply after we get the test result. Mostly, we are concerned about patch 6 and how it would affect the test result. Patch 6 changes the timing of loading GVT-g. According to the discussion in the last email,

[Intel-gfx] [PATCH 17/17] drm/1915/fbc: Replace plane->has_fbc with a pointer to the fbc instance

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä With multiple fbc instances we need to find the right one for each plane. Rather than going looking for the right instance every time let's just replace the has_fbc boolean with a pointer that gets us there straight away. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 16/17] drm/i915/fbc: Start passing around intel_fbc

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä In preparation for multiple FBC instances start passing around intel_fbc pointers rather than i915 pointers. And once there are multiple of these we can't rely on container_of() to get back to the i915, so we toss in a fbc->i915 pointer already. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 15/17] drm/i915/fbc: s/dev_priv/i915/

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Rename 'dev_priv' to 'i915' to match modern style. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 526 +++ 1 file changed, 263 insertions(+), 263 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/

[Intel-gfx] [PATCH 14/17] drm/i915: Relocate FBC_LLC_READ_CTRL

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä In the case of FBC_LLC_READ_CTRL the "FBC" stands for frame buffer _caching_, not frame buffer compression. Move the register definition out from the middle of the frame buffer compression register definitions. Let's just stick it somewhere with similar looking register offset

[Intel-gfx] [PATCH 13/17] drm/i915/fbc: Finish polishing FBC1 registers

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Switch all the FBC1 registers over to REG_BTT()/etc. And while at it add a few more registers/bits that escaped the net previously. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 62 +

[Intel-gfx] [PATCH 12/17] drm/i915/fbc: Clean up all register defines

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä The FBC register defines are a mess: - namespace changes between DPFC_, FBC_, and some platform specific prefix at a whim - ilk+ reuses most g4x bits but still has some separate bit defines elsewhere - it's not clear from the defines that the bit defines are shared So l

[Intel-gfx] [PATCH 11/17] drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Just use a same mask for ivb/hsw as for bdw+. The extra bit in the bdw mask is mbz on ivb/hsw anyway so this is just pointless complexity. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 3 +--

[Intel-gfx] [PATCH 10/17] drm/i915/fbc: Introduce intel_fbc_set_false_color()

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Pull the direct FBC register frobbing out from the debugfs code into the fbc code. Also add a vfunc for this so we don't need extra platforms checks. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_debugfs.c | 18 + drivers/gpu/drm/i915/disp

[Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Eliminate the last if-ladder by pulling the CFB/LLB programming into a vfunc as well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 56 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 08/17] drm/i915/fbc: s/gen7/ivb/

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä "gen7" in display code is not really sensible. We shall call these things "ivb". Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel

[Intel-gfx] [PATCH 07/17] drm/i915/fbc: Introduce .nuke() vfunc

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Eliminate yet another if-ladder by adding .nuke() vfunc. We also rename all *_recompress() stuff to *_nuke() since that's the terminology the spec uses. Also "recompress" is a bit confusing by perhaps implying that this triggers an immediate recompression. Depending on the ha

[Intel-gfx] [PATCH 06/17] drm/i915/fbc: Introduce intel_fbc_funcs

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Replace the "if-ladders everywhere" approach with vfuncs. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 80 +++- drivers/gpu/drm/i915/i915_drv.h | 3 + 2 files changed, 55 insertions(+), 28 deletions(-) diff --git

[Intel-gfx] [PATCH 05/17] drm/i915/fbc: Extract helpers to compute FBC control register values

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Declutter the *_fbc_activate() functions by pulling all the control register value computations into helpers. I left the enable bit in *_fbc_activate() in the hopes of maybe using the helpers in the *_fbc_deactivate() paths as well instead of the current rmw approach. That wo

[Intel-gfx] [PATCH 04/17] drm/i915/fbc: Introduce intel_fbc_is_compressing()

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Move the direct FBC status register reads from the debugfs code behind an abstract api. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_debugfs.c | 23 +++- drivers/gpu/drm/i915/display/intel_fbc.c | 36 +++ drivers/gpu/drm/

[Intel-gfx] [PATCH 03/17] drm/i915/fbc: Just use params->fence_y_offset always

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä No need to tiptoe around programming DPFC_FENCE_YOFF with params->fence_y_offset vs. 0. If the fence is not enabled it doesn't even matter what we program here. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 10 -- 1 file changed, 4 inse

[Intel-gfx] [PATCH 00/17] drm/i915/fbc: Prep work for multiple FBC instances

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Bunch of refactoring and cleanups, mainly as prep work for introducing multiple FBC instances in the future. Ville Syrjälä (17): drm/i915/fbc: Exract snb_fbc_program_fence() drm/i915/fbc: Extract {skl,glk}_fbc_program_cfb_stride() drm/i915/fbc: Just use params->fence_y_

[Intel-gfx] [PATCH 02/17] drm/i915/fbc: Extract {skl, glk}_fbc_program_cfb_stride()

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä Declutter gen7_fbc_activate() by sucking the override stride programming stuff into helpers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 53 +++- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH 01/17] drm/i915/fbc: Exract snb_fbc_program_fence()

2021-11-04 Thread Ville Syrjala
From: Ville Syrjälä We have two identical copies of the snb+ system agent CPU fence programming code. Extract into a helper. Also there's no real point in insisting that we program 0 into DPFC_CPU_FENCE_OFFSET when the fence is disabled. So just always stick the computed Y offset there whether o

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Failsafe migration blits (rev7)

2021-11-04 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits (rev7) URL : https://patchwork.freedesktop.org/series/95617/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7fdc5097e400 drm/i915/ttm: Reorganize the ttm move code -:511: WARNING:FILE_PATH_CHANGES: added, moved or d

Re: [Intel-gfx] [PATCH v3] drm/i915/display: Exit PSR when doing async flips

2021-11-04 Thread Ville Syrjälä
On Tue, Nov 02, 2021 at 12:32:14PM -0700, José Roberto de Souza wrote: > Changing the buffer in the middle of the scanout then entering an > period of flip idleness will cause part of the previous buffer being > diplayed to user when PSR is enabled. > > So here disabling PSR and scheduling activat

Re: [Intel-gfx] refactor the i915 GVT support and move to the modern mdev API v2

2021-11-04 Thread Joonas Lahtinen
Hi Zhenyu and Zhi, Can you have somebody from the GVT team to review the patches that are fully contained in gvt/ ? I also started discussion on patch 6 which is about defining the interface between the modules. I remember there is prior work to shrink the interface. Do you have links to such pat

[Intel-gfx] [PATCH] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks

2021-11-04 Thread Thomas Hellström
Some selftests assume that nothing will attempt to grab these bitlocks while they are held by the selftests. With GuC, for example, that is not true because the hanging workloads may cause the GuC code to attempt to grab them for a global reset, and that may cause it to end up sleeping on the bit n

Re: [Intel-gfx] [PATCH 06/29] drm/i915/gvt: move the gvt code into kvmgt.ko

2021-11-04 Thread Joonas Lahtinen
+ Thomas, Maarten and Matt (Also, Zhi and Zhenyu, please see down) Quoting Christoph Hellwig (2021-11-02 09:05:38) > Instead of having an option to build the gvt code into the main i915 > module, just move it into the kvmgt.ko module. This only requires > a new struct with three entries that the

Re: [Intel-gfx] [PATCH 02/29] drm/i915/gvt: integrate into the main Makefile

2021-11-04 Thread Joonas Lahtinen
Quoting Christoph Hellwig (2021-11-02 09:05:34) > Remove the separately included Makefile and just use the relative > reference from the main i915 Makefile as for source files in other > subdirectories. The thinking behind the split is to avoid any merge conflicts as the gvt/ subdirectory is handl

[Intel-gfx] [PATCH] kernel/locking: Use a pointer in ww_mutex_trylock().

2021-11-04 Thread Sebastian Andrzej Siewior
mutex_acquire_nest() expects a pointer, pass the pointer. Fixes: 12235da8c80a1 ("kernel/locking: Add context to ww_mutex_trylock()") Signed-off-by: Sebastian Andrzej Siewior --- Not sure why I haven't seen this earlier… kernel/locking/ww_rt_mutex.c | 2 +- 1 file changed, 1 insertion(+), 1 del

[Intel-gfx] [PATCH v6 2/2] drm/i915/ttm: Failsafe migration blits

2021-11-04 Thread Thomas Hellström
If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages. Intercept the blit fence with an async callback that checks the blit fence for errors and if there are errors perform

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