On Thu, Oct 07, 2021 at 05:52:47AM +, Li, Juston wrote:
> On Thu, 2021-10-07 at 02:57 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > No real reason to have this pxp state computation in
> > intel_atomic_check_planes(). Just stuff it into skl_plane_check().
> >
> > There was also
On Thu, 2021-10-07 at 02:57 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I was just perusing skl_program_plane() when I stumbled on
> this slightly iffy pxp stuff. Let's try to clean it up.
>
> Cc: Anshuman Gupta
> Cc: Daniele Ceraolo Spurio
> Cc: Juston Li
> Cc: Rodrigo Vivi
> Cc:
On Thu, 2021-10-07 at 02:57 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> intel_load_plane_csc_black() is specific to glk+ so deserves
> a name reflecting that fact. Also rename the variables to
> standard form so I won't get confused reading the code.
>
> Cc: Anshuman Gupta
> Cc: Danie
On Thu, 2021-10-07 at 02:57 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We are inside the vblank evade critical section here, racing
> against the raster beam. There is no time to print debug
> messages.
>
> Cc: Anshuman Gupta
> Cc: Daniele Ceraolo Spurio
> Cc: Juston Li
> Cc: Rodri
On Thu, 2021-10-07 at 02:57 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No real reason to have this pxp state computation in
> intel_atomic_check_planes(). Just stuff it into skl_plane_check().
>
> There was also some funny state copying being done from the
> old plane state to the new
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out
URL : https://patchwork.freedesktop.org/series/95541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10691_full -> Patchwork_21273_full
Summary
-
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out
URL : https://patchwork.freedesktop.org/series/95541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10691 -> Patchwork_21273
Summary
---
== Series Details ==
Series: drm/i915: Clean up the pxp stuff
URL : https://patchwork.freedesktop.org/series/95538/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10691_full -> Patchwork_21272_full
Summary
---
**FAILU
On 10/4/2021 15:06, Matthew Brost wrote:
Calling switch_to_kernel_context isn't needed if the engine PM reference
is taken while all user contexts are pinned as if don't have PM ref that
guarantees that all user contexts scheduling is disabled. By not calling
switch_to_kernel_context we save on i
On 10/4/2021 15:06, Matthew Brost wrote:
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a scheduling of user context could be enabled.
I'm not sure what 'while a scheduling of user context could be enabled'
means.
John.
Returning GT idle when it is not ca
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out
URL : https://patchwork.freedesktop.org/series/95541/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/d
On 10/4/2021 15:06, Matthew Brost wrote:
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a deregister context H2G is in flight. To do this must
issue the deregister H2G from a worker as context can be destroyed from
an atomic context and taking GT PM ref blows
== Series Details ==
Series: drm/i915/display: refactor plane config + pin out
URL : https://patchwork.freedesktop.org/series/95541/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
366ca42bffbf drm/i915/display: move plane prepare/cleanup to
intel_atomic_plane.c
-:38: WARNING:UN
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 760436b
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 34 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/inte
From: Dave Airlie
This just cleans up the calls a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 64 +-
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/displ
From: Dave Airlie
This just moves this code out of the i915_display.c into a new
standalone file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
From: Dave Airlie
This moves this functionality out of intel_display.c to separate
self-contained file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 279 +
drivers/gpu/drm/i915/display/inte
From: Dave Airlie
This just pulls this out into a function so it can be moved to
another file easier.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +++-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Dave Airlie
Make future refactoring simpler, but also this function is pretty
trivial.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++
2 files changed, 10 insertions(+),
From: Dave Airlie
Start to refactor more stuff out of intel_display.c. These fit
better in this file.
This moves the rps boosting code as well as this is the only user of it.
Signed-off-by: Dave Airlie
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 208 ++
drivers/gpu/drm
This is another series in the refactor intel_display.c into more manageable
places.
This moves the initial plane config and all the fb pin/unpin code out.
It also refactors both a little to make the interfaces cleaner.
Dave.
== Series Details ==
Series: drm/i915: DP per-lane drive settings for icl+
URL : https://patchwork.freedesktop.org/series/95535/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10691_full -> Patchwork_21271_full
Summary
-
On 10/4/2021 15:06, Matthew Brost wrote:
Move guc_id allocation under submission state sub-struct as a future
patch will reuse the spin lock as a global submission state lock. Moving
this into sub-struct makes ownership of fields / lock clear.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/
== Series Details ==
Series: drm/i915: Clean up the pxp stuff
URL : https://patchwork.freedesktop.org/series/95538/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10691 -> Patchwork_21272
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915: DP per-lane drive settings for icl+
URL : https://patchwork.freedesktop.org/series/95535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10691 -> Patchwork_21271
Summary
---
**SU
== Series Details ==
Series: drm/i915: DP per-lane drive settings for icl+
URL : https://patchwork.freedesktop.org/series/95535/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i
== Series Details ==
Series: drm/i915: DP per-lane drive settings for icl+
URL : https://patchwork.freedesktop.org/series/95535/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
284e669a57b2 drm/i915: Remove pointless extra namespace from dkl/snps buf trans
structs
0f71d656b29b d
== Series Details ==
Series: i915/display/dmc: Add Support for PipeC and PipeD DMC
URL : https://patchwork.freedesktop.org/series/95532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10691 -> Patchwork_21270
Summary
---
From: Ville Syrjälä
intel_load_plane_csc_black() is specific to glk+ so deserves
a name reflecting that fact. Also rename the variables to
standard form so I won't get confused reading the code.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Sig
From: Ville Syrjälä
We are inside the vblank evade critical section here, racing
against the raster beam. There is no time to print debug
messages.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm
From: Ville Syrjälä
There's lots of expensive stuff inserted between the PLANE_CTL
and PLANE_SURF writes even though the comment before the PLANE_CTL
write says not to put stuff there. Move it all to a more apporiate
place.
There's also a weird PLANE_COLOR_CTL RMW in there. I guess because
forc
From: Ville Syrjälä
No real reason to have this pxp state computation in
intel_atomic_check_planes(). Just stuff it into skl_plane_check().
There was also some funny state copying being done from the
old plane state to the new plane state when the plane is anyway
disabled.
The one thing we pres
From: Ville Syrjälä
I was just perusing skl_program_plane() when I stumbled on
this slightly iffy pxp stuff. Let's try to clean it up.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Ville Syrjälä (4):
drm/i915: Move the pxp plane state comput
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev6)
URL : https://patchwork.freedesktop.org/series/95127/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10690_full -> Patchwork_21269_full
===
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev6)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10690 -> Patchwork_21269
=
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev6)
URL : https://patchwork.freedesktop.org/series/95127/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
On Mon, Oct 04, 2021 at 03:06:32PM -0700, Matthew Brost wrote:
> Allow multiple batch buffers to be submitted in a single execbuf IOCTL
> after a context has been configured with the 'set_parallel' extension.
> The number batches is implicit based on the contexts configuration.
>
> This is impleme
From: Ville Syrjälä
Our lane power down defines already include the necessary shift,
don't shit them a second time.
Fortunately we masked off the correct bits, so we accidentally
left all lanes powered up all the time.
Bits 8-11 where we end up writing our misdirected lane mask are
documented a
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++--
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 111 ---
1 file changed, 39 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++-
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Now that the link buf_trans, link training, and the
combo/mg/dkl/snps phy programming are all fixed up we can
allow per-lane DP drive settings on icl+. Make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 -
1 file chang
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.
From: Ville Syrjälä
Add the FOO_LN() register macros for all the icl combo phy registers.
Also get rid of the semi-pointless FOO_LN0() variants and just use
the parametrized version.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++---
drivers/gp
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Note that the code only does two loops, with each one writing the
levels for two TX lanes. The register offsets also look a bit funny
because each time through the loop we write to the exact sa
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Note that the code only does two loops, with each one writing the
levels for two TX lanes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 -
1 fil
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b
From: Ville Syrjälä
Program each TX lane individually so that we can start to use per-lane
drive settings.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++--
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i9
From: Ville Syrjälä
Pull the convoluted loadgen calculation into a small helper.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/dr
From: Ville Syrjälä
DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
also the spec says to skip all loadgen stuff.
The code was dead anyway since it wasn't actually writing the value
anywhere.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
From: Ville Syrjälä
Use <4 instead of <=3 as the terminating condition for the
loops over the 4 lanes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/d
From: Ville Syrjälä
All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
fit into u8. Shrink the types accordingly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drive
From: Ville Syrjälä
The struct itself already has sufficient namespace. No need to
duplicate it in the members.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
drivers/gpu/drm
From: Ville Syrjälä
All the generic link training code should be in check now.
Let's move on to actually programming the each TX lane with
its own individual settings.
Ville Syrjälä (16):
drm/i915: Remove pointless extra namespace from dkl/snps buf trans
structs
drm/i915: Shrink {icl_mg,
So far we had support for main, PipeA and PipeB
DMC. If we find a binary from PipeA-D, lets load it.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/driver
On Wed, Oct 06, 2021 at 10:11:58AM +0100, Tvrtko Ursulin wrote:
On 05/10/2021 18:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to th
On Wed, 2021-10-06 at 18:30 +0200, Karol Herbst wrote:
> On Wed, Oct 6, 2021 at 4:41 AM Lyude Paul wrote:
> >
> > Since we don't support hybrid AUX/PWM backlights in nouveau right now,
> > let's add some explicit checks so that we don't break nouveau once we
> > enable support for these backlight
On Wed, 2021-10-06 at 11:50 +0300, Gwan-gyeong Mun wrote:
>
> On 10/6/21 2:18 AM, José Roberto de Souza wrote:
> > Alderlake-P was getting 'max time under evasion' messages when PSR2
> > is enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
> > period of time longer than VBLANK_EVASION_
On Wed, Oct 06, 2021 at 07:48:18PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 06, 2021 at 07:09:02PM +0300, Imre Deak wrote:
> > On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Unify all debug prints during link training to include information
>
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev5)
URL : https://patchwork.freedesktop.org/series/95127/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10689_full -> Patchwork_21267_full
===
On 06/10/2021 18:12, Matthew Brost wrote:
On Mon, Oct 04, 2021 at 03:36:48PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement GuC
priority management") introduc
On 06/10/2021 18:24, Matthew Brost wrote:
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Introduce the concept of context nice value which matches the process
nice.
We do this by extending the struct i915_sched_attr and add a helper
(i915_sched_attr_pri
On 10/6/21 12:24 AM, Christian König wrote:
Am 06.10.21 um 09:20 schrieb Stephen Rothwell:
Hi Randy,
On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap wrote:
on i386:
ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference to
`msm_hdmi_phy_8996_cfg'
Full randconfig fle
== Series Details ==
Series: HAX: drm/i915: Disable GuC submission by default.
URL : https://patchwork.freedesktop.org/series/95507/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10689_full -> Patchwork_21266_full
Summary
-
== Series Details ==
Series: drm/i915: PREEMPT_RT related fixups. (rev2)
URL : https://patchwork.freedesktop.org/series/95463/
State : failure
== Summary ==
Applying: drm/i915: Use preempt_disable/enable_rt() where recommended
Applying: drm/i915: Don't disable interrupts on PREEMPT_RT during a
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Introduce the concept of context nice value which matches the process
> nice.
>
> We do this by extending the struct i915_sched_attr and add a helper
> (i915_sched_attr_priority) to be used to convert to e
On Mon, Oct 04, 2021 at 03:36:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Introduce the concept of context nice value which matches the process
> nice.
>
> We do this by extending the struct i915_sched_attr and add a helper
> (i915_sched_attr_priority) to be used to convert to e
On Mon, Oct 04, 2021 at 03:36:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
> i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement GuC
> priority management") introduced some scheduling related vfuncs whi
On Wed, Oct 06, 2021 at 09:22:42AM +0100, Tvrtko Ursulin wrote:
>
> On 06/10/2021 00:14, Matthew Brost wrote:
> > On Tue, Oct 05, 2021 at 10:47:11AM -0700, Umesh Nerlige Ramappa wrote:
> > > With GuC handling scheduling, i915 is not aware of the time that a
> > > context is scheduled in and out of
On Wed, Oct 06, 2021 at 06:45:31PM +0300, Kai Vehmanen wrote:
> Hi,
>
> On Wed, 6 Oct 2021, Ville Syrjälä wrote:
>
> > On Mon, Sep 13, 2021 at 07:40:04PM +0300, Kai Vehmanen wrote:
> > > XE_LPD display adds support for display audio codec keepalive feature.
> > > This feature works also when disp
== Series Details ==
Series: drm/i915/mst: abstract intel_dp_mst_source_support()
URL : https://patchwork.freedesktop.org/series/95506/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10689_full -> Patchwork_21265_full
Summar
On Wed, Oct 06, 2021 at 07:09:02PM +0300, Imre Deak wrote:
> On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Unify all debug prints during link training to include information
> > on both the encoder and the LTTPR. We unify the format to something
>
On 2021-10-06 12:15:21 [+0200], To Ville Syrjälä wrote:
> On 2021-10-06 12:34:19 [+0300], Ville Syrjälä wrote:
> > I think the correct answer is to make uncore.lock a raw_spinlock.
> > Without the tracepoints deubgging any of this is stuff pretty much
> > impossible. We also take that lock a lot.
>
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev5)
URL : https://patchwork.freedesktop.org/series/95127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10689 -> Patchwork_21267
=
On Wed, Oct 6, 2021 at 4:41 AM Lyude Paul wrote:
>
> Since we don't support hybrid AUX/PWM backlights in nouveau right now,
> let's add some explicit checks so that we don't break nouveau once we
> enable support for these backlights in other drivers.
>
> Signed-off-by: Lyude Paul
> ---
> driver
On Mon, Oct 04, 2021 at 08:05:35PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I suppose intel_dp_dump_link_status() might be useful for diagnosing
> link training failures. Hoever we only call from the channel EQ phase
> currently. Let's call it from the CR phase as well.
>
> Signed-o
== Series Details ==
Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers
(rev5)
URL : https://patchwork.freedesktop.org/series/95127/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Unify all debug prints during link training to include information
> on both the encoder and the LTTPR. We unify the format to something
> like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
> sur
Hi,
On Wed, 6 Oct 2021, Ville Syrjälä wrote:
> On Mon, Sep 13, 2021 at 07:40:04PM +0300, Kai Vehmanen wrote:
> > XE_LPD display adds support for display audio codec keepalive feature.
> > This feature works also when display codec is in D3 state and the audio
> > link is off (BCLK off). To enable
On Mon, Oct 04, 2021 at 08:05:33PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print out each DP vswing adjustment request we got from the RX.
> Could help in diagnosing what's going on during link training.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> .../drm/i
On Mon, Oct 04, 2021 at 08:05:32PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Indicate which LTTPR we're currently attempting to train when
> we print which training pattern we're using.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/
On Mon, Oct 04, 2021 at 08:05:31PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we consider the max vswing reached when we transmit a
> the max voltage level, but we don't consider pre-emphasis at all.
> This kinda matches older DP specs that only had some vague text
> about tr
== Series Details ==
Series: series starting with [v7,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95501/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10688_full -> Patchwork_21264_full
=
== Series Details ==
Series: HAX: drm/i915: Disable GuC submission by default.
URL : https://patchwork.freedesktop.org/series/95507/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10689 -> Patchwork_21266
Summary
---
Hi,
On Tue, 5 Oct 2021, Greg KH wrote:
> On Wed, Sep 22, 2021 at 11:54:32AM +0300, Kai Vehmanen wrote:
> > In current code, the devres group for aggregate master is left open
> > after call to component_master_add_*(). This leads to problems when the
> > master does further managed allocations on
On Mon, Sep 13, 2021 at 07:40:04PM +0300, Kai Vehmanen wrote:
> XE_LPD display adds support for display audio codec keepalive feature.
> This feature works also when display codec is in D3 state and the audio
> link is off (BCLK off). To enable this functionality, display driver
> must update the A
Hi,
On 06/10/2021 08:58, Barry Song wrote:
On Wed, Oct 6, 2021 at 5:15 PM Wanghui (John) wrote:
HI Tvrtko
On 2021/10/4 22:36, Tvrtko Ursulin wrote:
void set_user_nice(struct task_struct *p, long nice)
{
bool queued, running;
- int old_prio;
+ int old_prio, ret;
== Series Details ==
Series: HAX: drm/i915: Disable GuC submission by default.
URL : https://patchwork.freedesktop.org/series/95507/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84ffb0236665 HAX: drm/i915: Disable GuC submission by default.
-:9: WARNING:COMMIT_LOG_LONG_LINE: P
== Series Details ==
Series: drm/i915/mst: abstract intel_dp_mst_source_support()
URL : https://patchwork.freedesktop.org/series/95506/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10689 -> Patchwork_21265
Summary
---
On Wed, Oct 06, 2021 at 01:16:18PM +0300, Jani Nikula wrote:
> Add a function for checking source MST support. Drop intel_dp->can_mst
> and use intel_dp->mst_mgr.cbs to indicate the same. It's the single
> point of truth without additional state variables. In code, "source
> support" is also self-d
On 06/10/2021 13:36, Christian König wrote:
Just exercising a very minor subset of the functionality, but already
proven useful.
v2: add missing locking
v3: some more cleanup and consolidation, add unlocked test as well
Signed-off-by: Christian König
---
drivers/dma-buf/Makefile | 3
On 06/10/2021 13:36, Christian König wrote:
A simpler version of the iterator to be used when the dma_resv object is
locked.
v2: fix index check here as well
v3: minor coding improvement, some documentation cleanup
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 51
== Series Details ==
Series: series starting with [1/1] usb: typec: altmodes/displayport: reorder
dp_altmode_configured()
URL : https://patchwork.freedesktop.org/series/95499/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10687_full -> Patchwork_21263_full
===
== Series Details ==
Series: series starting with [v7,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10688 -> Patchwork_21264
===
== Series Details ==
Series: series starting with [v7,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95501/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checke
== Series Details ==
Series: series starting with [v7,1/8] drm/i915/gem: Break out some shmem
backend utils
URL : https://patchwork.freedesktop.org/series/95501/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4bb02dc6bd4 drm/i915/gem: Break out some shmem backend utils
1d75863
Am 06.10.21 um 09:20 schrieb Stephen Rothwell:
Hi Randy,
On Tue, 5 Oct 2021 22:48:03 -0700 Randy Dunlap wrote:
on i386:
ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference to
`msm_hdmi_phy_8996_cfg'
Full randconfig fle is attached.
This would be because CONFIG_
Hi Dave, Daniel,
Handling drm-misc-next this week for Maxime.
drm-misc-next-2021-10-06:
drm-misc-next for v5.16:
UAPI Changes:
- Allow empty drm leases for creating separate GEM namespaces.
Cross-subsystem Changes:
- Slightly rework dma_buf_poll.
- Add dma_resv_for_each_fence_unlocked to iterat
No need for review. Submitting to test if this affects the DG1-6 selftest hang.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_
1 - 100 of 130 matches
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