So far, DCS backlight driver hardcode (0xFF) for max brightness level.
MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
And VBT brightness precision bits can support 8 ~ 16 bits.
We should set correct precision bits in VBT that meet panel's request.
Driver can refer to this
According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.
Cc: Ville
Driver has to swap the endian before send brightness level value
to tcon.
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Vandita Kulkarni
Cc: Cooper Chiou
Cc: William Tseng
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 3 +--
1 file changed, 1 insertion(+),
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confir
Driver should wait for free header or payload buffer in FIFO.
It would be good to wait a while for HW to release credit before
give it up to write to HW. Without sending initailize command
sets completely. It would caused MIPI display can't light up properly.
Cc: Ville Syrjala
Cc: Jani Nikula
Cc
DSI driver should have its own implementation to toggle
gpio pins based on GPIO info coming from VBT sequences.
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Vandita Kulkarni
Cc: Cooper Chiou
Cc: William Tseng
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44
Transfer "gpio_nunmber" instead of "gpio_index" while doing
gpio configuration in icl_exec_gpio().
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Vandita Kulkarni
Cc: Cooper Chiou
Cc: William Tseng
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
1 file changed, 1
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
v3:
- Add two patches that fix MIPI DCS backlight control.
Lee Shawn C (7):
drm/i915/dsi: send correct gpio_number on gen11 platform
drm/i915/jsl: program DSI panel GPIOs
drm/i915/dsi: wait for he
== Series Details ==
Series: ADL DDI translation buffer updates (rev2)
URL : https://patchwork.freedesktop.org/series/92921/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
faad50971bdd drm/i915/adl_s: Update ddi buf translation tables
43e59f118335 drm/i915/adl_p: Add ddi buf tra
On Thu, Jul 22, 2021 at 04:29:22PM -0700, Lucas De Marchi wrote:
> Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
> in intel_bios.c") moved the workaround for broken or missing VBT to
> intel_bios.c. However is_port_valid() only protects the handling of
> different skus of t
ADL-P now has its own set of DDI buf translation tables (except for eDP
which appears to be the same as TGL). Add the new values (last updated
in bspec 2021-07-22) to the driver.
v2:
- Actually hook up the new tables via encoder->get_buf_trans()
Bspec: 49291
Signed-off-by: Matt Roper
---
.../
The hardware team updates the translation tables on 2021-06-23. Let's
update the driver accordingly.
Bspec: 49291
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_ddi_buf_trans.c| 44 +--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm
Both ADL-S and ADL-P have had some updates to their combo PHY DDI buf
translation tables.
Matt Roper (2):
drm/i915/adl_s: Update ddi buf translation tables
drm/i915/adl_p: Add ddi buf translation tables for combo PHY
.../drm/i915/display/intel_ddi_buf_trans.c| 148 +++---
1 f
ADL-P now has its own set of DDI buf translation tables (except for eDP
which appears to be the same as TGL). Add the new values (last updated
in bspec 2021-07-22) to the driver.
Bspec: 49291
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_ddi_buf_trans.c| 104 ++
1
== Series Details ==
Series: Remaining patches for basic GuC submission
URL : https://patchwork.freedesktop.org/series/92912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10374_full -> Patchwork_20686_full
Summary
---
== Series Details ==
Series: drm/i915/gt: nuke gen6_hw_id
URL : https://patchwork.freedesktop.org/series/92916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10376 -> Patchwork_20687
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
(rev2)
URL : https://patchwork.freedesktop.org/series/92902/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373_full -> Patchwork_20685_full
===
== Series Details ==
Series: Remaining patches for basic GuC submission
URL : https://patchwork.freedesktop.org/series/92912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10374 -> Patchwork_20686
Summary
---
**SUCCE
== Series Details ==
Series: Remaining patches for basic GuC submission
URL : https://patchwork.freedesktop.org/series/92912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4c2a95bc42c drm/i915/guc: GuC virtual engines
-:595: CHECK:LINE_SPACING: Please don't use multiple blank
== Series Details ==
Series: drm/i915: Extend Wa_1406941453 to adl-p
URL : https://patchwork.freedesktop.org/series/92905/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373_full -> Patchwork_20684_full
Summary
---
== Series Details ==
Series: drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
(rev2)
URL : https://patchwork.freedesktop.org/series/92902/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373 -> Patchwork_20685
=
This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
recent platforms do not depend on this field, so it doesn't make much
sense to keep it generic like that. Instead, just do a mapping from
engine class to HW ID in the single place that is needed.
v2: use macros with the direct
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port() (rev2)
URL : https://patchwork.freedesktop.org/series/92874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373_full -> Patchwork_20682_full
From: John Harrison
In the case of a full GPU reset (e.g. because GuC has died or because
GuC's hang detection has been disabled), the driver can't rely on GuC
reporting the guilty context. Instead, the driver needs to scan all
active contexts and find one that is currently executing, as per the
From: John Harrison
Added the scheduling policy parameters to the 'guc_info' debugfs state
dump.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_a
From: John Harrison
Some testing environments and some heavier tests are slower than
previous limits allowed for. For example, it can take multiple seconds
for the 'context has been reset' notification handler to reach the
'kill the requests' code in the 'active' version of the 'reset
engines' te
From: John Harrison
Use the official driver default scheduling policies for configuring
the GuC scheduler rather than a bunch of hardcoded values.
v2:
(Matthew Brost)
- Move I915_ENGINE_WANT_FORCED_PREEMPTION to later patch
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed
From: Rahul Kumar Singh
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Signed-off-by: Matth
From: John Harrison
There are many ways in which the hangcheck selftest can fail. Very few
of them actually printed an error message to say what happened. So,
fill in the missing messages.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: Daniele Ceraolo
When using GuC submission, if a context gets banned disable scheduling
and mark all inflight requests as complete.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implemenation makes use of fence while there is likely simplier
options. A fence was choosen because of another feature coming soon
which requires a user to block on a context un
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fallback and this code path
is also required
From: John Harrison
Clear the 'disable resets' flag to allow GuC to reset hung contexts
(detected via pre-emption timeout).
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
1 file changed, 1 insertion
From: Daniele Ceraolo Spurio
Unblock GuC submission on Gen11+ platforms.
v2:
(Martin Peres / John H)
- Delete debug message when GuC is disabled by default on certain
platforms
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
Reviewed-
From: John Harrison
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Conversely, one of the tests specifically sends hanging batches to the
engines but wants
From: John Harrison
Changing the reset module parameter has no effect on a running GuC.
The corresponding entry in the ADS must be updated and then the GuC
informed via a Host2GuC message.
The new debugfs interface to module parameters allows this to happen.
However, connecting the parameter dat
From: John Harrison
It is impossible to seal all race conditions of resets occurring
concurrent to other operations. At least, not without introducing
excesive mutex locking. Instead, don't complain if it occurs. In
particular, don't complain if trying to send a H2G during a reset.
Whatever the H
Add disable GuC interrupts to intel_guc_sanitize(). Part of this
requires moving the guc_*_interrupt wrapper function into header file
intel_guc.h.
Signed-off-by: Matthew Brost
Cc: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 16 +++
GuC will notify the driver, via G2H, if it fails to
reset an engine. We recover by resorting to a full GPU
reset.
v2:
(John Harrison):
- s/drm_dbg/drm_err
Signed-off-by: Matthew Brost
Signed-off-by: Fernando Pacheco
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h
Requests may take slightly longer with GuC submission, let's increase
the timeouts in live_requests.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
With GuC virtual engines the physical engine which a request executes
and completes on isn't known to the i915. Therefore we can't attach a
request to a physical engines breadcrumbs. To work around this we create
a single breadcrumbs per engine class when using GuC submission and
direct all physica
Implement a simple static mapping algorithm of the i915 priority levels
(int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
follows:
i915 level < 0 -> GuC low level (3)
i915 level == 0 -> GuC normal level (2)
i915 level < INT_MAX-> GuC high level(1)
i9
GuC will issue a reset on detecting an engine hang and will notify
the driver via a G2H message. The driver will service the notification
by resetting the guilty context to a simple state or banning it
completely.
v2:
(John Harrison)
- Move msg[0] lookup after length check
v3:
(John Harrison)
From: "Signed-off-by: Rahul Kumar Singh"
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Sig
We receive notification of an engine reset from GuC at its
completion. Meaning GuC has potentially cleared any HW state
we may have been interested in capturing. GuC resumes scheduling
on the engine post-reset, as the resets are meant to be transparent,
further muddling our error state.
There is o
From: John Harrison
The media watchdog mechanism involves GuC doing a silent reset and
continue of the hung context. This requires the i915 driver provide a
golden context to GuC in the ADS.
v2:
(Matthew Brost):
- Fix memory corruption in shmem_read
(John H)
- Use locals rather than define
If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 63 +++
Update the bonding extension to return -ENODEV when using GuC submission
as this extension fundamentally will not work with the GuC submission
interface.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
1 file changed, 5 insertio
This is required to allow backend specific cleanup
v2:
(John H)
- Rework commit message
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_scheduler.c | 3 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 4 +---
drivers/gpu/drm/i915/i915_scheduler_
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to that of all the siblings.
v2: Update to work wit
Hold a reference to the intel_context over life of an i915_request.
Without this an i915_request can exist after the context has been
destroyed (e.g. request retired, context closed, but user space holds a
reference to the request from an out fence). In the case of GuC
submission + virtual engine,
Move active request tracking to a backend vfunc rather than assuming all
backends want to do this in the manner. In the of case execlists /
ring submission the tracking is on the physical engine while with GuC
submission it is on the context.
Signed-off-by: Matthew Brost
Reviewed-by: John Harriso
From: "Signed-off-by: John Harrison"
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
Unfortunately, the list must be dynamically allocated as its size is
variable. That means the driver must generate the list twice - once to
The new GuC interface introduces an MMIO H2G command,
INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This
MMIO tears down any active contexts generating a context reset G2H CTB
for each. Once that step completes the GuC tears down the CTB
channels. It is safe to suspend once thi
The GuC can implement execution qunatums, detect hung contexts and
other such things but it requires the timer expired interrupt to do so.
Signed-off-by: Matthew Brost
CC: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4
1 file changed, 4 insertions(+)
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given physical
engines. However, in GuC submission mode, the decomposition of virtual
to physical engines does not happen in i915. Instead, requests are
submitted to
The remaining patches for basic GuC submission [1]. Need 4 more RB and
CI results to get this merged.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/91840/
Daniele Ceraolo Spurio (1):
drm/i915/guc: Unblock GuC submission on Gen11+
John Harrison (11):
drm/i915/gu
Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
in intel_bios.c") moved the workaround for broken or missing VBT to
intel_bios.c. However is_port_valid() only protects the handling of
different skus of the same display version. Since in
intel_setup_outputs() we share the code
On Wed, 2021-07-21 at 15:30 +0200, Daniel Vetter wrote:
> It's not used. Drivers should instead use the helpers anyway.
>
> Currently both vbox and i915 hand-roll this and it's not the greatest.
> vbox looks buggy, and i915 does a bit much that helpers would take
> care of I think.
>
> Also impro
On Wed, 2021-07-21 at 15:30 +0200, Daniel Vetter wrote:
> We're trying to have a fairly strict split between core functionality
> that defines the uapi, including the docs, and the helper functions to
> implement it.
>
> Move drm_plane_enable_fb_damage_clips and associated kerneldoc into
> drm_pla
On Wed, 2021-07-21 at 15:30 +0200, Daniel Vetter wrote:
> There's two stages of manual upload/invalidate displays:
> - just handling dirtyfb and uploading the entire fb all the time
> - looking at damage clips
>
> In the latter case we support it through fbdev emulation (with
> fb_defio), atomic p
On Thu, Jul 22, 2021 at 02:50:24PM -0700, Daniele Ceraolo Spurio wrote:
>
>
>
> > > > @@ -1756,15 +1796,119 @@ static int guc_context_alloc(struct
> > > > intel_context *ce)
> > > > return lrc_alloc(ce, ce->engine);
> > > >}
> > > > +static void guc_context_set_prio(struct intel_guc
@@ -1756,15 +1796,119 @@ static int guc_context_alloc(struct intel_context *ce)
return lrc_alloc(ce, ce->engine);
}
+static void guc_context_set_prio(struct intel_guc *guc,
+struct intel_context *ce,
+u8 prio)
+{
+
On Thu, Jul 22, 2021 at 03:09:13PM -, Patchwork wrote:
>Patch Details
>
>Series: drm/i915/bios: Fix ports mask (rev2)
>URL: [1]https://patchwork.freedesktop.org/series/92850/
>State: failure
>Details:
>[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/i
On Thu, Jul 22, 2021 at 01:26:30PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/16/2021 1:17 PM, Matthew Brost wrote:
> > Implement a simple static mapping algorithm of the i915 priority levels
> > (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
> > follows:
> >
> > i915 l
== Series Details ==
Series: drm/i915: Extend Wa_1406941453 to adl-p
URL : https://patchwork.freedesktop.org/series/92905/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373 -> Patchwork_20684
Summary
---
**SUCCESS*
== Series Details ==
Series: drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
URL : https://patchwork.freedesktop.org/series/92902/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10373 -> Patchwork_20683
On 7/16/2021 1:17 PM, Matthew Brost wrote:
Implement a simple static mapping algorithm of the i915 priority levels
(int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
follows:
i915 level < 0 -> GuC low level (3)
i915 level == 0 -> GuC normal level (2)
i91
On Thu, Jul 22, 2021 at 12:20:41PM -0700, José Roberto de Souza wrote:
> Workaround also needed for alderlake-P.
>
> HSDES: 14010801662
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Marked incorrectly in the workaround database, but based on the notes
there, it is indeed needed for AD
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port() (rev2)
URL : https://patchwork.freedesktop.org/series/92874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10373 -> Patchwork_20682
==
On Thu, Jul 22, 2021 at 12:56:56PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/16/2021 1:17 PM, Matthew Brost wrote:
> > This adds GuC backend support for i915_request_cancel(), which in turn
> > makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
>
> This needs a bit of explanation on why we're usi
On 7/16/2021 1:17 PM, Matthew Brost wrote:
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This needs a bit of explanation on why we're using fences for this
instead of other simpler options.
Signed-off-by: Matthew Brost
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port() (rev2)
URL : https://patchwork.freedesktop.org/series/92874/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each c
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port() (rev2)
URL : https://patchwork.freedesktop.org/series/92874/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2895a0aeaa5c drm/i915/bios: Allow DSI ports to b
Thanks for the feedback!
On Tue, Jul 20, 2021 at 9:29 AM Daniel Vetter wrote:
>
> On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > drm's debug system uses distinct categories of debug messages, encoded
> > in an enum (DRM_UT_), which are mapped to bits in drm.debug.
> > drm_debug_
On 7/22/21 5:29 AM, Desmond Cheong Zhi Xi wrote:
drm_file.master should be protected by either drm_device.master_mutex
or drm_file.master_lookup_lock when being dereferenced. However,
drm_master_get is called on unprotected file_priv->master pointers in
vmw_surface_define_ioctl and vmw_gb_surface
Workaround also needed for alderlake-P.
HSDES: 14010801662
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i
On Thu, Jul 22, 2021 at 10:15:35AM -0700, Lucas De Marchi wrote:
> Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
> in intel_bios.c") moved the workaround for broken or missing VBT to
> intel_bios.c. However is_port_valid() only protects the handling of
> different skus of t
On Thu, Jul 22, 2021 at 6:00 PM Boqun Feng wrote:
>
> On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
> > > Inside drm_is_current_master, using the outer drm_device.master_mutex
> > > to protect reads of drm_
Hi
Am 13.07.21 um 22:51 schrieb Daniel Vetter:
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a
Hi
Am 13.07.21 um 22:51 schrieb Daniel Vetter:
intel-gfx-ci realized that something is not quite coherent anymore on
some platforms for our i915+vgem tests, when I tried to switch vgem
over to shmem helpers.
After lots of head-scratching I realized that I've removed calls to
drm_clflush. And we
Hi,
I'm not knowledgeable enougth to give this a full review. If you can
just answer my questions, fell free to add an
Acked-by: Thomas Zimmermann
to the patch. :)
Am 13.07.21 um 22:51 schrieb Daniel Vetter:
We want to stop gup, which isn't the case if we use vmf_insert_page
What is gup?
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:217:5: warning: symbol
'slpc_decode_min_freq' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:229:5: warning: symbol
'slpc_decode_max_freq' was not declared. Should it be static?
Reported-by: kernel test robot
Signed
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210722]
[If your patch is applied to the wrong git tree
On Thu, Jul 22, 2021 at 02:07:51PM +0100, Christoph Hellwig wrote:
> On Thu, Jul 22, 2021 at 10:00:40AM -0300, Jason Gunthorpe wrote:
> > this is better:
> >
> >struct sg_append_table state;
> >
> >sg_append_init(&state, sgt, gfp_mask);
> >
> >while (..)
> > ret = sg_append_page
Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
in intel_bios.c") moved the workaround for broken or missing VBT to
intel_bios.c. However is_port_valid() only protects the handling of
different skus of the same display version. Since in
intel_setup_outputs() we share the code
On Sun, Jul 18, 2021 at 02:09:12PM +0300, Leon Romanovsky wrote:
> @@ -386,12 +414,14 @@ static struct scatterlist *get_next_sg(struct sg_table
> *table,
> return ERR_PTR(-ENOMEM);
> sg_init_table(new_sg, alloc_size);
> if (cur) {
> + if (total_nents)
> +
== Series Details ==
Series: drm/i915/bios: Fix ports mask (rev3)
URL : https://patchwork.freedesktop.org/series/92850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10371 -> Patchwork_20681
Summary
---
**FAILURE**
On Thu, Jul 22, 2021 at 07:47:21AM +, Patchwork wrote:
> == Series Details ==
>
> Series: CI pass for reviewed Xe_HP SDV and DG2 patches
> URL : https://patchwork.freedesktop.org/series/92853/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_
On Thu, Jul 22, 2021 at 09:03:45AM -0700, Lucas De Marchi wrote:
> On Thu, Jul 22, 2021 at 08:20:34AM +0100, Christoph Hellwig wrote:
> > On Thu, Jul 22, 2021 at 01:55:23AM -0400, Lucas De Marchi wrote:
> > > humn... PORT_F. KBL doesn't have PORT_F. We decided to keep the handling
> > > of DISPLAY_
On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
> On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
> > Inside drm_is_current_master, using the outer drm_device.master_mutex
> > to protect reads of drm_file.master makes the function prone to creating
> > lock hie
On Thu, Jul 22, 2021 at 08:20:34AM +0100, Christoph Hellwig wrote:
On Thu, Jul 22, 2021 at 01:55:23AM -0400, Lucas De Marchi wrote:
humn... PORT_F. KBL doesn't have PORT_F. We decided to keep the handling
of DISPLAY_VER == 10 and DISPLAY_VER == 9 together and trust the VBT,
but when the VBT is n
On Thu, Jul 22, 2021 at 09:57:00AM +0200, Michal Wajdeczko wrote:
>
>
> On 22.07.2021 01:51, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 7/19/2021 9:04 PM, Matthew Brost wrote:
> >> On Mon, Jul 19, 2021 at 05:51:46PM -0700, Daniele Ceraolo Spurio wrote:
> >>>
> >>> On 7/16/2021 1:16 PM, Matthe
== Series Details ==
Series: drm/i915/bios: Fix ports mask (rev2)
URL : https://patchwork.freedesktop.org/series/92850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10371 -> Patchwork_20680
Summary
---
**FAILURE**
On Tue, Jul 20 2021, Jason Gunthorpe wrote:
> Platform simply wants to run some code when the device is first
> opened/last closed. Use the core framework and locking for this. Aside
> from removing a bit of code this narrows the locking scope from a global
> lock.
>
> Signed-off-by: Yishai Hada
On Tue, Jul 20 2021, Jason Gunthorpe wrote:
> Currently the driver ops have an open/release pair that is called once
> each time a device FD is opened or closed. Add an additional set of
> open/close_device() ops which are called when the device FD is opened for
> the first time and closed for th
== Series Details ==
Series: drm, drm/vmwgfx: fixes and updates related to drm_master
URL : https://patchwork.freedesktop.org/series/92894/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10371 -> Patchwork_20678
Summary
== Series Details ==
Series: SG fix together with update to RDMA umem (rev2)
URL : https://patchwork.freedesktop.org/series/92682/
State : failure
== Summary ==
Applying: lib/scatterlist: Fix wrong update of orig_nents
error: sha1 information is lacking or useless
(drivers/gpu/drm/i915/gem/i9
== Series Details ==
Series: MIPI DSI driver enhancements (rev2)
URL : https://patchwork.freedesktop.org/series/92695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10369_full -> Patchwork_20676_full
Summary
---
**SU
On Thu, Jul 22, 2021 at 3:03 PM Desmond Cheong Zhi Xi
wrote:
>
> On 22/7/21 6:35 pm, Daniel Vetter wrote:
> > On Thu, Jul 22, 2021 at 05:29:28PM +0800, Desmond Cheong Zhi Xi wrote:
> >> In particular, we make it clear that &drm_device.mode_config.idr_mutex
> >> protects the lease idr and list stru
1 - 100 of 163 matches
Mail list logo
