[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix wm params for ccs (rev4)

== Series Details == Series: drm/i915: Fix wm params for ccs (rev4) URL : https://patchwork.freedesktop.org/series/92491/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10346_full -> Patchwork_20631_full Summary --- *

[Intel-gfx] ✓ Fi.CI.BAT: success for More workaround updates

== Series Details == Series: More workaround updates URL : https://patchwork.freedesktop.org/series/92669/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20640 Summary --- **SUCCESS** No regressi

[Intel-gfx] ✗ Fi.CI.DOCS: warning for More workaround updates

== Series Details == Series: More workaround updates URL : https://patchwork.freedesktop.org/series/92669/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' description

[Intel-gfx] [PATCH 4/7] drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping

Extend the workaround bound to include A1 display. Bspec: 54370 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_device_info.c | 4 ++-- drivers/gpu/drm/i915/intel_step.h| 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c

[Intel-gfx] [PATCH 2/7] drm/i915/icl: Drop a couple unnecessary workarounds

While doing a quick sanity check of the ICL workarounds in the driver I noticed a few things that should be updated: * There's no mention in the bspec that WaPipelineFlushCoherentLines is needed on gen11 (both the current WA database and the old, deprecated page 20196 were checked); it appe

[Intel-gfx] [PATCH 0/7] More workaround updates

The first six patches are just general maintenance of workarounds for various platforms. The final patch switches the way we match ranges of steppings in the driver from an inclusive upper bound to an exclusive upper bound; this matches how workarounds are defined in our specs and should help redu

[Intel-gfx] [PATCH 1/7] drm/i915: Fix application of WaInPlaceDecompressionHang

On SKL we've been applying this workaround on H0+ steppings, which is actually backwards; H0 is supposed to be the first stepping where the workaround is no longer needed. Flip the bounds so that the workaround applies to all steppings _before_ H0. On BXT we've been applying this workaround to al

[Intel-gfx] [PATCH 5/7] drm/i915/rkl: Wa_1409767108 also applies to RKL

Bspec: 53273 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 64be896bcd8b..e3aaf967

[Intel-gfx] [PATCH 3/7] drm/i915: Program DFR enable/disable as a GT workaround

DFR programming (which we enable as an optimization on gen11, but must ensure is disabled on gen12) should be handled as a GT workaround rather than clock gating initialization. This will ensure that the programming of these registers is verified with our typical workaround checks. Signed-off-by:

[Intel-gfx] [PATCH 6/7] drm/i915/rkl: Wa_1408330847 no longer applies to RKL

RKL doesn't have PSR2 support, so PSR2-related workarounds no longer apply. Bspec: 53273 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_psr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/d

[Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive

Workarounds are documented in the bspec with an exclusive upper bound (i.e., a "fixed" stepping that no longer needs the workaround). This makes our driver's use of an inclusive upper bound for stepping ranges confusing; the differing notation between code and bspec makes it very easy for mistakes

Re: [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC

On Sat, Jul 10, 2021 at 03:55:02AM +, Matthew Brost wrote: > On Fri, Jul 09, 2021 at 05:16:34PM -0700, John Harrison wrote: > > On 6/24/2021 00:04, Matthew Brost wrote: > > > When running the GuC the GPU can't be considered idle if the GuC still > > > has contexts pinned. As such, a call has be

[Intel-gfx] ✗ Fi.CI.IGT: failure for drivers/gpu/drm/i915/display: remove boilerplate code using LOCK_ALL macros

== Series Details == Series: drivers/gpu/drm/i915/display: remove boilerplate code using LOCK_ALL macros URL : https://patchwork.freedesktop.org/series/92596/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20630_full

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms

== Series Details == Series: series starting with [1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms URL : https://patchwork.freedesktop.org/series/92667/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20639

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms

== Series Details == Series: series starting with [1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms URL : https://patchwork.freedesktop.org/series/92667/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parse

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Call i915_globals_exit() after i915_pmu_exit()

== Series Details == Series: series starting with [1/2] drm/i915: Call i915_globals_exit() after i915_pmu_exit() URL : https://patchwork.freedesktop.org/series/92663/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20638 ==

[Intel-gfx] ✗ Fi.CI.IGT: failure for Some DG1 uAPI cleanup

== Series Details == Series: Some DG1 uAPI cleanup URL : https://patchwork.freedesktop.org/series/92581/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20628_full Summary --- **FAILURE** Ser

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: Call i915_globals_exit() after i915_pmu_exit()

== Series Details == Series: series starting with [1/2] drm/i915: Call i915_globals_exit() after i915_pmu_exit() URL : https://patchwork.freedesktop.org/series/92663/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warn

[Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3)

== Series Details == Series: GuC submission support (rev3) URL : https://patchwork.freedesktop.org/series/91840/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h LD [M] drivers/gp

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Migrate memory to SMEM when imported cross-device (rev2)

== Series Details == Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev2) URL : https://patchwork.freedesktop.org/series/92617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20636 Su

[Intel-gfx] [PATCH 2/4] drm/i915/display/psr2: Mark as updated all planes that intersect with pipe_clip

Without this planes that were added by intel_psr2_sel_fetch_update() that intersect with pipe damaged area will not have skl_program_plane() and intel_psr2_program_plane_sel_fetch() called, causing panel to not be properly updated. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- dr

[Intel-gfx] [PATCH 1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms

xelpd platforms also requires that FBC is disabled when PSR2 is enabled so extending it. BSpec: 50422 Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 3/4] drm/i915/display/psr2: Fix cursor updates using legacy apis

The fast path only updates cursor register what will not cause any updates in the screen when using PSR2 selective fetch. The only option that we have is to go trough the slow patch that will do full atomic commit, that will trigger the PSR2 selective fetch compute and programing calls. Without t

[Intel-gfx] [PATCH 4/4] drm/i915/display/psr2: Force a PSR exit in the frontbuffer modification flushes

The CURSURFLIVE() write do not works with PSR2 selective fetch, the only way to update screen is to program PSR2 plane and transcoder registers during the vblank. We could use the frontbuffer dirty areas set by userspace with drmModeDirtyFB() but we would still need to wait for the vblank to prope

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up DPLL stuff

== Series Details == Series: drm/i915: Clean up DPLL stuff URL : https://patchwork.freedesktop.org/series/92577/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20627_full Summary --- **FAILURE*

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Migrate memory to SMEM when imported cross-device (rev2)

== Series Details == Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev2) URL : https://patchwork.freedesktop.org/series/92617/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess functi

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Migrate memory to SMEM when imported cross-device (rev2)

== Series Details == Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev2) URL : https://patchwork.freedesktop.org/series/92617/ State : warning == Summary == $ dim checkpatch origin/drm-tip a518ef415105 drm/i915/gem: Check object_can_migrate from object_migrate bc470df2a6

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Convert from atomic_t to refcount_t on intel_vgpu_ppgtt_spt->refcount

== Series Details == Series: drm/i915/gvt: Convert from atomic_t to refcount_t on intel_vgpu_ppgtt_spt->refcount URL : https://patchwork.freedesktop.org/series/92648/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20635 ==

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gvt: Convert from atomic_t to refcount_t on intel_vgpu_ppgtt_spt->refcount

== Series Details == Series: drm/i915/gvt: Convert from atomic_t to refcount_t on intel_vgpu_ppgtt_spt->refcount URL : https://patchwork.freedesktop.org/series/92648/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warn

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix error return code in igt_vma_create()

== Series Details == Series: drm/i915: Fix error return code in igt_vma_create() URL : https://patchwork.freedesktop.org/series/92646/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20634 Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for Per client GPU stats (rev2)

== Series Details == Series: Per client GPU stats (rev2) URL : https://patchwork.freedesktop.org/series/92574/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20626_full Summary --- **FAILURE**

Re: [Intel-gfx] [PATCH 46/51] drm/i915/selftest: Fix MOCS selftest for GuC submission

On Fri, Jul 16, 2021 at 01:17:19PM -0700, Matthew Brost wrote: > From: Rahul Kumar Singh > > When GuC submission is enabled, the GuC controls engine resets. Rather > than explicitly triggering a reset, the driver must submit a hanging > context to GuC and wait for the reset to occur. > > Signed-

Re: [Intel-gfx] [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission

On Fri, Jul 16, 2021 at 01:17:21PM -0700, Matthew Brost wrote: > From: John Harrison > > When GuC submission is enabled, the GuC controls engine resets. Rather > than explicitly triggering a reset, the driver must submit a hanging > context to GuC and wait for the reset to occur. > > Conversely,

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix error return code in igt_vma_create()

== Series Details == Series: drm/i915: Fix error return code in igt_vma_create() URL : https://patchwork.freedesktop.org/series/92646/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter '

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE

== Series Details == Series: series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE URL : https://patchwork.freedesktop.org/series/92632/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20633 Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/step: Add macro magic for handling steps (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/step: Add macro magic for handling steps (rev2) URL : https://patchwork.freedesktop.org/series/92560/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20625_full

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE

== Series Details == Series: series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE URL : https://patchwork.freedesktop.org/series/92632/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function pa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE

== Series Details == Series: series starting with [1/7] vgaarb: remove VGA_DEFAULT_DEVICE URL : https://patchwork.freedesktop.org/series/92632/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1354bf88b4ee vgaarb: remove VGA_DEFAULT_DEVICE ddb8e5b71998 vgaarb: remove vga_conflicts

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Make modeset locking easier

== Series Details == Series: drm: Make modeset locking easier URL : https://patchwork.freedesktop.org/series/92606/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20632 Summary --- **SUCCESS** No

[Intel-gfx] [PATCH 2/2] drm/i915: Tear down properly on early i915_init exit

In i915_exit(), we check i915_pci_driver.driver.owner to detect if i915_init exited early and don't tear anything down. However, we didn't have proper tear-down paths for early exits in i915_init(). Most of the time, you would never notice this as driver init failures are extremely rare and gener

[Intel-gfx] [PATCH 1/2] drm/i915: Call i915_globals_exit() after i915_pmu_exit()

We should tear down in the opposite order we set up. Signed-off-by: Jason Ekstrand Fixes: 537f9c84a427 ("drm/i915/pmu: Fix CPU hotplug with multiple GPUs") Cc: Daniel Vetter --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: Make modeset locking easier

== Series Details == Series: drm: Make modeset locking easier URL : https://patchwork.freedesktop.org/series/92606/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' des

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Make modeset locking easier

== Series Details == Series: drm: Make modeset locking easier URL : https://patchwork.freedesktop.org/series/92606/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../

Re: [Intel-gfx] [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck

On Fri, Jul 16, 2021 at 01:17:22PM -0700, Matthew Brost wrote: > From: John Harrison > > Some testing environments and some heavier tests are slower than > previous limits allowed for. For example, it can take multiple seconds > for the 'context has been reset' notification handler to reach the >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Make modeset locking easier

== Series Details == Series: drm: Make modeset locking easier URL : https://patchwork.freedesktop.org/series/92606/ State : warning == Summary == $ dim checkpatch origin/drm-tip b1e190e95142 drm: Introduce drm_modeset_lock_ctx_retry() -:104: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ctx' -

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wm params for ccs (rev4)

== Series Details == Series: drm/i915: Fix wm params for ccs (rev4) URL : https://patchwork.freedesktop.org/series/92491/ State : success == Summary == CI Bug Log - changes from CI_DRM_10346 -> Patchwork_20631 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.IGT: failure for Provide core infrastructure for managing open/release (rev2)

== Series Details == Series: Provide core infrastructure for managing open/release (rev2) URL : https://patchwork.freedesktop.org/series/92556/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20624_full

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix wm params for ccs (rev4)

== Series Details == Series: drm/i915: Fix wm params for ccs (rev4) URL : https://patchwork.freedesktop.org/series/92491/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelis

Re: [Intel-gfx] [PATCH v2 43/50] drm/i915/dg2: Add vswing programming for SNPS phys

On Tue, Jul 13, 2021 at 08:15:33PM -0700, Matt Roper wrote: > Vswing programming for SNPS PHYs is just a single step -- look up the > value that corresponds to the voltage level from a table and program it > into the SNPS_PHY_TX_EQ register. > > Bspec: 53920 > Cc: Matt Atwood > Signed-off-by: Mat

Re: [Intel-gfx] [PATCH v2 42/50] drm/i915/dg2: Add MPLLB programming for HDMI

On Tue, Jul 13, 2021 at 08:15:32PM -0700, Matt Roper wrote: > At the moment we don't have a proper algorithm that can be used to > calculate PHY settings for arbitrary HDMI link rates. The PHY tables > here should support the regular modes of real-world HDMI monitors. > > Bspec: 54032 > Cc: Matt

Re: [Intel-gfx] [PATCH v2 46/50] drm/i915/dg2: Wait for SNPS PHY calibration during display init

On Tue, Jul 13, 2021 at 08:15:36PM -0700, Matt Roper wrote: > Initialization of the PHY is handled by the hardware/firmware, but the > driver should wait up to 25ms for the PHY to report that its calibration > has completed. > > Bspec: 49189 > Bspec: 50107 > Cc: Matt Atwood > Signed-off-by: Matt

Re: [Intel-gfx] [PATCH v2 45/50] drm/i915/dg2: Classify DG2 PHY types

On Tue, Jul 13, 2021 at 08:15:35PM -0700, Matt Roper wrote: > Although the bspec labels four of DG2's outputs as "combo PHY," the > underlying PHYs in both cases are actually Synopsys PHYs that are > programmed completely differently than the traditional Intel "combo" PHY > units. As such, we don'

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Fix shared dpll mismatch for bigjoiner slave (rev3)

== Series Details == Series: drm/i915/display: Fix shared dpll mismatch for bigjoiner slave (rev3) URL : https://patchwork.freedesktop.org/series/91830/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10345_full -> Patchwork_20623_full ===

Re: [Intel-gfx] [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest

On Fri, Jul 16, 2021 at 01:17:17PM -0700, Matthew Brost wrote: > From: John Harrison > > There are many ways in which the hangcheck selftest can fail. Very few > of them actually printed an error message to say what happened. So, > fill in the missing messages. > > Signed-off-by: John Harrison

Re: [Intel-gfx] [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags

On Fri, Jul 16, 2021 at 01:17:12PM -0700, Matthew Brost wrote: > From: John Harrison > > Changing the reset module parameter has no effect on a running GuC. > The corresponding entry in the ADS must be updated and then the GuC > informed via a Host2GuC message. > > The new debugfs interface to m

[Intel-gfx] ✓ Fi.CI.BAT: success for drivers/gpu/drm/i915/display: remove boilerplate code using LOCK_ALL macros

== Series Details == Series: drivers/gpu/drm/i915/display: remove boilerplate code using LOCK_ALL macros URL : https://patchwork.freedesktop.org/series/92596/ State : success == Summary == CI Bug Log - changes from CI_DRM_10345 -> Patchwork_20630 ==

[Intel-gfx] [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission

From: Rahul Kumar Singh When GuC submission is enabled, the GuC controls engine resets. Rather than explicitly triggering a reset, the driver must submit a hanging context to GuC and wait for the reset to occur. Signed-off-by: Rahul Kumar Singh Signed-off-by: John Harrison Signed-off-by: Matth

[Intel-gfx] [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+

From: Daniele Ceraolo Spurio Unblock GuC submission on Gen11+ platforms. v2: (Martin Peres / John H) - Delete debug message when GuC is disabled by default on certain platforms Signed-off-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Matthew Brost Reviewed-

[Intel-gfx] [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest

From: John Harrison There are many ways in which the hangcheck selftest can fail. Very few of them actually printed an error message to say what happened. So, fill in the missing messages. Signed-off-by: John Harrison Signed-off-by: Matthew Brost Cc: Daniele Ceraolo Spurio --- drivers/gpu/dr

[Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX-> GuC high level(1) i9

[Intel-gfx] [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests

Requests may take slightly longer with GuC submission, let's increase the timeouts in live_requests. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.

[Intel-gfx] [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags

From: John Harrison Changing the reset module parameter has no effect on a running GuC. The corresponding entry in the ADS must be updated and then the GuC informed via a Host2GuC message. The new debugfs interface to module parameters allows this to happen. However, connecting the parameter dat

[Intel-gfx] [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck

From: John Harrison Some testing environments and some heavier tests are slower than previous limits allowed for. For example, it can take multiple seconds for the 'context has been reset' notification handler to reach the 'kill the requests' code in the 'active' version of the 'reset engines' te

[Intel-gfx] [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission

From: John Harrison When GuC submission is enabled, the GuC controls engine resets. Rather than explicitly triggering a reset, the driver must submit a hanging context to GuC and wait for the reset to occur. Conversely, one of the tests specifically sends hanging batches to the engines but wants

[Intel-gfx] [PATCH 43/51] drm/i915/guc: Support request cancellation

This adds GuC backend support for i915_request_cancel(), which in turn makes CONFIG_DRM_I915_REQUEST_TIMEOUT work. Signed-off-by: Matthew Brost Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_context.c | 9 + drivers/gpu/drm/i915/gt/intel_context.h | 7 + drivers/gpu/drm/i9

[Intel-gfx] [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC

From: John Harrison In the case of a full GPU reset (e.g. because GuC has died or because GuC's hang detection has been disabled), the driver can't rely on GuC reporting the guilty context. Instead, the driver needs to scan all active contexts and find one that is currently executing, as per the

[Intel-gfx] [PATCH 46/51] drm/i915/selftest: Fix MOCS selftest for GuC submission

From: Rahul Kumar Singh When GuC submission is enabled, the GuC controls engine resets. Rather than explicitly triggering a reset, the driver must submit a hanging context to GuC and wait for the reset to occur. Signed-off-by: Rahul Kumar Singh Signed-off-by: John Harrison Signed-off-by: Matth

[Intel-gfx] [PATCH 20/51] drm/i915: Track 'serial' counts for virtual engines

From: John Harrison The serial number tracking of engines happens at the backend of request submission and was expecting to only be given physical engines. However, in GuC submission mode, the decomposition of virtual to physical engines does not happen in i915. Instead, requests are submitted to

[Intel-gfx] [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission

Update the bonding extension to return -ENODEV when using GuC submission as this extension fundamentally will not work with the GuC submission interface. Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 + 1 file changed, 5 insertio

[Intel-gfx] [PATCH 35/51] drm/i915/guc: Enable GuC engine reset

From: John Harrison Clear the 'disable resets' flag to allow GuC to reset hung contexts (detected via pre-emption timeout). Signed-off-by: John Harrison Signed-off-by: Matthew Brost Reviewed-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-- 1 file changed, 1 insertion

[Intel-gfx] [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification

GuC will notify the driver, via G2H, if it fails to reset an engine. We recover by resorting to a full GPU reset. Signed-off-by: Matthew Brost Signed-off-by: Fernando Pacheco Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + drivers/gpu/drm/i915/gt/uc/intel_g

[Intel-gfx] [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize

Add disable GuC interrupts to intel_guc_sanitize(). Part of this requires moving the guc_*_interrupt wrapper function into header file intel_guc.h. Signed-off-by: Matthew Brost Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 16 drivers/gpu/drm/i915/gt/u

[Intel-gfx] [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface

Reset implementation for new GuC interface. This is the legacy reset implementation which is called when the i915 owns the engine hang check. Future patches will offload the engine hang check to GuC but we will continue to maintain this legacy path as a fallback and this code path is also required

[Intel-gfx] [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset

From: John Harrison The driver must provide GuC with a list of mmio registers that should be saved/restored during a GuC-based engine reset. Unfortunately, the list must be dynamically allocated as its size is variable. That means the driver must generate the list twice - once to work out the siz

[Intel-gfx] [PATCH 36/51] drm/i915/guc: Capture error state on context reset

We receive notification of an engine reset from GuC at its completion. Meaning GuC has potentially cleared any HW state we may have been interested in capturing. GuC resumes scheduling on the engine post-reset, as the resets are meant to be transparent, further muddling our error state. There is o

[Intel-gfx] [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc

This help the backends clean up when the schedule engine object gets destroyed. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/i915_scheduler.c | 3 ++- drivers/gpu/drm/i915/i915_scheduler.h | 4 +--- drivers/gpu/drm/i915/i915_scheduler_types.h | 5 + 3 files changed, 8 in

[Intel-gfx] [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission

When using GuC submission, if a context gets banned disable scheduling and mark all inflight requests as complete. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_context.h | 13 ++ drivers/gpu/drm/i

[Intel-gfx] [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS

From: John Harrison The media watchdog mechanism involves GuC doing a silent reset and continue of the hung context. This requires the i915 driver provide a golden context to GuC in the ADS. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_gt.c

[Intel-gfx] [PATCH 30/51] drm/i915/guc: Handle context reset notification

GuC will issue a reset on detecting an engine hang and will notify the driver via a G2H message. The driver will service the notification by resetting the guilty context to a simple state or banning it completely. v2: (John Harrison) - Move msg[0] lookup after length check Cc: Matthew Brost C

[Intel-gfx] [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled

If submission is disabled by the backend for any reason, reset the GPU immediately in the heartbeat code as the backend can't be reenabled until the GPU is reset. Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 63 +++

[Intel-gfx] [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump

From: John Harrison Added the scheduling policy parameters to the 'guc_info' debugfs state dump. Signed-off-by: John Harrison Signed-off-by: Matthew Brost Reviewed-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_a

[Intel-gfx] [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up

From: John Harrison Use the official driver default scheduling policies for configuring the GuC scheduler rather than a bunch of hardcoded values. v2: (Matthew Brost) - Move I915_ENGINE_WANT_FORCED_PREEMPTION to later patch Signed-off-by: John Harrison Signed-off-by: Matthew Brost Reviewed

[Intel-gfx] [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request

Hold a reference to the intel_context over life of an i915_request. Without this an i915_request can exist after the context has been destroyed (e.g. request retired, context closed, but user space holds a reference to the request from an out fence). In the case of GuC submission + virtual engine,

[Intel-gfx] [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface

The new GuC interface introduces an MMIO H2G command, INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This MMIO tears down any active contexts generating a context reset G2H CTB for each. Once that step completes the GuC tears down the CTB channels. It is safe to suspend once thi

[Intel-gfx] [PATCH 34/51] drm/i915/guc: Don't complain about reset races

From: John Harrison It is impossible to seal all race conditions of resets occurring concurrent to other operations. At least, not without introducing excesive mutex locking. Instead, don't complain if it occurs. In particular, don't complain if trying to send a H2G during a reset. Whatever the H

[Intel-gfx] [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC

Add bypass tasklet submission path to GuC. The tasklet is only used if H2G channel has backpresure. Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++ 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/

[Intel-gfx] [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC

The GuC can implement execution qunatums, detect hung contexts and other such things but it requires the timer expired interrupt to do so. Signed-off-by: Matthew Brost CC: John Harrison Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/intel_rps.c | 4 1 file changed, 4 insertions(+)

[Intel-gfx] [PATCH 25/51] drm/i915: Move active request tracking to a vfunc

Move active request tracking to a backend vfunc rather than assuming all backends want to do this in the maner. In the case execlists / ring submission the tracking is on the physical engine while with GuC submission it is on the context. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/

[Intel-gfx] [PATCH 19/51] drm/i915/guc: GuC virtual engines

Implement GuC virtual engines. Rather simple implementation, basically just allocate an engine, setup context enter / exit function to virtual engine specific functions, set all other variables / functions to guc versions, and set the engine mask to that of all the siblings. v2: Update to work wit

[Intel-gfx] [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs

With GuC virtual engines the physical engine which a request executes and completes on isn't known to the i915. Therefore we can't attach a request to a physical engines breadcrumbs. To work around this we create a single breadcrumbs per engine class when using GuC submission and direct all physica

[Intel-gfx] [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling

Semaphores are an optimization and not required for basic GuC submission to work properly. Disable until we have time to do the implementation to enable semaphores and tune them for performance. Also long direction is just to delete semaphores from the i915 so another reason to not enable these for

[Intel-gfx] [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface

Implement GuC context operations which includes GuC specific operations alloc, pin, unpin, and destroy. v2: (Daniel Vetter) - Use msleep_interruptible rather than cond_resched in busy loop (Michal) - Remove C++ style comment Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- d

[Intel-gfx] [PATCH 17/51] drm/i915/guc: Add several request trace points

Add trace points for request dependencies and GuC submit. Extended existing request trace points to include submit fence value,, guc_id, and ring tail value. v2: Fix white space alignment in i915_request_add trace point Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison

[Intel-gfx] [PATCH 18/51] drm/i915: Add intel_context tracing

Add intel_context tracing. These trace points are particular helpful when debugging the GuC firmware and can be enabled via CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option. Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/intel_co

[Intel-gfx] [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer

Ensure G2H response has space in the buffer before sending H2G CTB as the GuC can't handle any backpressure on the G2H interface. v2: (Matthew) - s/INTEL_GUC_SEND/INTEL_GUC_CT_SEND v3: (Matthew) - Add G2H credit accounting to blocking path, add g2h_release_space helper (John H) - CTB_

[Intel-gfx] [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC

When running the GuC the GPU can't be considered idle if the GuC still has contexts pinned. As such, a call has been added in intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for the number of unpinned contexts to go to zero. v2: rtimeout -> remaining_timeout v3: Drop unnecessa

[Intel-gfx] [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC

Update GuC debugfs to support the new GuC structures. v2: (John Harrison) - Remove intel_lrc_reg.h include from i915_debugfs.c (Michal) - Rename GuC debugfs functions Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 22

[Intel-gfx] [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling

Disable preempt busywait when using GuC scheduling. This isn't needed as the GuC controls preemption when scheduling. v2: (John H): - Fix commit message Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 -- 1 file

[Intel-gfx] [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences

If two requests are on the same ring, they are explicitly ordered by the HW. So, a submission fence is sufficient to ensure ordering when using the new GuC submission interface. Conversely, if two requests share a timeline and are on the same physical engine but different context this doesn't ensur

[Intel-gfx] [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable

Extend the deregistration context fence to fence whne a GuC context has scheduling disable pending. v2: (John H) - Update comment why we check the pin count within spin lock Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- .../gpu/drm/i915/gt/uc/intel_guc_submi

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