Am 25.06.21 um 10:22 schrieb Thomas Zimmermann:
The field drm_device.irq_enabled is only used by legacy drivers
with userspace modesetting. Don't set it in armada.
Signed-off-by: Thomas Zimmermann
R-b'ed by Laurent via IRC
---
drivers/gpu/drm/armada/armada_drv.c | 2 --
1 file changed,
== Series Details ==
Series: CT changes required for GuC submission
URL : https://patchwork.freedesktop.org/series/91943/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10282_full -> Patchwork_20474_full
Summary
---
*
== Series Details ==
Series: CT changes required for GuC submission
URL : https://patchwork.freedesktop.org/series/91943/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10282 -> Patchwork_20474
Summary
---
**SUCCESS**
== Series Details ==
Series: CT changes required for GuC submission
URL : https://patchwork.freedesktop.org/series/91943/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/dis
== Series Details ==
Series: CT changes required for GuC submission
URL : https://patchwork.freedesktop.org/series/91943/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4de6bd659c01 drm/i915/guc: Relax CTB response timeout
9074da160af0 drm/i915/guc: Improve error message for uns
Improve the error message when a unsolicited CT response is received by
printing fence that couldn't be found, the last fence, and all requests
with a response outstanding.
Signed-off-by: Matthew Brost
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 10 +++---
Implement a stall timer which fails H2G CTBs once a period of time
with no forward progress is reached to prevent deadlock.
v2:
(Michal)
- Improve error message in ct_deadlock()
- Set broken when ct_deadlock() returns true
- Return -EPIPE on ct_deadlock()
Signed-off-by: John Harrison
Sign
Add non blocking CTB send function, intel_guc_send_nb. GuC submission
will send CTBs in the critical path and does not need to wait for these
CTBs to complete before moving on, hence the need for this new function.
The non-blocking CTB now must have a flow control mechanism to ensure
the buffer is
CTB writes are now in the path of command submission and should be
optimized for performance. Rather than reading CTB descriptor values
(e.g. head, tail) which could result in accesses across the PCIe bus,
store shadow local copies and only read/write the descriptor values when
absolutely necessary
From: John Harrison
Add several module failure load inject points in the CT buffer creation
code path.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8
1 file changed, 8 insertions(+)
diff --g
With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often software hits the case where no space is available in the CTB
buffer.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Michal Wajdeczko
---
In upcoming patch we will allow more CTB requests to be sent in
parallel to the GuC for processing, so we shouldn't assume any more
that GuC will always reply without 10ms.
Use bigger value hardcoded value of 1s instead.
v2: Add CONFIG_DRM_I915_GUC_CTB_TIMEOUT config option
v3:
(Daniel Vetter)
As part of enabling GuC submission discussed in [1], [2], and [3] we
need optimize and update the CT code as this is now in the critical
path of submission. This series includes the patches to do that which is
the first 7 patches from [3]. The patches should have addressed all the
feedback in [3] a
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