[Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA

== Series Details == Series: Restricted DMA URL : https://patchwork.freedesktop.org/series/91694/ State : failure == Summary == Applying: swiotlb: Refactor swiotlb init functions Applying: swiotlb: Refactor swiotlb_create_debugfs Applying: swiotlb: Set dev->dma_io_tlb_mem to the swiotlb pool u

Re: [Intel-gfx] [PATCH v13 00/12] Restricted DMA

v14: https://lore.kernel.org/patchwork/cover/1448954/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v14 12/12] of: Add plumbing for restricted DMA pool

If a device is not behind an IOMMU, we look up the device node and set up the restricted DMA when the restricted-dma-pool is presented. Signed-off-by: Claire Chang Tested-by: Stefano Stabellini Tested-by: Will Deacon --- drivers/of/address.c| 33 + drivers/o

[Intel-gfx] [PATCH v14 11/12] dt-bindings: of: Add restricted DMA pool

Introduce the new compatible string, restricted-dma-pool, for restricted DMA. One can specify the address and length of the restricted DMA memory region by restricted-dma-pool in the reserved-memory node. Signed-off-by: Claire Chang Tested-by: Stefano Stabellini Tested-by: Will Deacon --- .../

[Intel-gfx] [PATCH v14 10/12] swiotlb: Add restricted DMA pool initialization

Add the initialization function to create restricted DMA pools from matching reserved-memory nodes. Regardless of swiotlb setting, the restricted DMA pool is preferred if available. The restricted DMA pools provide a basic level of protection against the DMA overwriting buffer contents at unexpec

[Intel-gfx] [PATCH v14 08/12] swiotlb: Refactor swiotlb_tbl_unmap_single

Add a new function, swiotlb_release_slots, to make the code reusable for supporting different bounce buffer pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon --- kernel/dma/swiotlb.c | 35 ---

[Intel-gfx] [PATCH v14 09/12] swiotlb: Add restricted DMA alloc/free support

Add the functions, swiotlb_{alloc,free} and is_swiotlb_for_alloc to support the memory allocation from restricted DMA pool. The restricted DMA pool is preferred if available. Note that since coherent allocation needs remapping, one must set up another device coherent pool by shared-dma-pool and u

[Intel-gfx] [PATCH v14 07/12] swiotlb: Move alloc_size to swiotlb_find_slots

Rename find_slots to swiotlb_find_slots and move the maintenance of alloc_size to it for better code reusability later. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon --- kernel/dma/swiotlb.c | 16 1 file change

[Intel-gfx] [PATCH v14 06/12] swiotlb: Use is_swiotlb_force_bounce for swiotlb data bouncing

Propagate the swiotlb_force into io_tlb_default_mem->force_bounce and use it to determine whether to bounce the data or not. This will be useful later to allow for different pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon A

[Intel-gfx] [PATCH v14 05/12] swiotlb: Update is_swiotlb_active to add a struct device argument

Update is_swiotlb_active to add a struct device argument. This will be useful later to allow for different pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon Acked-by: Stefano Stabellini --- drivers/gpu/drm/i915/gem/i915_gem

[Intel-gfx] [PATCH v14 04/12] swiotlb: Update is_swiotlb_buffer to add a struct device argument

Update is_swiotlb_buffer to add a struct device argument. This will be useful later to allow for different pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon Acked-by: Stefano Stabellini --- drivers/iommu/dma-iommu.c | 12 ++

[Intel-gfx] [PATCH v14 03/12] swiotlb: Set dev->dma_io_tlb_mem to the swiotlb pool used

Always have the pointer to the swiotlb pool used in struct device. This could help simplify the code for other pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon Acked-by: Stefano Stabellini --- drivers/base/core.c| 4 ++

[Intel-gfx] [PATCH v14 02/12] swiotlb: Refactor swiotlb_create_debugfs

Split the debugfs creation to make the code reusable for supporting different bounce buffer pools. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon --- kernel/dma/swiotlb.c | 21 ++--- 1 file changed, 14 insertions

[Intel-gfx] [PATCH v14 01/12] swiotlb: Refactor swiotlb init functions

Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct initialization to make the code reusable. Signed-off-by: Claire Chang Reviewed-by: Christoph Hellwig Tested-by: Stefano Stabellini Tested-by: Will Deacon --- kernel/dma/swiotlb.c | 50 ++

[Intel-gfx] [PATCH v14 00/12] Restricted DMA

This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For example, we plan to use the PCI-e bus for Wi

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/eb: Fix pagefault disabling in the first slowpath

== Series Details == Series: drm/i915/eb: Fix pagefault disabling in the first slowpath URL : https://patchwork.freedesktop.org/series/91691/ State : success == Summary == CI Bug Log - changes from CI_DRM_10245_full -> Patchwork_20416_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: allow DG1 autoprobe for CONFIG_BROKEN (rev2)

== Series Details == Series: drm/i915: allow DG1 autoprobe for CONFIG_BROKEN (rev2) URL : https://patchwork.freedesktop.org/series/91440/ State : success == Summary == CI Bug Log - changes from CI_DRM_10243_full -> Patchwork_20415_full Summ

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Update firmware to v62.0.0 (rev4)

On Wed, Jun 16, 2021 at 06:04:55AM +, Patchwork wrote: > == Series Details == > > Series: Update firmware to v62.0.0 (rev4) > URL : https://patchwork.freedesktop.org/series/91106/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10226_full -> Patchwork_20379_full >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/eb: Fix pagefault disabling in the first slowpath

== Series Details == Series: drm/i915/eb: Fix pagefault disabling in the first slowpath URL : https://patchwork.freedesktop.org/series/91691/ State : success == Summary == CI Bug Log - changes from CI_DRM_10245 -> Patchwork_20416 Summary --

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce i915_sched_engine object (rev6)

On Fri, Jun 18, 2021 at 03:53:40AM +, Patchwork wrote: > == Series Details == > > Series: Introduce i915_sched_engine object (rev6) > URL : https://patchwork.freedesktop.org/series/90630/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10240_full -> Patchwork_20406

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR

== Series Details == Series: series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR URL : https://patchwork.freedesktop.org/series/91685/ State : success == Summary == CI Bug Log - changes from CI_DRM_10243_full -> Patchwork_20414_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/eb: Fix pagefault disabling in the first slowpath

== Series Details == Series: drm/i915/eb: Fix pagefault disabling in the first slowpath URL : https://patchwork.freedesktop.org/series/91691/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2a6b87403e3a drm/i915/eb: Fix pagefault disabling in the first slowpath -:11: ERROR:GIT_CO

[Intel-gfx] [PATCH] drm/i915/eb: Fix pagefault disabling in the first slowpath

In commit ebc0808fa2da0548a78e715858024cb81cd732bc Author: Chris Wilson Date: Tue Oct 18 13:02:51 2016 +0100 drm/i915: Restrict pagefault disabling to just around copy_from_user() we entirely missed that there's a slow path call to eb_relocate_entry (or i915_gem_execbuffer_relocate_entry

Re: [Intel-gfx] [PATCH 9/9] drm/i915/fbc: Allocate llb before cfb

whole series is Reviewed-by: José Roberto de Souza On Thu, 2021-06-10 at 21:32 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Since the llb allocation has a fixed size, let's grab it before > the potentially variable sized cfb. That should avoid some allocation > failure cases once we al

Re: [Intel-gfx] [PATCH v4] drm/i915: Document the Virtual Engine uAPI

On Fri, Jun 18, 2021 at 5:00 PM Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > A little bit of documentation covering the topics of engine discovery, > context engine maps and virtual engines. It is not very detailed but > supposed to be a starting point of giving a brief high level overview

Re: [Intel-gfx] [PULL] topic/i915-ttm

On Mon, 14 Jun 2021 at 19:37, Joonas Lahtinen wrote: > > Quoting Joonas Lahtinen (2021-06-11 14:13:02) > > Quoting Joonas Lahtinen (2021-06-11 13:40:56) > > > Quoting Maarten Lankhorst (2021-06-11 12:27:15) > > > > Pull request for drm-misc-next and drm-intel-gt-next. > > > > > > > > topic/i915-tt

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: allow DG1 autoprobe for CONFIG_BROKEN (rev2)

== Series Details == Series: drm/i915: allow DG1 autoprobe for CONFIG_BROKEN (rev2) URL : https://patchwork.freedesktop.org/series/91440/ State : success == Summary == CI Bug Log - changes from CI_DRM_10243 -> Patchwork_20415 Summary --

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR

== Series Details == Series: series starting with [1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR URL : https://patchwork.freedesktop.org/series/91685/ State : success == Summary == CI Bug Log - changes from CI_DRM_10243 -> Patchwork_20414 ==

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Document the Virtual Engine uAPI (rev4)

== Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev4) URL : https://patchwork.freedesktop.org/series/91406/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20413_full Summary -

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy

== Series Details == Series: series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy URL : https://patchwork.freedesktop.org/series/91679/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20412_full ==

Re: [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

Acked-by: Tony Ye Regards, Tony On 6/11/2021 4:40 PM, Matthew Brost wrote: > Add entry for i915 new parallel submission uAPI plan. > > v2: > (Daniel Vetter): >- Expand logical order explaination >- Add dummy header >- Only allow N BBs in execbuf IOCTL >- Configure parallel sub

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics (rev2)

== Series Details == Series: drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics (rev2) URL : https://patchwork.freedesktop.org/series/91661/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20411_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Document the Virtual Engine uAPI (rev4)

== Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev4) URL : https://patchwork.freedesktop.org/series/91406/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20413 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Document the Virtual Engine uAPI (rev4)

== Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev4) URL : https://patchwork.freedesktop.org/series/91406/ State : warning == Summary == $ dim checkpatch origin/drm-tip 043a7f21361b drm/i915: Document the Virtual Engine uAPI -:80: WARNING:SPACE_BEFORE_TAB: please, no

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy

== Series Details == Series: series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy URL : https://patchwork.freedesktop.org/series/91679/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20412

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gen11: Disable cursor clock gating in HDR mode

== Series Details == Series: drm/i915/gen11: Disable cursor clock gating in HDR mode URL : https://patchwork.freedesktop.org/series/91674/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20410_full Sum

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR

On Fri, 18 Jun 2021 at 17:14, Matthew Auld wrote: > > From: Clint Taylor > > The PUNIT FW is currently returning 0 for all memory bandwidth > parameters. Read the values directly from MCHBAR offsets 0x5918 and > 0x4000(4). This is a temporary WA until the PUNIT FW returns valid > values. Any tak

[Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available

From: Clint Taylor Use MCHBAR Gear_type information to compute memory bandwidth available during MCHBAR calculations. Tested-by: Swati Sharma Cc: Swati Sharma Cc: Ville Syrjälä Signed-off-by: Clint Taylor Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bw.c | 8

[Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR

From: Clint Taylor The PUNIT FW is currently returning 0 for all memory bandwidth parameters. Read the values directly from MCHBAR offsets 0x5918 and 0x4000(4). This is a temporary WA until the PUNIT FW returns valid values. Cc: Ville Syrjälä Cc: Matt Roper Cc: Jani Saarinen Signed-off-by: Cl

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy

== Series Details == Series: series starting with [1/2] drm/i915/selftests: add back the selftest() hook for the buddy URL : https://patchwork.freedesktop.org/series/91679/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won'

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics (rev2)

== Series Details == Series: drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics (rev2) URL : https://patchwork.freedesktop.org/series/91661/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20411 =

Re: [Intel-gfx] [PATCH] drm/dp_mst: Add missing drm parameters to recently added call to drm_dbg_kms()

It's no problem! We all make mistakes sometimes :), I should have been more diligent on compile-checking this myself as well On Thu, 2021-06-17 at 08:20 +, Lin, Wayne wrote: > [Public] > > Really sorry for the mistake that I made and any inconvenience it brought. > Thanks José and Lyude. > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Verify result from CTB (de)register action

== Series Details == Series: drm/i915/guc: Verify result from CTB (de)register action URL : https://patchwork.freedesktop.org/series/91673/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20409_full Su

Re: [Intel-gfx] drm/i915: __GFP_RETRY_MAYFAIL allocations in stable kernels

On Thu, 17 Jun 2021 at 18:27, Daniel Vetter wrote: > > On Mon, Jun 14, 2021 at 09:45:37PM +0900, Sergey Senozhatsky wrote: > > Hi, > > > > We are observing some user-space crashes (sigabort, segfaults etc.) > > under moderate memory pressure (pretty far from severe pressure) which > > have one thi

[Intel-gfx] [PATCH v4] drm/i915: Document the Virtual Engine uAPI

From: Tvrtko Ursulin A little bit of documentation covering the topics of engine discovery, context engine maps and virtual engines. It is not very detailed but supposed to be a starting point of giving a brief high level overview of general principles and intended use cases. v2: * Have the tex

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen11: Disable cursor clock gating in HDR mode

== Series Details == Series: drm/i915/gen11: Disable cursor clock gating in HDR mode URL : https://patchwork.freedesktop.org/series/91674/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20410 Summary -

[Intel-gfx] [PATCH v3] drm/i915: Document the Virtual Engine uAPI

From: Tvrtko Ursulin A little bit of documentation covering the topics of engine discovery, context engine maps and virtual engines. It is not very detailed but supposed to be a starting point of giving a brief high level overview of general principles and intended use cases. v3: * Move text to

Re: [Intel-gfx] [PATCH v13 01/12] swiotlb: Refactor swiotlb init functions

On Fri, Jun 18, 2021 at 09:09:17AM -0500, Tom Lendacky wrote: > > swiotlb_init_with_tbl uses memblock_alloc to allocate the io_tlb_mem > > and memblock_alloc[1] will do memset in memblock_alloc_try_nid[2], so > > swiotlb_init_with_tbl is also good. > > I'm happy to add the memset in swiotlb_init_io

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Verify result from CTB (de)register action

== Series Details == Series: drm/i915/guc: Verify result from CTB (de)register action URL : https://patchwork.freedesktop.org/series/91673/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20409 Summary

Re: [Intel-gfx] [PATCH 2/2] drm/i915: add back the avail tracking

On 18/06/2021 14:44, Thomas Hellström wrote: On 6/18/21 3:31 PM, Matthew Auld wrote: Looks like it got lost along the way, so add it back. This is needed for the region query uAPI where we need to report an accurate available size for lmem. Hmm. How is this uAPI intended to work in a multi-cl

Re: [Intel-gfx] [PATCH v13 01/12] swiotlb: Refactor swiotlb init functions

On Thu, 17 Jun 2021, Claire Chang wrote: > Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct > initialization to make the code reusable. > > Signed-off-by: Claire Chang > Reviewed-by: Christoph Hellwig > Tested-by: Stefano Stabellini > Tested-by: Will Deacon > --- > kerne

Re: [Intel-gfx] [PATCH v13 09/12] swiotlb: Add restricted DMA alloc/free support

On Thu, 17 Jun 2021, Claire Chang wrote: > Add the functions, swiotlb_{alloc,free} and is_swiotlb_for_alloc to > support the memory allocation from restricted DMA pool. > > The restricted DMA pool is preferred if available. > > Note that since coherent allocation needs remapping, one must set up

Re: [Intel-gfx] [PATCH v13 03/12] swiotlb: Set dev->dma_io_tlb_mem to the swiotlb pool used

On Thu, 17 Jun 2021, Claire Chang wrote: > Always have the pointer to the swiotlb pool used in struct device. This > could help simplify the code for other pools. > > Signed-off-by: Claire Chang > Reviewed-by: Christoph Hellwig > Tested-by: Stefano Stabellini > Tested-by: Will Deacon Acked-by

Re: [Intel-gfx] [PATCH v13 05/12] swiotlb: Update is_swiotlb_active to add a struct device argument

On Thu, 17 Jun 2021, Claire Chang wrote: > Update is_swiotlb_active to add a struct device argument. This will be > useful later to allow for different pools. > > Signed-off-by: Claire Chang > Reviewed-by: Christoph Hellwig > Tested-by: Stefano Stabellini > Tested-by: Will Deacon Acked-by: St

Re: [Intel-gfx] [PATCH v13 04/12] swiotlb: Update is_swiotlb_buffer to add a struct device argument

On Thu, 17 Jun 2021, Claire Chang wrote: > Update is_swiotlb_buffer to add a struct device argument. This will be > useful later to allow for different pools. > > Signed-off-by: Claire Chang > Reviewed-by: Christoph Hellwig > Tested-by: Stefano Stabellini > Tested-by: Will Deacon Acked-by: St

Re: [Intel-gfx] [PATCH v13 06/12] swiotlb: Use is_swiotlb_force_bounce for swiotlb data bouncing

On Thu, 17 Jun 2021, Claire Chang wrote: > Propagate the swiotlb_force into io_tlb_default_mem->force_bounce and > use it to determine whether to bounce the data or not. This will be > useful later to allow for different pools. > > Signed-off-by: Claire Chang > Reviewed-by: Christoph Hellwig > T

Re: [Intel-gfx] [PATCH 2/2] drm/i915: add back the avail tracking

On 6/18/21 3:31 PM, Matthew Auld wrote: Looks like it got lost along the way, so add it back. This is needed for the region query uAPI where we need to report an accurate available size for lmem. Hmm. How is this uAPI intended to work in a multi-client environment where the returned value can

Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: add back the selftest() hook for the buddy

On 18/06/2021 14:36, Thomas Hellström wrote: Hi. On 6/18/21 3:31 PM, Matthew Auld wrote: When we resurrected the selftest we forgot to add back the selftest() hook, meaning the test is not currently run. Reported-by: kernel test robot Signed-off-by: Matthew Auld Cc: Thomas Hellström Do we

Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: add back the selftest() hook for the buddy

Hi. On 6/18/21 3:31 PM, Matthew Auld wrote: When we resurrected the selftest we forgot to add back the selftest() hook, meaning the test is not currently run. Reported-by: kernel test robot Signed-off-by: Matthew Auld Cc: Thomas Hellström Do we need a Fixes: tag? Reviewed-by: Thomas Hells

[Intel-gfx] [PATCH 2/2] drm/i915: add back the avail tracking

Looks like it got lost along the way, so add it back. This is needed for the region query uAPI where we need to report an accurate available size for lmem. This time around let's push it directly into the allocator, which simplifies things, like not having to care about internal fragmentation, or

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: add back the selftest() hook for the buddy

When we resurrected the selftest we forgot to add back the selftest() hook, meaning the test is not currently run. Reported-by: kernel test robot Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + 1 file changed, 1 insertion(+) dif

[Intel-gfx] [PATCH v2] drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

We have assumed that if the current placement was not the requested placement, but instead one of the busy placements, a TTM move would have been triggered. That is not the case. So when we initially place LMEM objects in "Limbo", (that is system placement without any pages allocated), to be able

Re: [Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

> -Original Message- > From: Ville Syrjälä > Sent: 18 June 2021 18:15 > To: Surendrakumar Upadhyay, TejaskumarX > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock > gating in HDR mode > > On Fri, Jun 18, 2021 at 05:16:06P

Re: [Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

> -Original Message- > From: Ville Syrjälä > Sent: 18 June 2021 18:15 > To: Surendrakumar Upadhyay, TejaskumarX > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock > gating in HDR mode > > On Fri, Jun 18, 2021 at 05:16:06P

Re: [Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

On Fri, Jun 18, 2021 at 05:16:06PM +0530, Tejas Upadhyay wrote: > Display underrun in HDR mode when cursor is enabled. > RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h. > As per W/A 1604331009, Disable cursor clock gating in HDR mode. > > Bspec : 33451 > > Changes since V2: >

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

On 6/18/21 12:53 PM, Matthew Auld wrote: On Fri, 18 Jun 2021 at 09:31, Thomas Hellström wrote: We have assumed that if the current placement was not the requested placement, but instead one of the busy placements, a TTM move would have been triggered. That is not the case. So when we initiall

Re: [Intel-gfx] [PATCH v2 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > The icl combo phy DP HBR2 is identical to the eDP HBR3 table. > Get rid of one redundant copy. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../drm/i915/display/intel_ddi_buf_trans.c| 39 +---

Re: [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix dg1 buf trans tables

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > For some reason the dg1 buf trans tables have been stuffed into > icl_get_combo_buf_trans_edp() which doesn't even get called > on dg1. Split them out into a proper dg1 specific function, > and also make sure we use the proper bu

Re: [Intel-gfx] [PATCH v2 11/17] drm/i915: Introduce rkl_get_combo_buf_trans()

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Give RKL its own get_buf_trans() func. > > v2: Drop the FIXME since the spec was clarified to > indicate that TGL values are used for the HDMI/eDP cases. > > Reviewed-by: Jani Nikula #v1 Holds for v2. > Signed-off-by: Vill

Re: [Intel-gfx] [PATCH v2 09/17] drm/i915: Introduce encoder->get_buf_trans()

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Convert the get_buf_trans() functions into an encoder vfunc. > Allows us to get rid of bunch of platform if-ladders. > > v2: Handle adl-p > > Reviewed-by: Jani Nikula #v1 Holds for v2. > Signed-off-by: Ville Syrjälä > --- >

[Intel-gfx] [drm-intel:drm-intel-gt-next 2/8] drivers/gpu/drm/i915/selftests/i915_buddy.c:777:5: warning: no previous prototype for 'i915_buddy_mock_selftests'

tree: git://anongit.freedesktop.org/drm-intel drm-intel-gt-next head: 13c2ceb6addb6b14468e09b75832c98909eed8e7 commit: 88be9a0a06b73ecd85a688a7c174c941e9692e92 [2/8] drm/i915/ttm: add ttm_buddy_man config: x86_64-randconfig-a012-20210618 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22

[Intel-gfx] ✗ Fi.CI.IGT: failure for New uAPI drm properties for color management (rev2)

== Series Details == Series: New uAPI drm properties for color management (rev2) URL : https://patchwork.freedesktop.org/series/91523/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20408_full Summary

Re: [Intel-gfx] [PATCH v2 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans()

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Raise the abstraction level of the get_buf_trans() functions > a bit more by returning the whole wrapper intel_ddi_buf_trans > struct. > > v2: Handle adl-p > > Reviewed-by: Jani Nikula #v1 Holds for v2. > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH v2 06/17] drm/i915: Introduce intel_get_buf_trans()

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Add a small helper to get the buf trans entris+num_entries > from the struct. Should avoid copy-paste errors in the > platform specific get_buf_trans() functions. > > @@ > identifier T, N; > @@ > - *N = T.num_entries; > - return

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

On 6/18/21 12:26 PM, Patchwork wrote: Project List - Patchwork *Patch Details* *Series:* drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics *URL:* https://patchwork.freedesktop.org/series/91661/ *State:*failure

Re: [Intel-gfx] [PATCH v2 05/17] drm/i915: Wrap the buf trans tables into a struct

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Put a wrapper struct around the buf trans tables so that > we can declare the number of entries and default HDMI entry > alongside the table. > > @wrap@ > identifier old =~ "^.*translations.*"; > fresh identifier new = "_" ## old

Re: [Intel-gfx] [PATCH v2 04/17] drm/i915: Rename dkl phy buf trans tables

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Rename the dkl phy buf trans tables to follow the same > naming pattern used by everyone else. > > v2: Handle adl-p > > Reviewed-by: Jani Nikula #v1 Holds for v2. > Signed-off-by: Ville Syrjälä > --- > .../drm/i915/display/i

Re: [Intel-gfx] [PATCH v2 03/17] drm/i915: Wrap the platform specific buf trans structs into a union

On Tue, 08 Jun 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > In order to abstact the buf trans stuff let's wrap the platform > specific structs into a union. > > v2: Handle adl-p > > Reviewed-by: Jani Nikula #v1 Holds for v2. > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915

[Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

Display underrun in HDR mode when cursor is enabled. RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h. As per W/A 1604331009, Disable cursor clock gating in HDR mode. Bspec : 33451 Changes since V2: - Made it general gen11 WA - Removed WA needed check - Added cu

Re: [Intel-gfx] [bug report] drm/i915/guc: Add support for data reporting in GuC responses

Hello Dan, On 18.06.2021 09:38, Dan Carpenter wrote: > Hello Michal Wajdeczko, > > The patch b839a869dfc9: "drm/i915/guc: Add support for data reporting > in GuC responses" from Mar 26, 2018, leads to the following static > checker warning: > > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:307

[Intel-gfx] [PATCH] drm/i915/guc: Verify result from CTB (de)register action

In commit b839a869dfc9 ("drm/i915/guc: Add support for data reporting in GuC responses") we missed the hypothetical case that GuC might return positive non-zero value as success data. While that would be lucky treated as error case, and at the end will result in reporting valid -EIO, in the meanti

Re: [Intel-gfx] [PATCH] drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

On Fri, 18 Jun 2021 at 09:31, Thomas Hellström wrote: > > We have assumed that if the current placement was not the requested > placement, but instead one of the busy placements, a TTM move would have > been triggered. That is not the case. > > So when we initially place LMEM objects in "Limbo", (

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

== Series Details == Series: drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics URL : https://patchwork.freedesktop.org/series/91661/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20407_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for New uAPI drm properties for color management (rev2)

== Series Details == Series: New uAPI drm properties for color management (rev2) URL : https://patchwork.freedesktop.org/series/91523/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20408 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for New uAPI drm properties for color management (rev2)

== Series Details == Series: New uAPI drm properties for color management (rev2) URL : https://patchwork.freedesktop.org/series/91523/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for New uAPI drm properties for color management (rev2)

== Series Details == Series: New uAPI drm properties for color management (rev2) URL : https://patchwork.freedesktop.org/series/91523/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8a1dbc104f1d drm/amd/display: Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check -:32: CHECK:LOGICA

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics

== Series Details == Series: drm/i915/ttm: Fix incorrect assumptions about ttm_bo_validate() semantics URL : https://patchwork.freedesktop.org/series/91661/ State : success == Summary == CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20407

[Intel-gfx] [PATCH v4 17/17] drm/amd/display: Add handling for new "Broadcast RGB" property

This commit implements the "Broadcast RGB" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 2 files changed, 21 insertions(+), 5 deletions(-) di

[Intel-gfx] [PATCH v4 14/17] drm/i915/display: Add handling for new "preferred color format" property

This commit implements the "preferred color format" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 + drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++ 3 f

[Intel-gfx] [PATCH v4 16/17] drm/i915/display: Use the general "Broadcast RGB" implementation

Change from the i915 specific "Broadcast RGB" drm property implementation to the general one. This commit delete all traces of the former "Broadcast RGB" implementation and add a new one using the new driver agnoistic functions an variables. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH v4 15/17] drm/uAPI: Move "Broadcast RGB" property from driver specific to general context

Add "Broadcast RGB" to general drm context so that more drivers besides i915 and gma500 can implement it without duplicating code. Userspace can use this property to tell the graphic driver to use full or limited color range for a given connector, overwriting the default behaviour/automatic detect

[Intel-gfx] [PATCH v4 12/17] drm/uAPI: Add "preferred color format" drm property as setting for userspace

Add a new general drm property "preferred color format" which can be used by userspace to tell the graphic drivers to which color format to use. Possible options are: - auto (default/current behaviour) - rgb - ycbcr444 - ycbcr422 (not supported by both amdgpu and i915) - ycbcr4

[Intel-gfx] [PATCH v4 11/17] drm/i915/display: Add handling for new "active color range" property

This commit implements the "active color range" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 + drivers/g

[Intel-gfx] [PATCH v4 13/17] drm/amd/display: Add handling for new "preferred color format" property

This commit implements the "preferred color format" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++ 2 files changed, 28 insertions(+), 6 deletion

[Intel-gfx] [PATCH v4 10/17] drm/amd/display: Add handling for new "active color range" property

This commit implements the "active color range" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++ 2 files changed, 37 insertions(+) diff --git a/d

[Intel-gfx] [PATCH v4 05/17] drm/i915/display: Add handling for new "active bpc" property

This commit implements the "active bpc" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_display.c | 17 + drivers/gpu/drm/i915/display/intel_dp.c | 7 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +

[Intel-gfx] [PATCH v4 07/17] drm/amd/display: Add handling for new "active color format" property

This commit implements the "active color format" drm property for the AMD GPU driver. Signed-off-by: Werner Sembach --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +-- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++ 2 files changed, 31 insertions(+), 2 deletions(-

[Intel-gfx] [PATCH v4 09/17] drm/uAPI: Add "active color range" drm property as feedback for userspace

Add a new general drm property "active color range" which can be used by graphic drivers to report the used color range back to userspace. There was no way to check which color range got actually used on a given monitor. To surely predict this, one must know the exact capabilities of the monitor a

[Intel-gfx] [PATCH v4 06/17] drm/uAPI: Add "active color format" drm property as feedback for userspace

Add a new general drm property "active color format" which can be used by graphic drivers to report the used color format back to userspace. There was no way to check which color format got actually used on a given monitor. To surely predict this, one must know the exact capabilities of the monito

[Intel-gfx] [PATCH v4 08/17] drm/i915/display: Add handling for new "active color format" property

This commit implements the "active color format" drm property for the Intel GPU driver. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_display.c | 22 +++- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c |

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