== Series Details ==
Series: drm/i915/reg: replace BIT() usage with REG_BIT() (rev2)
URL : https://patchwork.freedesktop.org/series/90270/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10098_full -> Patchwork_20144_full
Sum
On Wed, 19 May 2021, Zhenyu Wang wrote:
> Reviewed-by: Zhenyu Wang
>
> Thanks!
Thanks for the review. Please also let Greg know whether he can pick
this up via the debugfs tree; I don't care either way.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
__
On 5/18/21 6:30 PM, Christian König wrote:
Am 18.05.21 um 18:07 schrieb Thomas Hellström:
On 5/18/21 5:42 PM, Christian König wrote:
Am 18.05.21 um 17:38 schrieb Thomas Hellström:
On 5/18/21 5:28 PM, Christian König wrote:
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM
On 5/18/21 3:23 PM, Christoph Hellwig wrote:
On Mon, May 17, 2021 at 11:46:35PM +0200, Thomas Hellström wrote:
Apart from the caching aliasing Mattew brought up, doesn't the
remap_pfn_range_xxx() family require the mmap_sem held in write mode since
it modifies the vma structure? remap_io_sg() i
On Tue, May 18, 2021 at 02:34:44PM -0700, Anusha Srivatsa wrote:
Finally, rename the header and source file from csr to dmc.
v2: Add file rename in Documentation.
- Place headers in orders. (Jani)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
Documentation/gpu/i915.rst
On 5/18/21 5:00 PM, Matthew Auld wrote:
On Tue, 18 May 2021 at 14:21, Christoph Hellwig wrote:
On Mon, May 17, 2021 at 06:06:44PM +0100, Matthew Auld wrote:
Looks like it is caused by the validation failure then. Which means the
existing code is doing something wrong in its choice of the pa
On Tue, May 18, 2021 at 02:34:43PM -0700, Anusha Srivatsa wrote:
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_csr.c | 64 +--
drivers/gpu/drm/i915/display/inte
On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote:
Rename all occurences of CSR_* with DMC_*
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_csr.c | 167 +-
drivers/gpu/d
On Tue, May 18, 2021 at 02:34:41PM -0700, Anusha Srivatsa wrote:
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_csr.c | 12 ++--
drivers/gpu/drm/i915/display/inte
On Tue, May 18, 2021 at 02:34:40PM -0700, Anusha Srivatsa wrote:
No functional change.
v2: Chchpatch fixes.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
`git show -U0 --word-diff=color` really helps here. Not sure if I would
split the patch per struct/funct
On Thu, May 06, 2021 at 12:13:17PM -0700, Matthew Brost wrote:
> From: Chris Wilson
>
> The different submission backends each have their own preferred
> behaviour and interrupt setup. Let each handle their own interrupts.
>
> This becomes more useful later as we to extract the use of auxiliary
On Thu, May 06, 2021 at 12:13:16PM -0700, Matthew Brost wrote:
> From: Chris Wilson
>
> Since we setup the submission method for the engines once, it is easy to
> assign an enum and use that instead of probing into the backends.
>
> Signed-off-by: Matthew Brost
> Signed-off-by: Chris Wilson
>
On 2021.05.18 18:17:05 +0200, Greg Kroah-Hartman wrote:
> There is no need to keep the dentry around for the debugfs kvmgt cache
> file, as we can just look it up when we want to remove it later on.
> Simplify the structure by removing the dentry and relying on debugfs
> to find the dentry to remov
== Series Details ==
Series: ADL-P: more reviewed patches
URL : https://patchwork.freedesktop.org/series/90305/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20151
Summary
---
**SUCCESS**
No reg
On Thu, May 06, 2021 at 12:13:15PM -0700, Matthew Brost wrote:
> From: Chris Wilson
>
> Now that we no longer switch back and forth between guc and execlists,
> we no longer need to restore the backend's vfunc and can leave them set
> after initialisation. The only catch is that we lose the submi
== Series Details ==
Series: ADL-P: more reviewed patches
URL : https://patchwork.freedesktop.org/series/90305/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel
== Series Details ==
Series: ADL-P: more reviewed patches
URL : https://patchwork.freedesktop.org/series/90305/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a03b363a26c6 drm/i915/xelpd: Calculate VDSC RC parameters
7961852577ed drm/i915/xelpd: Add rc_qp_table for rcparams calc
== Series Details ==
Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL : https://patchwork.freedesktop.org/series/89840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20150
Sum
From: Vandita Kulkarni
Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as per the sequence mentioned in the bspec.
Cc: Stanislav Lisovskiy
Cc: José Roberto de Souza
Signed-off-by: Vandita Ku
From: Ville Syrjälä
The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accommodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
For crtc_state->wm.sk
From: Gwan-gyeong Mun
In order to reuse code of PSR interrupt error check on other PSR functions,
it adds psr_interrupt_error_check() function.
Cc: José Roberto de Souza
Signed-off-by: Gwan-gyeong Mun
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
v3:
- Make tables 'static const' and add lookup functions to index into
From: Vandita Kulkarni
On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.
Bspec: 49255
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton Tayl
From: Imre Deak
On ADL_P besides programming the PLL accordingly the DP/HDMI link rate
should be also programmed to the DDI_BUF_CTL register, do that.
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
Signed-off-by: Lucas De March
From: Mika Kahola
Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx
From: José Roberto de Souza
ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.
So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
th
From: Matt Roper
XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms. However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAG
From: José Roberto de Souza
Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.
Bspec: 49213
Cc: Matt Roper
Signed-off-by: José Roberto de Sou
From: Vandita Kulkarni
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesn't support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
v2:
- Checkp
From: Gwan-gyeong Mun
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And
it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline
without intel_crtc_state on other psr internal function like as
intel_psr_enable_source().
Cc: Ville Syrjälä
Cc: José Roberto de
From: Anusha Srivatsa
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.
Cc: Matt Roper
Cc: Clinton Taylor
Cc: Lucas De Marchi
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Tay
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
v2:
- Update according to recent bspec updates; there are now separate
tables for RBR/HBR and HBR2/HBR3. (Anusha)
BSpec: 54956
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Clinton
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy c
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
From: Anusha Srivatsa
ADL_P has same memory characteristics as ADL_S platform.
Bspec: 64631
Cc: José Roberto de Souza
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Now just a few remaining from the original batch of patches to support
ADL-P.
Anusha Srivatsa (4):
drm/i915/adl_p: Setup ports/phys
drm/i915/adl_p: Add PLL Support
drm/i915/adlp: Add PIPE_MISC2 programming
drm/i915/adl_p: Update memory bandwidth parameters
Gwan-gyeong Mun (2):
drm/i915/
== Series Details ==
Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL : https://patchwork.freedesktop.org/series/89840/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/rfc/i915_scheduler.rst:43: WARNIN
== Series Details ==
Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL : https://patchwork.freedesktop.org/series/89840/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe3698660450 drm/doc/rfc: i915 GuC submission / DRM scheduler
-:30: WARNING:BAD_SIG
Add entry for i915 GuC submission / DRM scheduler integration plan.
Follow up patch with details of new parallel submission uAPI to come.
v2:
(Daniel Vetter)
- Expand explaination of why bonding isn't supported for GuC
submission
- CC some of the DRM scheduler maintainers
- Add priority
Add entry fpr i915 new parallel submission uAPI plan.
v2:
(Daniel Vetter):
- Expand logical order explaination
- Add dummy header
- Only allow N BBs in execbuf IOCTL
- Configure parallel submission per slot not per gem context
Cc: Tvrtko Ursulin
Cc: Tony Ye
CC: Carl Zhang
Cc: Daniel V
Subject and patches say it all.
v2: Address comments, patches has details of changes
Signed-off-by: Matthew Brost
Matthew Brost (2):
drm/doc/rfc: i915 GuC submission / DRM scheduler
drm/doc/rfc: i915 new parallel submission uAPI plan
Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 +++
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20149
Summary
---
**WARNING*
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/i
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c95595fe6606 drm/i915/dmc: s/intel_csr/intel_dmc
dcf0abc59e2e drm/i915/dmc: s/HAS_CSR/HAS_DMC
533a65622dfe dr
No functional change.
v2: Chchpatch fixes.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 170 +-
.../drm/i915/display/intel_display_debugfs.c | 14 +-
.../drm/i915/display/intel_display_power.c| 52 +++---
drivers/gpu/
Currently in our driver we use both CSR and DMC interchangeably.
Even though the spec mentions both, we do not follow that convention
in the driver.
Renaming all references of CSR to just be DMC. This hopefully makes
the driver of this part a litlle less confusing.
Suggested-by: Jani Nikula
Ack
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 64 +--
drivers/gpu/drm/i915/display/intel_csr.h | 10 +--
drivers/gpu/drm/i915/display/intel_display.c | 14 ++--
.../drm/i915/display/intel_display_po
Finally, rename the header and source file from csr to dmc.
v2: Add file rename in Documentation.
- Place headers in orders. (Jani)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
Documentation/gpu/i915.rst | 12 ++--
drivers/gpu/drm/i915/Makefile
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 12 ++--
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_
Rename all occurences of CSR_* with DMC_*
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 167 +-
drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 16 +-
.../drm/i915/displ
== Series Details ==
Series: Rename all CSR references to DMC (rev4)
URL : https://patchwork.freedesktop.org/series/90043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20148
Summary
---
**SUCCESS*
== Series Details ==
Series: Rename all CSR references to DMC (rev4)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:540: WARNING: Unknown target
name: "csr firmware
== Series Details ==
Series: Rename all CSR references to DMC (rev4)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/i
== Series Details ==
Series: Rename all CSR references to DMC (rev4)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
843f8bd30dfb drm/i915/dmc: s/intel_csr/intel_dmc
c583faac1a4b drm/i915/dmc: s/HAS_CSR/HAS_DMC
b2dab106272a dr
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20147
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 64 +--
drivers/gpu/drm/i915/display/intel_csr.h | 10 +--
drivers/gpu/drm/i915/display/intel_display.c | 14 ++--
.../drm/i915/display/intel_display_po
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 12 ++--
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_
Rename all occurences of CSR_* with DMC_*
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 167 +-
drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 16 +-
.../drm/i915/displ
Currently in our driver we use both CSR and DMC interchangeably.
Even though the spec mentions both, we do not follow that convention
in the driver.
Renaming all references of CSR to just be DMC. This hopefully makes
the driver of this part a litlle less confusing.
Suggested-by: Jani Nikula
Ack
No functional change.
v2: Chchpatch fixes.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 170 +-
.../drm/i915/display/intel_display_debugfs.c | 14 +-
.../drm/i915/display/intel_display_power.c| 52 +++---
drivers/gpu/
Finally, rename the header and source file from csr to dmc.
v2: Add file rename in Documentation.
- Place headers in orders. (Jani)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
Documentation/gpu/i915.rst | 10 +-
drivers/gpu/drm/i915/Makefile
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
634883ae67b3 drm/i915/dpcd_bl: Remove redundant AUX backlight frequenc
On Tue, 2021-05-18 at 05:56 +, Patchwork wrote:
Patch Details
Series: drm/i915: Initialize err in remap_io_sg()
URL:https://patchwork.freedesktop.org/series/90258/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20139/index.html
CI Bug Log - changes from
On Fri, May 14, 2021 at 08:10:15PM -0700, Matt Roper wrote:
> From: Vandita Kulkarni
>
> Add methods to calculate rc parameters for all bpps, against the fixed
> arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
> formats. Our hw doesn't support YUV compression yet. The c
== Series Details ==
Series: drm/i915/gvt: remove local storage of debugfs file
URL : https://patchwork.freedesktop.org/series/90294/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10098 -> Patchwork_20146
Summary
---
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM (rev2)
URL : https://patchwork.freedesktop.org/series/90022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10094_full -> Patchwork_20142_full
Su
== Series Details ==
Series: drm/i915/plane: add intel_plane_helper_add() helper
URL : https://patchwork.freedesktop.org/series/90287/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10098 -> Patchwork_20145
Summary
---
Am 18.05.21 um 18:07 schrieb Thomas Hellström:
On 5/18/21 5:42 PM, Christian König wrote:
Am 18.05.21 um 17:38 schrieb Thomas Hellström:
On 5/18/21 5:28 PM, Christian König wrote:
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17
On Tue, May 18, 2021 at 06:17:05PM +0200, Greg Kroah-Hartman wrote:
> There is no need to keep the dentry around for the debugfs kvmgt cache
> file, as we can just look it up when we want to remove it later on.
> Simplify the structure by removing the dentry and relying on debugfs
> to find the den
== Series Details ==
Series: drm/i915/reg: replace BIT() usage with REG_BIT() (rev2)
URL : https://patchwork.freedesktop.org/series/90270/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10098 -> Patchwork_20144
Summary
-
There is no need to keep the dentry around for the debugfs kvmgt cache
file, as we can just look it up when we want to remove it later on.
Simplify the structure by removing the dentry and relying on debugfs
to find the dentry to remove when we want to.
By doing this change, we remove the last in-
On 5/18/21 5:42 PM, Christian König wrote:
Am 18.05.21 um 17:38 schrieb Thomas Hellström:
On 5/18/21 5:28 PM, Christian König wrote:
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26
Am 18.05.21 um 17:38 schrieb Thomas Hellström:
On 5/18/21 5:28 PM, Christian König wrote:
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling t
On 5/18/21 5:28 PM, Christian König wrote:
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling the eviction_valuable driver callback at eviction
Am 18.05.21 um 17:20 schrieb Thomas Hellström:
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling the eviction_valuable driver callback at eviction
time to
determine whether we actually can
On 5/18/21 5:18 PM, Christian König wrote:
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling the eviction_valuable driver callback at eviction
time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM bac
Am 18.05.21 um 17:15 schrieb Thomas Hellström:
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
On 5/18/21 10:26 AM, Thomas Hellström wrote:
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other dr
On Tue, 18 May 2021 at 14:21, Christoph Hellwig wrote:
>
> On Mon, May 17, 2021 at 06:06:44PM +0100, Matthew Auld wrote:
> > > Looks like it is caused by the validation failure then. Which means the
> > > existing code is doing something wrong in its choice of the page
> > > protection bit. I re
On 5/18/21 1:59 PM, Christian König wrote:
Can you send me the patch directly and not just on CC?
Thanks,
Christian.
Original patch sent. Pls remember to CC lists on reply, though.
The reason we need this is because of i915's strange mmap functionality
which allows a bo to be mapped at mult
On Tue, May 18, 2021 at 04:24:26PM +0300, Jani Nikula wrote:
> Add a small helper to keep intel_plane_helper_funcs static.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_atomic_p
On 5/18/21 3:24 PM, Christoph Hellwig wrote:
On Tue, May 18, 2021 at 08:46:44AM +0200, Thomas Hellström wrote:
And worse, if we prefault a user-space buffer object map using
remap_io_sg() and then zap some ptes using madvise(), the next time those
ptes are accessed, we'd trigger a new call to r
[AMD Official Use Only]
The format is simple:
: %
we also have entries for the memory mapped:
mem : KiB
On my submission
https://lists.freedesktop.org/archives/amd-gfx/2021-May/063149.html I added a
python script to print out the info. It has a CPU usage lower that top, for
example.
To b
[Public]
Cycling some of the Nvidia/nouveau guys here too.
I think there is a benefit on trying to estandarize how fdinfo can be used to
expose per engine and device memory utilization.
Another of the advantages of going the /proc/ way instead of the sysfs debugfs
approach is that you inherit
Am 18.05.21 um 15:24 schrieb Thomas Hellström:
On 5/18/21 3:08 PM, Christian König wrote:
Am 18.05.21 um 14:52 schrieb Thomas Hellström:
On 5/18/21 2:09 PM, Christian König wrote:
Am 18.05.21 um 14:04 schrieb Thomas Hellström:
On 5/18/21 1:55 PM, Christian König wrote:
Am 18.05.21 um 10
On 5/18/21 3:08 PM, Christian König wrote:
Am 18.05.21 um 14:52 schrieb Thomas Hellström:
On 5/18/21 2:09 PM, Christian König wrote:
Am 18.05.21 um 14:04 schrieb Thomas Hellström:
On 5/18/21 1:55 PM, Christian König wrote:
Am 18.05.21 um 10:26 schrieb Thomas Hellström:
The internal ttm_b
Add a small helper to keep intel_plane_helper_funcs static.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 7 ++-
drivers/gpu/drm/i915/display/intel_atomic_plane.h | 3 +--
drivers/gpu/drm/i915/d
On Tue, May 18, 2021 at 08:46:44AM +0200, Thomas Hellström wrote:
> And worse, if we prefault a user-space buffer object map using
> remap_io_sg() and then zap some ptes using madvise(), the next time those
> ptes are accessed, we'd trigger a new call to remap_io_sg() which would now
> find alre
On Mon, May 17, 2021 at 11:46:35PM +0200, Thomas Hellström wrote:
> Apart from the caching aliasing Mattew brought up, doesn't the
> remap_pfn_range_xxx() family require the mmap_sem held in write mode since
> it modifies the vma structure? remap_io_sg() is called from the fault
> handler with t
On Mon, May 17, 2021 at 06:06:44PM +0100, Matthew Auld wrote:
> > Looks like it is caused by the validation failure then. Which means the
> > existing code is doing something wrong in its choice of the page
> > protection bit. I really need help from the i915 maintainers here..
>
> AFAIK there a
Am 18.05.21 um 15:06 schrieb Thomas Hellström:
On 5/18/21 1:51 PM, Christian König wrote:
Am 18.05.21 um 10:26 schrieb Thomas Hellström:
i915 mock selftests are run without the device set up. In order to
be able
to run the region related mock selftests, export functions in order
for the
TT
Am 18.05.21 um 14:52 schrieb Thomas Hellström:
On 5/18/21 2:09 PM, Christian König wrote:
Am 18.05.21 um 14:04 schrieb Thomas Hellström:
On 5/18/21 1:55 PM, Christian König wrote:
Am 18.05.21 um 10:26 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses vmap functionality, and w
On 5/18/21 1:51 PM, Christian König wrote:
Am 18.05.21 um 10:26 schrieb Thomas Hellström:
i915 mock selftests are run without the device set up. In order to be
able
to run the region related mock selftests, export functions in order
for the
TTM range manager to be set up without a device to a
On Tue, May 18, 2021 at 10:30:25AM +0200, Simon Rettberg wrote:
> Am Thu, 13 May 2021 07:30:17 -0400
> schrieb Rodrigo Vivi :
>
> > On Thu, May 13, 2021 at 10:18:49AM +1000, Dave Airlie wrote:
> > > Reviewed-by: Dave Airlie
> > >
> > > Can we get this fix in, having a regression spanning 3 kerne
On 5/18/21 2:09 PM, Christian König wrote:
Am 18.05.21 um 14:04 schrieb Thomas Hellström:
On 5/18/21 1:55 PM, Christian König wrote:
Am 18.05.21 um 10:26 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses vmap functionality, and while it
probably might be possible to use it for
On Tue, 18 May 2021 at 12:17, Ville Syrjälä
wrote:
>
> On Tue, May 18, 2021 at 12:09:56PM +0100, Emil Velikov wrote:
> > Hi Ville,
> >
> > On Mon, 17 May 2021 at 18:24, Ville Syrjälä
> > wrote:
> > >
> > > On Sun, May 16, 2021 at 06:14:32PM +0100, Emil Velikov wrote:
> > > > From: Vivek Das Mohap
== Series Details ==
Series: drm/i915/reg: replace BIT() usage with REG_BIT()
URL : https://patchwork.freedesktop.org/series/90270/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10095 -> Patchwork_20143
Summary
---
*
On Fri, May 14, 2021 at 08:10:23PM -0700, Matt Roper wrote:
> From: Vandita Kulkarni
>
> On adlp the two mbuses have two display pipes and
> two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
> Mbus2. The Mbus can be joined and all the DBUFS can be
> used on Pipe A or B.
Reviewed-by: Stanislav
Op 18-05-2021 om 10:26 schreef Thomas Hellström:
> We are calling the eviction_valuable driver callback at eviction time to
> determine whether we actually can evict a buffer object.
> The upcoming i915 TTM backend needs the same functionality for swapout,
> and that might actually be beneficial to
1 - 100 of 160 matches
Mail list logo
