[Intel-gfx] ✗ Fi.CI.BAT: failure for Alder Lake-P Support (rev3)

== Series Details == Series: Alder Lake-P Support (rev3) URL : https://patchwork.freedesktop.org/series/89899/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10086 -> Patchwork_20133 Summary --- **FAILURE** Serious

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Alder Lake-P Support (rev3)

== Series Details == Series: Alder Lake-P Support (rev3) URL : https://patchwork.freedesktop.org/series/89899/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3)

== Series Details == Series: Alder Lake-P Support (rev3) URL : https://patchwork.freedesktop.org/series/89899/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1f1476bbdc3a drm/i915/xelpd: Enhanced pipe underrun reporting 0018489cbe17 drm/i915/xelpd: Support DP1.4 compression BPPs

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)

== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8) URL : https://patchwork.freedesktop.org/series/84754/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10083_full -> Patchwork_20128_full ===

[Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming

From: Vandita Kulkarni Update MBUS_CTL register if the 2 mbus can be joined as per the current DDB allocation and active pipes, also update hashing mode and pipe select bits as per the sequence mentioned in the bspec. Cc: Stanislav Lisovskiy Cc: José Roberto de Souza Signed-off-by: Vandita Ku

[Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support

From: Vandita Kulkarni On adlp the two mbuses have two display pipes and two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on Mbus2. The Mbus can be joined and all the DBUFS can be used on Pipe A or B. Bspec: 49255 Cc: Anusha Srivatsa Signed-off-by: Vandita Kulkarni Signed-off-by: Clinton Tayl

[Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization

From: José Roberto de Souza Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper Signed-off-by: José Roberto de Sou

[Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming

From: Anusha Srivatsa When scalers are enabled, we need to program underrun bubble counter to 0x50 to avoid Soft Pipe A underruns. Make sure other bits dont get overwritten. Cc: Matt Roper Cc: Clint Taylor Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: Clinton Taylor

[Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()

From: Gwan-gyeong Mun It removes intel_crtc_state from function argument of intel_psr_enable_source() in order to use intel_psr_enable_source() without intel_crtc_state on other psr internal functions. And we can get cpu_trancoder from intel_psr, therefore we don't need to pass intel_crtc_state t

[Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct

From: Gwan-gyeong Mun It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without intel_crtc_state on other psr internal function like as intel_psr_enable_source(). Cc: Ville Syrjälä Cc: José Roberto de

[Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets

From: Ville Syrjälä The dbuf slices are going to be split across several MBUS units. The actual dbuf programming will use offsets relative to the MBUS unit. To accommodate that we shall store the MBUS relative offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[]. For crtc_state->wm.sk

[Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support

From: Anusha Srivatsa The clocks in ALD_P is similar to that of TGL. The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL. This patch adds the helper function intel_mg_pll_enable_reg() which is similar to intel_combo_pll_enable_reg() for being lookup place for PLL_ENABLE register in combo phy c

[Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys

From: Anusha Srivatsa The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4. The first two are connected to combo phys while the rest are connected to TC phys. Cc: Matt Roper Cc: Clinton Taylor Cc: Lucas De Marchi Cc: Swathi Dhanavanthri Signed-off-by: Anusha Srivatsa Signed-off-by: Clinton Tay

[Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters

From: Anusha Srivatsa ADL_P has same memory characteristics as ADL_S platform. Bspec: 64631 Cc: José Roberto de Souza Cc: Clint Taylor Signed-off-by: Anusha Srivatsa Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed,

[Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL

From: Imre Deak On ADL_P besides programming the PLL accordingly the DP/HDMI link rate should be also programmed to the DDI_BUF_CTL register, do that. Cc: José Roberto de Souza Signed-off-by: Imre Deak Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++

[Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function

From: Gwan-gyeong Mun This introduces the following function that can enable and disable psr without intel_crtc_state/drm_connector_state when intel_psr is already enabled with current intel_crtc_state and drm_connector_state information. - intel_psr_pause(): Pause current PSR. it deactivates cu

[Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI

From: Mika Kahola Today when the DSI controller is paired with the Combo-PHY it uses the high-speed (HS) Word clock for its low power (LP) transmit PPI communication to the DPHY. The interface signaling only changes state at an Escape clock frequency (i.e. its effectively running on a virtual Tx

[Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function

From: Gwan-gyeong Mun In order to reuse code of PSR interrupt error check on other PSR functions, it adds psr_interrupt_error_check() function. Cc: José Roberto de Souza Signed-off-by: Gwan-gyeong Mun Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_psr.c | 47 +++

[Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation

From: Vandita Kulkarni Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by the VESA C model for DSC 1.1 v2: - Add include guard to header (Jani) - Move the big tables to a .c file (Chris, Jani, Lucas) v3: - Make tables 'static const' and add lookup functions to index into

[Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks

XE_LPD reduces the number of regular watermark latency levels from 8 to 6 on non-dgfx platforms. However the hardware also adds a special purpose SAGV wateramrk (and an accompanying transition watermark) that will be used by the hardware in place of the level 0 values during SAGV transitions. Bsp

[Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold

From: José Roberto de Souza On ADL-P TC cold is exited and blocked when legacy aux is powered, that is exacly the same of what ICL need for static TC ports. TODO: When a TBT hub or monitor is connected it will cause TBT and legacy aux to be powered at the same time, hopefully this will not cause

[Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables

From: Mika Kahola Define and use DP voltage swing and pre-emphasis translation tables for ADL-P. v2: - Update according to recent bspec updates; there are now separate tables for RBR/HBR and HBR2/HBR3. (Anusha) BSpec: 54956 Cc: Imre Deak Signed-off-by: Mika Kahola Signed-off-by: Clinton

[Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences

From: José Roberto de Souza ADL-P have basically the same TC connection and disconnection sequences as ICL and TGL, the major difference is the new registers. So here adding functions without the icl prefix in the name and making the new functions call the platform specific function to access th

[Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL

From: Manasi Navare On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield replacing the pipeline full and deprecating the pipeline override bit. This patch adds this corresponding bitfield in the register defs, crtc state vrr structure and populates this in vrr compute config and vrr ena

[Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters

From: Vandita Kulkarni Add methods to calculate rc parameters for all bpps, against the fixed arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444 formats. Our hw doesn't support YUV compression yet. The calculations used here are from VESA C model for DSC 1.1 v2: - Checkp

[Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting

XE_LPD brings enhanced underrun recovery: the hardware can somewhat mitigate underruns by using an interpolated replacement pixel (soft underrun) or the previous pixel (hard underrun). Furthermore, underruns can now be caused downstream by the port, even if the pipe itself is operating properly.

[Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs

From: Vandita Kulkarni Support compression BPPs from bpc to uncompressed BPP -1. So far we have 8,10,12 as valid compressed BPPS now the support is extended. Cc: Manasi Navare Signed-off-by: Vandita Kulkarni Signed-off-by: Matt Roper Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/displ

[Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support

Many of the ALD-P patches have received review and landed on drm-tip now. Let's rebase and resend the remaining patches that still need review (or have prereq patches that need review). Previous version of the series was https://patchwork.freedesktop.org/series/89899/#rev2 Aside from gen

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Another batch of reviewed XeLPD / ADL-P patches

On Sat, May 15, 2021 at 02:24:57AM +, Patchwork wrote: > == Series Details == > > Series: Another batch of reviewed XeLPD / ADL-P patches > URL : https://patchwork.freedesktop.org/series/90169/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10083_full -> Patchwork

[Intel-gfx] ✗ Fi.CI.IGT: failure for Another batch of reviewed XeLPD / ADL-P patches

== Series Details == Series: Another batch of reviewed XeLPD / ADL-P patches URL : https://patchwork.freedesktop.org/series/90169/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10083_full -> Patchwork_20127_full Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg1: Add HWMON power support

== Series Details == Series: drm/i915/dg1: Add HWMON power support URL : https://patchwork.freedesktop.org/series/90186/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10085 -> Patchwork_20132 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg1: Add HWMON power support

== Series Details == Series: drm/i915/dg1: Add HWMON power support URL : https://patchwork.freedesktop.org/series/90186/ State : warning == Summary == $ dim checkpatch origin/drm-tip 72896d03e908 drm/i915/dg1: Add HWMON power support -:22: WARNING:FILE_PATH_CHANGES: added, moved or deleted fil

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2)

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2) URL : https://patchwork.freedesktop.org/series/90184/ State : success == Summary == CI Bug Log - changes from CI_DRM_10085 -> Patchwork_20131

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2)

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2) URL : https://patchwork.freedesktop.org/series/90184/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be che

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2)

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2) URL : https://patchwork.freedesktop.org/series/90184/ State : warning == Summary == $ dim checkpatch origin/drm-tip acbf2a345c71 drm/i915/display: Fix fastsets involving PSR ff9e8e89

[Intel-gfx] [PATCH v3 1/1] drm/i915/dg1: Add HWMON power support

As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display power utilization. The following standard HWMON entries are currently supported (and appropriately scaled): /sys/class/drm/card0/device/hwmon/hwmon - energy1_input - power1_cap - power1

Re: [Intel-gfx] [PATCH] drm/i915: Fix a possible use of uninitialized variable in remap_io_sg()

On Fri, 2021-05-14 at 07:49 +0200, Christoph Hellwig wrote: > On Thu, May 13, 2021 at 04:28:41PM -0700, José Roberto de Souza wrote: > > If the do while loop breaks in 'if (!sg_dma_len(sgl))' in the first > > iteration, err is uninitialized causing a wrong call to zap_vma_ptes(). > > But scatterli

[Intel-gfx] [PATCH v3 0/1] drm/i915/dg1: Add HWMON power support

drm/i915/dg1: Add HWMON power support As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display power utilization. The following standard HWMON entries are currently supported (and appropriately scaled): /sys/class/drm/card0/device/hwmon/hwmon - energy1_input

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR URL : https://patchwork.freedesktop.org/series/90184/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10085 -> Patchwork_20130 ===

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR URL : https://patchwork.freedesktop.org/series/90184/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked se

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR

== Series Details == Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR URL : https://patchwork.freedesktop.org/series/90184/ State : warning == Summary == $ dim checkpatch origin/drm-tip f2ee45fe2883 drm/i915/display: Fix fastsets involving PSR 9b3671205d77 dr

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/dg1: Add HWMON power sensor support

On 2021-04-21 18:03:51, Jani Nikula wrote: > On Tue, 13 Apr 2021, Dale B Stimson wrote: > > As part of the System Managemenent Interface (SMI), use the HWMON > > subsystem to display power utilization. > > > > The following standard HWMON power sensors are currently supported > > (and appropriatel

[Intel-gfx] ✓ Fi.CI.BAT: success for Rename all CSR references to DMC (rev2)

== Series Details == Series: Rename all CSR references to DMC (rev2) URL : https://patchwork.freedesktop.org/series/90043/ State : success == Summary == CI Bug Log - changes from CI_DRM_10085 -> Patchwork_20129 Summary --- **SUCCESS*

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Nuke has_infoframe

Please ignore this series. Smaller and better one sent: https://patchwork.freedesktop.org/series/90184/ On Thu, 2021-05-13 at 22:28 -0700, José Roberto de Souza wrote: > This was only reduntant information has_hdmi_sink can do the same job. > set_infoframes() hooks will call intel_write_infoframe

[Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn off infoframes

intel_dp_set_infoframes() call in intel_ddi_post_disable_dp() will take care to disable all enabled infoframes. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/int

[Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled

When PSR is enabled it handles DP_SDP_VSC, changing revision and all the other fields as necessary. It can also enabled and disable this SDP as needed without a full modeset. So here masking DP_SDP_VSC bit when previous and future state PSR enabled, it will still be checked when comparing the aske

[Intel-gfx] [PATCH v2 3/4] drm/i915/display: Nuke has_infoframe

This was only reduntant information has_hdmi_sink can do the same job. set_infoframes() hooks will call intel_write_infoframe() for the supported infoframes types and it will only be enabled if given type is set in crtc_state->infoframes.enable. While at it also fixing the style of dig_port->set_i

[Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR

Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out") is not allowing fastsets to happen when PSR states changes but PSR is a feature that can be enabled and disabled during fastsets. So here moving the PSR pipe conf checks to a block that is only executed

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Rename all CSR references to DMC (rev2)

== Series Details == Series: Rename all CSR references to DMC (rev2) URL : https://patchwork.freedesktop.org/series/90043/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dmc.c:1: warning: 'DMC Support' not found ___

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Rename all CSR references to DMC (rev2)

== Series Details == Series: Rename all CSR references to DMC (rev2) URL : https://patchwork.freedesktop.org/series/90043/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gt/i

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rename all CSR references to DMC (rev2)

== Series Details == Series: Rename all CSR references to DMC (rev2) URL : https://patchwork.freedesktop.org/series/90043/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2614b89575a3 drm/i915/dmc: s/intel_csr/intel_dmc -:355: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be

[Intel-gfx] [PATCH 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC

No functional change. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 12 ++-- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 3/5] drm/i915/dmc: Rename macro names containing csr

Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 167 +- drivers/gpu/drm/i915/display/intel_csr.h | 6 +- .../drm/i915/display/intel_display_debugfs.c | 16 +- .../drm/i915/displ

[Intel-gfx] [PATCH 4/5] drm/i915/dmc: Rename functions names having "csr"

No functional change. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 64 +-- drivers/gpu/drm/i915/display/intel_csr.h | 10 +-- drivers/gpu/drm/i915/display/intel_display.c | 14 ++-- .../drm/i915/display/intel_display_po

[Intel-gfx] [PATCH 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h

Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- Documentation/gpu/i915.rst| 6 +++--- drivers/gpu/drm/i915/Makefile

[Intel-gfx] [PATCH 1/5] drm/i915/dmc: s/intel_csr/intel_dmc

No functional change. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 170 +- .../drm/i915/display/intel_display_debugfs.c | 14 +- .../drm/i915/display/intel_display_power.c| 52 +++--- drivers/gpu/drm/i915/display/intel

[Intel-gfx] [PATCH 0/5] Rename all CSR references to DMC

Currently in our driver we use both CSR and DMC interchangeably. Even though the spec mentions both, we do not follow that convention in the driver. Renaming all references of CSR to just be DMC. This hopefully makes the driver of this part a litlle less confusing. Suggested-by: Jani Nikula Ack

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups

== Series Details == Series: drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups URL : https://patchwork.freedesktop.org/series/90164/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10082_full -> Patchwork_20126_full Summary --

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Only select I2C_ALGOBIT for drivers that actually need it

== Series Details == Series: drm: Only select I2C_ALGOBIT for drivers that actually need it URL : https://patchwork.freedesktop.org/series/90163/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10082_full -> Patchwork_20125_full ==

Re: [Intel-gfx] [RFC PATCH 4/5] drm/i915: Introduce 'set parallel submit' extension

On Wed, May 12, 2021 at 10:34:59AM +0200, Daniel Vetter wrote: > On Tue, May 11, 2021 at 11:44:28AM -0700, Matthew Brost wrote: > > On Tue, May 11, 2021 at 05:11:44PM +0200, Daniel Vetter wrote: > > > On Thu, May 06, 2021 at 10:30:48AM -0700, Matthew Brost wrote: > > > > i915_drm.h updates for 'set

Re: [Intel-gfx] [PATCH 19/27] drm/i915/gem: Use the proto-context to handle create parameters

On Tue, May 4, 2021 at 3:33 PM Daniel Vetter wrote: > > On Mon, May 03, 2021 at 10:57:40AM -0500, Jason Ekstrand wrote: > > This means that the proto-context needs to grow support for engine > > configuration information as well as setparam logic. Fortunately, we'll > > be deleting a lot of setpa

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)

== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8) URL : https://patchwork.freedesktop.org/series/84754/ State : success == Summary == CI Bug Log - changes from CI_DRM_10083 -> Patchwork_20128 =

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)

== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8) URL : https://patchwork.freedesktop.org/series/84754/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)

== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8) URL : https://patchwork.freedesktop.org/series/84754/ State : warning == Summary == $ dim checkpatch origin/drm-tip 268e6a95dfed drm/i915/dpcd_bl: Remove redundant AUX backlight frequency

Re: [Intel-gfx] [PATCH 17/27] drm/i915/gem: Rework error handling in default_engines

On Tue, May 4, 2021 at 11:17 AM Daniel Vetter wrote: > > On Mon, May 03, 2021 at 10:57:38AM -0500, Jason Ekstrand wrote: > > Since free_engines works for partially constructed engine sets, we can > > use the usual goto pattern. > > > > Signed-off-by: Jason Ekstrand > > I guess subsequent patches

Re: [Intel-gfx] [PATCH 10/27] drm/i915/gem: Remove engine auto-magic with FENCE_SUBMIT

On Tue, May 4, 2021 at 3:56 AM Daniel Vetter wrote: > > On Mon, May 03, 2021 at 10:57:31AM -0500, Jason Ekstrand wrote: > > Even though FENCE_SUBMIT is only documented to wait until the request in > > the in-fence starts instead of waiting until it completes, it has a bit > > more magic than that.

[Intel-gfx] [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT

If we can't read DP_EDP_PWMGEN_BIT_COUNT in intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency defined in the VBT, we'll keep going in the function until we inevitably fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in doing this, so just return early.

[Intel-gfx] [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight

Since we're about to be moving this code into shared DRM helpers, we might as well start to cache certain backlight capabilities that can be determined from the EDP DPCD, and are likely to be relevant to the majority of drivers using said helpers. The main purpose of this is just to prevent every d

[Intel-gfx] [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers

Since we're about to implement eDP backlight support in nouveau using the standard protocol from VESA, we might as well just take the code that's already written for this and move it into a set of shared DRM helpers. Note that these helpers are intended to handle DPCD related backlight control bit

[Intel-gfx] [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau

This adds support for controlling panel backlights over eDP using VESA's standard backlight control interface. Luckily, Nvidia was cool enough to never come up with their own proprietary backlight control interface (at least, not any that I or the laptop manufacturers I've talked to are aware of),

[Intel-gfx] [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together

No functional changes, just move set_vesa_backlight_enable() closer to it's only caller: intel_dp_aux_vesa_enable_backlight(). Signed-off-by: Lyude Paul Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_dp_aux_backlight.c | 54 +-- 1 file changed, 27 insertions(+), 27 del

[Intel-gfx] [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures

Also, stop printing the DPCD register that failed, and just describe it instead. Saves us from having to look up each register offset when reading through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give us that anyway). Signed-off-by: Lyude Paul Reviewed-by: Rodrigo Vivi --- .

[Intel-gfx] [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit

Get rid of the extraneous switch case in here, and just open code edp_backlight_mode as we only ever use it once. v4: * Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin Signed-off-by: Lyude Paul Reviewed-by: Rodrigo Vivi --- ..

[Intel-gfx] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations

Noticed this while moving all of the VESA backlight code in i915 over to DRM helpers: it would appear that we calculate the frequency value we want to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never actually changes during runtime. So, let's simplify things by just caching thi

[Intel-gfx] [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly

This is kind of an annoying aspect of DRM's DP helpers: drm_dp_dpcd_readb/writeb() return the size of bytes read/written on success, thus we want to check against that instead of checking if the return value is less than 0. I'll probably be fixing this in the near future once I start doing DP work

[Intel-gfx] [PATCH v6 0/9] drm: Extract DPCD backlight helpers from i915, add support in nouveau

This series: * Cleans up i915's DPCD backlight code a little bit * Extracts i915's DPCD backlight code into a set of shared DRM helpers * Starts using those helpers in nouveau to add support to nouveau for DPCD backlight control v2 series-wide changes: * Rebase v3 series-wide changes: * Split up

Re: [Intel-gfx] [PATCH 06/27] drm/i915: Drop the CONTEXT_CLONE API

On Tue, May 4, 2021 at 3:50 AM Daniel Vetter wrote: > > On Mon, May 03, 2021 at 10:57:27AM -0500, Jason Ekstrand wrote: > > This API allows one context to grab bits out of another context upon > > creation. It can be used as a short-cut for setparam(getparam()) for > > things like I915_CONTEXT_PA

Re: [Intel-gfx] [PATCH 02/27] drm/i915: Stop storing the ring size in the ring pointer

On Tue, May 4, 2021 at 3:47 AM Daniel Vetter wrote: > > On Mon, May 03, 2021 at 10:57:23AM -0500, Jason Ekstrand wrote: > > Previously, we were storing the ring size in the ring pointer before it > > was actually allocated. We would then guard setting the ring size on > > checking for CONTEXT_ALL

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Move the TMDS clock division into intel_hdmi_mode_clock_valid()

On Fri, 2021-05-14 at 20:36 +0300, Ville Syrjälä wrote: > On Fri, May 14, 2021 at 05:28:40PM +, Souza, Jose wrote: > > On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Now that we have to tell intel_hdmi_mode_clock_valid() whether > > > we're askin

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Move the TMDS clock division into intel_hdmi_mode_clock_valid()

On Fri, May 14, 2021 at 05:28:40PM +, Souza, Jose wrote: > On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Now that we have to tell intel_hdmi_mode_clock_valid() whether > > we're asking about 4:4:4 or 4:2:0 output it can take care of > > the dotclock->

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Drop redundant has_hdmi_sink check

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > intel_hdmi_bpc_possible() will check has_hdmi_sink for us, so no > need to check it in intel_hdmi_mode_clock_valid() anymore. Reviewed-by: José Roberto de Souza > > Cc: Werner Sembach > Signed-off-by: Ville Syr

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Move platform checks into intel_hdmi_bpc_possible()

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Let's put the platform checks into intel_hdmi_bpc_possible() so that > it'll confirm both the source and sink capabilities. Reviewed-by: José Roberto de Souza > > Cc: Werner Sembach > Signed-off-by: Ville Syrjä

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Move has_hdmi_sink check into intel_hdmi_bpc_possible()

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > We wish intel_hdmi_bpc_possible() to consider whether the sink > supports HDMI or just DVI when checking whether it'll support > HDMI deep color or not. This also takes care of the "force DVI" > property. Reviewed-

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Check sink deep color capabilitis during HDMI .mode_valid()

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Currently HDMI .mode_valid() only checks whether the source can do > deep color. Let's check whether the sink can do it as well. > Reviewed-by: José Roberto de Souza > Cc: Werner Sembach > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Extract intel_hdmi_bpc_possible()

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Extract intel_hdmi_bpc_possible() from intel_hdmi_deep_color_possible() > so that we can reuse it for mode validation. > Reviewed-by: José Roberto de Souza > Cc: Werner Sembach > Signed-off-by: Ville Syrjälä >

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Move the TMDS clock division into intel_hdmi_mode_clock_valid()

On Tue, 2021-05-11 at 19:05 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Now that we have to tell intel_hdmi_mode_clock_valid() whether > we're asking about 4:4:4 or 4:2:0 output it can take care of > the dotclock->TMDS clock conversion. > > Cc: Werner Sembach > Signed-off-by: Ville Sy

Re: [Intel-gfx] [PATCH 3/3] drm/i915/panel: mass rename functions to have intel_panel_ prefix

On Wed, May 12, 2021 at 04:30:46PM +0300, Jani Nikula wrote: > Follow the usual naming conventions. Also pull HAS_GMCH() check to > intel_panel_fitting(). No functional changes. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- > drivers/gpu/drm/i915/di

[Intel-gfx] ✓ Fi.CI.BAT: success for Another batch of reviewed XeLPD / ADL-P patches

== Series Details == Series: Another batch of reviewed XeLPD / ADL-P patches URL : https://patchwork.freedesktop.org/series/90169/ State : success == Summary == CI Bug Log - changes from CI_DRM_10083 -> Patchwork_20127 Summary --- **

Re: [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915

On Fri, May 14, 2021 at 11:36:37AM -0500, Jason Ekstrand wrote: > On Fri, May 14, 2021 at 6:12 AM Tvrtko Ursulin > wrote: > > > > On 06/05/2021 20:13, Matthew Brost wrote: > > > Basic GuC submission support. This is the first bullet point in the > > > upstreaming plan covered in the following RFC

Re: [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915

On Fri, May 14, 2021 at 12:11:56PM +0100, Tvrtko Ursulin wrote: > > On 06/05/2021 20:13, Matthew Brost wrote: > > Basic GuC submission support. This is the first bullet point in the > > upstreaming plan covered in the following RFC [1]. > > > > At a very high level the GuC is a piece of firmware

Re: [Intel-gfx] thinkpad x1 carbon display flickering after update to 5.12. good on 5.11.x (i915)

Hello. On Fri, May 14, 2021 at 10:24:26AM +0200, Thomas Stein wrote: > After upgrading to linux 5.12 the display on my X1 Carbon Gen 2 starts to > flicker. Well actually it seems to turn off and on again and again. Here a > link to a video a person posted who has the same issue as me obviousely.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Another batch of reviewed XeLPD / ADL-P patches

== Series Details == Series: Another batch of reviewed XeLPD / ADL-P patches URL : https://patchwork.freedesktop.org/series/90169/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches

== Series Details == Series: Another batch of reviewed XeLPD / ADL-P patches URL : https://patchwork.freedesktop.org/series/90169/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc16ea52587b drm/i915/xelpd: Handle new location of outputs D and E 314d49aa2d02 drm/i915/xelpd: Incr

Re: [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915

On Fri, May 14, 2021 at 6:12 AM Tvrtko Ursulin wrote: > > On 06/05/2021 20:13, Matthew Brost wrote: > > Basic GuC submission support. This is the first bullet point in the > > upstreaming plan covered in the following RFC [1]. > > > > At a very high level the GuC is a piece of firmware which sits

Re: [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915

Pulling a few threads together... On Mon, May 10, 2021 at 1:39 PM Francisco Jerez wrote: > > I agree with Martin on this. Given that using GuC currently involves > making your open-source graphics stack rely on a closed-source > cryptographically-protected blob in order to submit commands to the

[Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership

From: José Roberto de Souza When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display has the control over the TC phy. The "not safe" naming is confusing using ownership make it easier to read also future platforms will have a new register that does the same job as DP_PHY_MODE_STATUS_NOT_SAF

[Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp

From: Vandita Kulkarni Move the platform specific max bpc calculation into intel_dp_dsc_compute_bpp function Cc: Manasi Navare Signed-off-by: Vandita Kulkarni Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_dp.c | 20 ++-- 1 file

[Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner

From: Animesh Manna No need for checking dsc flag for uncompressed pipe joiner mode validation. Cc: Manasi Navare Signed-off-by: Animesh Manna Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/i

[Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255

XE_LPD continues to use the same "skylake-style" watermark programming as other recent platforms. The only change to the watermark calculations compared to Display12 is that XE_LPD now allows a maximum of 255 lines vs the old limit of 31. Due to the larger possible lines value, the corresponding

[Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia

From: José Roberto de Souza Alderlake P have modular FIA like TGL but it is always modular in all skus, not like TGL that we had to read a register to check if it is monolithic or modular. BSpec: 55480 BSpec: 50572 Cc: Imre Deak Signed-off-by: José Roberto de Souza Signed-off-by: Clinton Taylo

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