Am 11.05.21 um 16:28 schrieb Thomas Hellström:
On 5/11/21 4:09 PM, Christian König wrote:
Am 11.05.21 um 16:06 schrieb Thomas Hellström (Intel):
On 5/11/21 3:58 PM, Christian König wrote:
Am 11.05.21 um 15:25 schrieb Thomas Hellström:
Most logical place to introduce TTM buffer objects is
On 11/05/2021 19:39, Matthew Brost wrote:
On Tue, May 11, 2021 at 08:26:59AM -0700, Bloomfield, Jon wrote:
-Original Message-
From: Martin Peres
Sent: Tuesday, May 11, 2021 1:06 AM
To: Daniel Vetter
Cc: Jason Ekstrand ; Brost, Matthew
; intel-gfx ;
dri-devel ; Ursulin, Tvrtko
; Ekstran
== Series Details ==
Series: CI pass for reviewed XeLPD / ADL-P patches (rev2)
URL : https://patchwork.freedesktop.org/series/90048/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10071 -> Patchwork_20107
Summary
---
== Series Details ==
Series: CI pass for reviewed XeLPD / ADL-P patches (rev2)
URL : https://patchwork.freedesktop.org/series/90048/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm
== Series Details ==
Series: CI pass for reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90048/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10071 -> Patchwork_20106
Summary
---
**FAILU
Hi all,
After merging the drm-misc tree, today's linux-next build (powerpc
allyesconfig) failed like this:
drivers/gpu/drm/nouveau/nouveau_connector.c: In function
'nouveau_connector_of_detect':
drivers/gpu/drm/nouveau/nouveau_connector.c:463:59: error: 'struct drm_device'
has no member named '
== Series Details ==
Series: CI pass for reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90048/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/d
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_po
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
From: Umesh Nerlige Ramappa
Enable relevant OA formats for ADL_P.
Cc: Ashutosh Dixit
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Clinton Taylor
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --g
From: Clinton Taylor
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
would assign the DDC pin map based on the PCH, but it can also change
based on the CPU. From Bspec 20124: "The physical port to pin pair
mapping are defined in the Bspec per PCH. Mapping can further change
XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.
v2:
- Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
property code will already prevent userspace from passing us values
Let's do a quick CI pass for the patches that have already been reviewed
so that we can go ahead and land them while we wait for reviews to roll
in on the remaining patches.
Clinton Taylor (1):
drm/i915/adl_p: Add PCH support
Matt Roper (5):
drm/i915/xelpd: Handle proper AUX interrupt bits
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Luca
If VT-d is active, the memory bandwidth usage of the display is 5%
higher. Take this into account when determining whether we can support
a display configuration.
Bspec: 64631
Cc: Matt Atwood
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bw.c |
On 2021.05.11 12:54:46 -0300, Jason Gunthorpe wrote:
> On Tue, May 11, 2021 at 04:33:30PM +0800, Zhenyu Wang wrote:
> > As kvmgt module contains all handling for VFIO/mdev, leaving mdev attribute
> > groups in gvt module caused dependency issue. Although it was there for
> > possible
> > other hyp
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_pm.c
between commit:
e7c6e405e171 ("Fix misc new gcc warnings")
from Linus' tree and commit:
c6deb5e97ded ("drm/i915/pm: Make the wm parameter of print_wm_latency a
pointer")
from the
Hi all,
Today's linux-next merge of the amdgpu tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
between commit:
c777dc9e7933 ("drm/ttm: move the page_alignment into the BO v2")
from the drm-misc tree and commit:
dd03daec0ff1 ("drm/amdgpu: restructure amdgpu_vram_mgr_
== Series Details ==
Series: Rename all CSR references to DMC
URL : https://patchwork.freedesktop.org/series/90043/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10071 -> Patchwork_20105
Summary
---
**FAILURE**
Se
== Series Details ==
Series: Rename all CSR references to DMC
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/display/intel_csr.c
Error: Cannot open file ./drivers/gp
== Series Details ==
Series: Rename all CSR references to DMC
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/intel_en
== Series Details ==
Series: Rename all CSR references to DMC
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
79e2c73a294f drm/i915/dmc: s/intel_csr/intel_dmc
-:355: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be writte
Finally, rename the header and source file from csr to dmc.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c
Currently in our driver we use both CSR and DMC interchangeably.
Even though the spec mentions both, we do not follow that convention
in the driver.
Renaming all references of CSR to just be DMC. This hopefully makes
the driver of this part a litlle less confusing.
Suggested-by: Jani Nikula
Anu
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 64 +--
drivers/gpu/drm/i915/display/intel_csr.h | 10 +--
drivers/gpu/drm/i915/display/intel_display.c | 14 ++--
.../drm/i915/display/intel_display_po
Rename all occurences of CSR_* with DMC_*
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 167 +-
drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 16 +-
.../drm/i915/displ
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 14 +++---
.../gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/gpu/drm/i915/i915_gpu_
No functional change.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 170 +-
.../drm/i915/display/intel_display_debugfs.c | 14 +-
.../drm/i915/display/intel_display_power.c| 52 +++---
drivers/gpu/drm/i915/display/intel
On 11.05.2021 17:16, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:13:34PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> New GuC firmware will unify format of MMIO and CTB H2G messages.
>> Introduce their definitions now to allow gradual transition of
>> our code to match new c
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev4)
URL : https://patchwork.freedesktop.org/series/89753/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10071 -> Patchwork_20104
=
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev4)
URL : https://patchwork.freedesktop.org/series/89753/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d0614da24cad drm/dp_mst: Use kH
== Series Details ==
Series: drm/doc/rfc: drop the i915_gem_lmem.h header
URL : https://patchwork.freedesktop.org/series/90040/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10071 -> Patchwork_20103
Summary
---
**FAI
== Series Details ==
Series: drm/doc/rfc: drop the i915_gem_lmem.h header
URL : https://patchwork.freedesktop.org/series/90040/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
098d9b88764e drm/doc/rfc: drop the i915_gem_lmem.h header
-:15: WARNING:FILE_PATH_CHANGES: added, moved
On Tue, May 11, 2021 at 07:43:30PM +0200, Daniel Vetter wrote:
> On Tue, May 11, 2021 at 10:01:28AM -0700, Matthew Brost wrote:
> > On Tue, May 11, 2021 at 05:26:34PM +0200, Daniel Vetter wrote:
> > > On Thu, May 06, 2021 at 12:13:57PM -0700, Matthew Brost wrote:
> > > > Add lrc descriptor context
On Sun, 2021-04-18 at 03:00 +, Patchwork wrote:
Patch Details
Series: series starting with [1/5] drm/i915/display: Fill PSR state during
hardware configuration read out
URL:https://patchwork.freedesktop.org/series/89204/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm
== Series Details ==
Series: drm/i915: Check HDMI sink deep color capabilities during .mode_valid()
URL : https://patchwork.freedesktop.org/series/90036/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10069 -> Patchwork_20102
On Tue, May 11, 2021 at 05:11:44PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 10:30:48AM -0700, Matthew Brost wrote:
> > i915_drm.h updates for 'set parallel submit' extension.
> >
> > Cc: Tvrtko Ursulin
> > Cc: Tony Ye
> > CC: Carl Zhang
> > Cc: Daniel Vetter
> > Cc: Jason Ekstrand
On Wed, 21 Apr 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Convert the get_buf_trans() functions into an encoder vfunc.
> Allows us to get rid of bunch of platform if-ladders.
>
> Signed-off-by: Ville Syrjälä
The series up to and including this patch,
Reviewed-by: Jani Nikula
> ---
On Mon, Apr 26, 2021 at 11:24:10PM +0800, Kai-Heng Feng wrote:
> On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX
> to discrete GFX after S3. This is not desirable, because userspace will
> treat connected display as a new one, losing display settings.
>
> The expected behav
On Tue, May 11, 2021 at 05:13:54PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 10:30:49AM -0700, Matthew Brost wrote:
> > Add I915_EXEC_NUMBER_BB_* to drm_i915_gem_execbuffer2.flags which allows
> > submitting N BBs per IOCTL.
> >
> > Cc: Tvrtko Ursulin
> > Cc: Tony Ye
> > CC: Carl Zha
On Tue, May 11, 2021 at 05:16:38PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:13:34PM -0700, Matthew Brost wrote:
> > From: Michal Wajdeczko
> >
> > New GuC firmware will unify format of MMIO and CTB H2G messages.
> > Introduce their definitions now to allow gradual transition of
>
On Tue, May 11, 2021 at 05:18:22PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:13:46PM -0700, Matthew Brost wrote:
> > Introduce i915_sched_engine object which is lower level data structure
> > that i915_scheduler / generic code can operate on without touching
> > execlist specific str
On Tue, May 11, 2021 at 04:49:58PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 10:30:46AM -0700, Matthew Brost wrote:
> > Add entry fpr i915 new parallel submission uAPI plan.
> >
> > Cc: Tvrtko Ursulin
> > Cc: Tony Ye
> > CC: Carl Zhang
> > Cc: Daniel Vetter
> > Cc: Jason Ekstrand
On Tue, May 11, 2021 at 10:12:32AM -0700, Matthew Brost wrote:
> On Tue, May 11, 2021 at 06:28:25PM +0200, Daniel Vetter wrote:
> > On Thu, May 06, 2021 at 12:14:28PM -0700, Matthew Brost wrote:
> > > We receive notification of an engine reset from GuC at its
> > > completion. Meaning GuC has poten
On Tue, May 11, 2021 at 10:01:28AM -0700, Matthew Brost wrote:
> On Tue, May 11, 2021 at 05:26:34PM +0200, Daniel Vetter wrote:
> > On Thu, May 06, 2021 at 12:13:57PM -0700, Matthew Brost wrote:
> > > Add lrc descriptor context lookup array which can resolve the
> > > intel_context from the lrc des
On Tue, May 11, 2021 at 07:28:08PM +0200, Daniel Vetter wrote:
> On Tue, May 11, 2021 at 06:03:56PM +0100, Matthew Auld wrote:
> > The proper headers have now landed in include/uapi/drm/i915_drm.h, so we
> > can drop i915_gem_lmem.h and instead just reference the real headers for
> > pulling in the
On Tue, May 11, 2021 at 06:03:56PM +0100, Matthew Auld wrote:
> The proper headers have now landed in include/uapi/drm/i915_drm.h, so we
> can drop i915_gem_lmem.h and instead just reference the real headers for
> pulling in the kernel doc.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev3)
URL : https://patchwork.freedesktop.org/series/89753/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10068 -> Patchwork_20101
=
On Tue, May 11, 2021 at 06:28:25PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:14:28PM -0700, Matthew Brost wrote:
> > We receive notification of an engine reset from GuC at its
> > completion. Meaning GuC has potentially cleared any HW state
> > we may have been interested in capturin
On Tue, May 11, 2021 at 05:26:34PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:13:57PM -0700, Matthew Brost wrote:
> > Add lrc descriptor context lookup array which can resolve the
> > intel_context from the lrc descriptor index. In addition to lookup, it
> > can determine in the lrc d
The proper headers have now landed in include/uapi/drm/i915_drm.h, so we
can drop i915_gem_lmem.h and instead just reference the real headers for
pulling in the kernel doc.
Suggested-by: Daniel Vetter
Signed-off-by: Matthew Auld
---
Documentation/gpu/rfc/i915_gem_lmem.h | 237
On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński wrote:
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. Unfortunately
> we need extend transition period and support relocations for two
> other igfx platforms -
From: "Kalamarz, Lukasz"
As a part of local memory effort we need to make sure, that
every available memory region is covered. This patch is an attempt
for this problem. If it will be accepted it will be replicated on
each test that can actually benefit from it.
Signed-off-by: Dominik Grzegorzek
From: Dominik Grzegorzek
As we need to add new test variants, convert the code to standard
igt_main format so those variants can be easily accommodated.
Signed-off-by: Janusz Krzysztofik
Signed-off-by: Zbigniew Kempczyński
---
tests/i915/gem_gpgpu_fill.c | 25 -
1 file
Just the really basic stuff, which unlocks adding more interesting testcases
later, like gem_lmem_swapping.
On the kernel side we landed the uAPI bits[1] behind CONFIG_BROKEN, which is
already enabled in CI builds, so it should be possible to get some more BAT
testing(outside of just the selftests
From: Andrzej Turko
Added stubs for memory regions to make upstreaming of tests which are
using this interface possible.
The memory region uapi implementation in the driver is not stable yet.
Thus, the full memory region interface cannot be used in lib. This
commit adds stubs for this uapi to be
From: Andrzej Turko
Add a wrapper for gem_create_ext ioctl (a version of gem_create that
accepts extensions). In preparation for the driver change implementing it,
a local definition of its id and necessary structs have been added,
which are to be erased as soon as those definitions
appear in the
From: Zbigniew Kempczyński
As with new memory region era we will have to cover different sets
of memory regions inside the tests this patch adds support for
generating subtest names according to passed memory region collection.
Signed-off-by: Zbigniew Kempczyński
Signed-off-by: José Roberto de
Add some explicit testcases for the create_ext placements extension.
Signed-off-by: Matthew Auld
Cc: Dominik Grzegorzek
Cc: Joonas Lahtinen
---
tests/i915/gem_create.c | 188
1 file changed, 188 insertions(+)
diff --git a/tests/i915/gem_create.c b/test
From: Lukasz Kalamarz
With an introduction of Local Memory concept we should be able to
allocate object in specific memory region. This patch implements
helper functions that allow this.
Signed-off-by: Lukasz Kalamarz
Cc: Janulgue Abdiel
Cc: Matthew Auld
Cc: Michal Winiarski
Cc: Katarzyna De
From: Andrzej Turko
Converted the test gem_gpgpu_fill to use memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
---
tests/i915/gem_gpgpu_fill.c | 42 ++---
1 file changed, 34 insertions(+), 8 del
From: Andrzej Turko
Erase definitions from intel_memory_region.h and change the procedures
to operate on objects defined in i915_drm.h instead. Those objects
were defined in intel_memory_region.h in order to upstream memory region
stubs before the original definitions from i915_drm.h.
Modify tes
From: Andrzej Turko
Converted the test gem_media_fill to use memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
---
tests/i915/gem_media_fill.c | 57 -
1 file changed, 44 insertions(+), 13 de
Sync to get gem_create_ext and the regions query stuff.
Signed-off-by: Matthew Auld
---
include/drm-uapi/i915_drm.h | 394
1 file changed, 360 insertions(+), 34 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index bf9ea47
From: Andrzej Turko
Converted the test gem_exec_basic to use the memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
---
tests/i915/gem_exec_basic.c | 50 +
1 file changed, 34 insertions(+), 1
On Mon, May 10, 2021 at 11:03 PM Christoph Hellwig wrote:
>
> > +static inline struct io_tlb_mem *get_io_tlb_mem(struct device *dev)
> > +{
> > +#ifdef CONFIG_DMA_RESTRICTED_POOL
> > + if (dev && dev->dma_io_tlb_mem)
> > + return dev->dma_io_tlb_mem;
> > +#endif /* CONFIG_DMA_RESTR
== Series Details ==
Series: series starting with [v1,1/1] drm/dp_mst: Use kHz as link rate units
when settig source max link caps at init (rev3)
URL : https://patchwork.freedesktop.org/series/89753/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b289f6f63caf drm/dp_mst: Use kH
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM
URL : https://patchwork.freedesktop.org/series/90022/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10068 -> Patchwork_20100
Summary
---
On Tue, May 11, 2021 at 08:26:59AM -0700, Bloomfield, Jon wrote:
> > -Original Message-
> > From: Martin Peres
> > Sent: Tuesday, May 11, 2021 1:06 AM
> > To: Daniel Vetter
> > Cc: Jason Ekstrand ; Brost, Matthew
> > ; intel-gfx ;
> > dri-devel ; Ursulin, Tvrtko
> > ; Ekstrand, Jason ;
>
On Mon, May 10, 2021 at 11:03 PM Christoph Hellwig wrote:
>
> > +#ifdef CONFIG_DMA_RESTRICTED_POOL
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#endif
>
> I don't think any of this belongs into swiotlb.c. Marking
> swiotlb_init_io_tlb_mem non-static and having a
On Mon, May 10, 2021 at 11:05 PM Christoph Hellwig wrote:
>
> > +static inline bool is_dev_swiotlb_force(struct device *dev)
> > +{
> > +#ifdef CONFIG_DMA_RESTRICTED_POOL
> > + if (dev->dma_io_tlb_mem)
> > + return true;
> > +#endif /* CONFIG_DMA_RESTRICTED_POOL */
> > + return
On Tue, May 11, 2021 at 05:37:54PM +0200, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 12:14:03PM -0700, Matthew Brost wrote:
> > Disable engine barriers for unpinning with GuC. This feature isn't
> > needed with the GuC as it disables context scheduling before unpinning
> > which guarantees the
On Thu, May 06, 2021 at 12:14:28PM -0700, Matthew Brost wrote:
> We receive notification of an engine reset from GuC at its
> completion. Meaning GuC has potentially cleared any HW state
> we may have been interested in capturing. GuC resumes scheduling
> on the engine post-reset, as the resets are
On Thu, May 06, 2021 at 12:14:22PM -0700, Matthew Brost wrote:
> GuC will issue a reset on detecting an engine hang and will notify
> the driver via a G2H message. The driver will service the notification
> by resetting the guilty context to a simple state or banning it
> completely.
>
> Cc: Matth
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM
URL : https://patchwork.freedesktop.org/series/90022/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/d
== Series Details ==
Series: drm/i915: Move LMEM (VRAM) management over to TTM
URL : https://patchwork.freedesktop.org/series/90022/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7c8e78644333 drm/i915: Untangle the vma pages_mutex
e148e51b2187 drm/i915: Don't free shared locks
== Series Details ==
Series: drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON
(rev3)
URL : https://patchwork.freedesktop.org/series/89639/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10068 -> Patchwork_20099
=
From: Ville Syrjälä
Now that we have to tell intel_hdmi_mode_clock_valid() whether
we're asking about 4:4:4 or 4:2:0 output it can take care of
the dotclock->TMDS clock conversion.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++---
1 file
From: Ville Syrjälä
We wish intel_hdmi_bpc_possible() to consider whether the sink
supports HDMI or just DVI when checking whether it'll support
HDMI deep color or not. This also takes care of the "force DVI"
property.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/d
From: Ville Syrjälä
intel_hdmi_bpc_possible() will check has_hdmi_sink for us, so no
need to check it in intel_hdmi_mode_clock_valid() anymore.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 ++
1 file changed, 10 inserti
From: Ville Syrjälä
Currently HDMI .mode_valid() only checks whether the source can do
deep color. Let's check whether the sink can do it as well.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +---
1 file changed, 9 insertions(
From: Ville Syrjälä
Let's put the platform checks into intel_hdmi_bpc_possible() so that
it'll confirm both the source and sink capabilities.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +++--
1 file changed, 7 insertions(+), 6 de
From: Ville Syrjälä
Extract intel_hdmi_bpc_possible() from intel_hdmi_deep_color_possible()
so that we can reuse it for mode validation.
Cc: Werner Sembach
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 46 +--
1 file changed, 27 insertions(+)
From: Ville Syrjälä
I just realized we're not chekcking the HDMI sink's deep color
capabilities during .mode_valid(). That can lead us to not filter
out modes that we can't actually support. Let's try to remedy that.
Entire series available here:
git://github.com/vsyrjala/linux.git hdmi_dc_check
On Thu, May 06, 2021 at 12:14:03PM -0700, Matthew Brost wrote:
> Disable engine barriers for unpinning with GuC. This feature isn't
> needed with the GuC as it disables context scheduling before unpinning
> which guarantees the HW will not reference the context. Hence it is
> not necessary to defer
> -Original Message-
> From: Martin Peres
> Sent: Tuesday, May 11, 2021 1:06 AM
> To: Daniel Vetter
> Cc: Jason Ekstrand ; Brost, Matthew
> ; intel-gfx ;
> dri-devel ; Ursulin, Tvrtko
> ; Ekstrand, Jason ;
> Ceraolo Spurio, Daniele ; Bloomfield, Jon
> ; Vetter, Daniel ;
> Harrison, John C
On Thu, May 06, 2021 at 12:13:57PM -0700, Matthew Brost wrote:
> Add lrc descriptor context lookup array which can resolve the
> intel_context from the lrc descriptor index. In addition to lookup, it
> can determine in the lrc descriptor context is currently registered with
> the GuC by checking if
On Thu, May 06, 2021 at 12:13:46PM -0700, Matthew Brost wrote:
> Introduce i915_sched_engine object which is lower level data structure
> that i915_scheduler / generic code can operate on without touching
> execlist specific structures. This allows additional submission backends
> to be added witho
On Thu, May 06, 2021 at 12:13:34PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> New GuC firmware will unify format of MMIO and CTB H2G messages.
> Introduce their definitions now to allow gradual transition of
> our code to match new changes.
>
> Signed-off-by: Michal Wajdeczko
> Si
On Thu, May 06, 2021 at 10:30:49AM -0700, Matthew Brost wrote:
> Add I915_EXEC_NUMBER_BB_* to drm_i915_gem_execbuffer2.flags which allows
> submitting N BBs per IOCTL.
>
> Cc: Tvrtko Ursulin
> Cc: Tony Ye
> CC: Carl Zhang
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Signed-off-by: Matthew Brost
On Tue, May 11, 2021 at 03:58:43PM +0100, Daniel Stone wrote:
> Hi,
>
> On Tue, 11 May 2021 at 15:34, Daniel Vetter wrote:
> > On Thu, May 06, 2021 at 10:30:45AM -0700, Matthew Brost wrote:
> > > +No major changes are required to the uAPI for basic GuC submission. The
> > > only
> > > +change is
On Thu, May 06, 2021 at 10:30:48AM -0700, Matthew Brost wrote:
> i915_drm.h updates for 'set parallel submit' extension.
>
> Cc: Tvrtko Ursulin
> Cc: Tony Ye
> CC: Carl Zhang
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Signed-off-by: Matthew Brost
> ---
> include/uapi/drm/i915_drm.h | 126 ++
Hi,
On Tue, 11 May 2021 at 15:34, Daniel Vetter wrote:
> On Thu, May 06, 2021 at 10:30:45AM -0700, Matthew Brost wrote:
> > +No major changes are required to the uAPI for basic GuC submission. The
> > only
> > +change is a new scheduler attribute:
> > I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP.
> >
On Thu, May 06, 2021 at 10:30:47AM -0700, Matthew Brost wrote:
> Expose logical engine instance to user via query engine info IOCTL. This
> is required for split-frame workloads as these need to be placed on
> engines in a logically contiguous order. The logical mapping can change
> based on fusing
On Thu, May 06, 2021 at 10:30:46AM -0700, Matthew Brost wrote:
> Add entry fpr i915 new parallel submission uAPI plan.
>
> Cc: Tvrtko Ursulin
> Cc: Tony Ye
> CC: Carl Zhang
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Signed-off-by: Matthew Brost
> ---
> Documentation/gpu/rfc/i915_scheduler.r
On Thu, May 06, 2021 at 10:30:45AM -0700, Matthew Brost wrote:
> Add entry for i915 GuC submission / DRM scheduler integration plan.
> Follow up patch with details of new parallel submission uAPI to come.
>
> Cc: Jon Bloomfield
> Cc: Jason Ekstrand
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: J
On Mon, May 10, 2021 at 03:33:46PM +0200, Werner Sembach wrote:
> When encoder validation of a display mode fails, retry with less bandwidth
> heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
> to support 4k60Hz output, which previously failed silently.
>
> AMDGPU had nea
On 5/11/21 4:09 PM, Christian König wrote:
Am 11.05.21 um 16:06 schrieb Thomas Hellström (Intel):
On 5/11/21 3:58 PM, Christian König wrote:
Am 11.05.21 um 15:25 schrieb Thomas Hellström:
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add so
Am 11.05.21 um 16:06 schrieb Thomas Hellström (Intel):
On 5/11/21 3:58 PM, Christian König wrote:
Am 11.05.21 um 15:25 schrieb Thomas Hellström:
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality lik
On 5/11/21 3:58 PM, Christian König wrote:
Am 11.05.21 um 15:25 schrieb Thomas Hellström:
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we
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