[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Fix state mismatch in drm infoframe (rev3)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Fix state mismatch in drm infoframe (rev3) URL : https://patchwork.freedesktop.org/series/89225/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function param

Re: [Intel-gfx] [PATCH v4] drm/doc/rfc: i915 DG1 uAPI

2021-04-22 Thread Dave Airlie
On Tue, 20 Apr 2021 at 02:45, Matthew Auld wrote: > > Add an entry for the new uAPI needed for DG1. Also add the overall > upstream plan, including some notes for the TTM conversion. > > v2(Daniel): > - include the overall upstreaming plan > - add a note for mmap, there are differences here fo

[Intel-gfx] [V3] drm/i915/display: Fix state mismatch in drm infoframe

2021-04-22 Thread Bhanuprakash Modem
While reading the SDP infoframe, we are getting filtered with the encoder type INTEL_OUTPUT_DDI which causes the infoframe mismatch. This patch will drop encoder->type check as we can mask individual infoframe type. [1025.606556] i915 :00:02.0: [drm] *ERROR* mismatch in drm infoframe [1025.607

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : success == Summary == CI Bug Log - changes from CI_DRM_1 -> Patchwork_19978 ==

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Fu

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops (rev2) URL : https://patchwork.freedesktop.org/series/89374/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5f3807d8462e drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation lapto

[Intel-gfx] [PATCH v2] drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops

2021-04-22 Thread Kai-Heng Feng
On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX to discrete GFX after S3. This is not desirable, because userspace will treat connected display as a new one, losing display settings. The expected behavior is to let discrete GFX drives all external displays. The platform in

Re: [Intel-gfx] [PATCH] vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV

2021-04-22 Thread Zhenyu Wang
On 2021.04.22 10:58:10 -0300, Jason Gunthorpe wrote: > On Thu, Apr 22, 2021 at 03:35:33PM +0200, Arnd Bergmann wrote: > > From: Arnd Bergmann > > > > The Kconfig dependency is incomplete since DRM_I915_GVT is a 'bool' > > symbol that depends on the 'tristate' VFIO_MDEV. This allows a > > configur

Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-22 Thread Lyude Paul
On Thu, 2021-04-22 at 18:33 -0400, Lyude Paul wrote: > OK - talked with Ville a bit on this and did some of my own research, I > actually think that moving i2c to drm_dp_aux_init() is the right decision > for > the time being. The reasoning behind this being that as shown by my previous > work of f

Re: [Intel-gfx] [PATCH v5 16/16] of: Add plumbing for restricted DMA pool

2021-04-22 Thread Claire Chang
On Thu, Apr 22, 2021 at 4:17 PM Claire Chang wrote: > > If a device is not behind an IOMMU, we look up the device node and set > up the restricted DMA when the restricted-dma-pool is presented. > > Signed-off-by: Claire Chang > --- > drivers/of/address.c| 25 + > driv

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2) URL : https://patchwork.freedesktop.org/series/89379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19977_full Summary -

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2) URL : https://patchwork.freedesktop.org/series/89379/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19977 Summary --- **SU

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/fbc: Avoid GLK+ FBC corruption (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption (rev2) URL : https://patchwork.freedesktop.org/series/89379/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or membe

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: Avoid GLK+ FBC corruption

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption URL : https://patchwork.freedesktop.org/series/89379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19976_full Summary --- *

Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-22 Thread Lyude Paul
OK - talked with Ville a bit on this and did some of my own research, I actually think that moving i2c to drm_dp_aux_init() is the right decision for the time being. The reasoning behind this being that as shown by my previous work of fixing drivers that call drm_dp_aux_register() too early - it se

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2) URL : https://patchwork.freedesktop.org/series/89348/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19974_full =

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make preempt timeout for banned contexts configurable

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998_full -> Patchwork_19973_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Avoid GLK+ FBC corruption

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption URL : https://patchwork.freedesktop.org/series/89379/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19976 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/fbc: Avoid GLK+ FBC corruption

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/fbc: Avoid GLK+ FBC corruption URL : https://patchwork.freedesktop.org/series/89379/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww'

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

2021-04-22 Thread Ville Syrjälä
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote: > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Currently we try to detect a symmetric memory configurations > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is > > either

[Intel-gfx] [PATCH 1/2] drm/i915/fbc: Don't nuke manually around flips

2021-04-22 Thread Ville Syrjala
From: Ville Syrjälä Apparently we have discovered another way to hit the dreaded top of screen FBC corruption on GLK. Previously we thought it was limited to some combination of FBC nuke+disable+plane update during the same frame, for which we have the extra vblank wait as a workaround. But looks

[Intel-gfx] [PATCH 2/2] drm/i915: Remove redundant DIRTYFB frontbuffer flushes

2021-04-22 Thread Ville Syrjala
From: Ville Syrjälä The frontbuffer tracking code is supposed to handle plane updates via ORIGIN_FLIP. Right now we're also doing internal ORIGIN_DIRTYFB flushes for some reason. Can't see the point so get rid of them. In fact on GLK+ these are acively harmful and only risk angering the hardware

[Intel-gfx] [PATCH 0/2] drm/i915/fbc: Avoid GLK+ FBC corruption

2021-04-22 Thread Ville Syrjala
From: Ville Syrjälä Remove redundant manual FBC nukes to avoid the GLK+ FBC nuke+disable+plane update fail and causing the top of the screen to become corrupted. A 100% workaround likely needs yet another vblank wait, but that's not entirely trivial to do without hurting interactivity, so for now

Re: [Intel-gfx] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-22 Thread Lyude Paul
On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > The init vs. register split is intentional. Registering the thing > and allowing userspace access to it before the rest of the driver > is ready isn't particularly great. For a while now we've tried to > move towards an architecture where

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops URL : https://patchwork.freedesktop.org/series/89374/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/gen

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2) URL : https://patchwork.freedesktop.org/series/89348/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19974 ===

Re: [Intel-gfx] [PULL] drm-misc-next-fixes

2021-04-22 Thread Alex Deucher
On Thu, Apr 22, 2021 at 12:33 PM Maxime Ripard wrote: > > Hi Dave, Daniel, > > Here's this week drm-misc-next-fixes PR, for the next merge window > Can we also cherry-pick this patch: https://cgit.freedesktop.org/drm/drm-misc/commit/?id=d510c88cfbb294d2b1e2d0b71576e9b79d0e2e83 It should have real

[Intel-gfx] [PULL] drm-misc-next-fixes

2021-04-22 Thread Maxime Ripard
Hi Dave, Daniel, Here's this week drm-misc-next-fixes PR, for the next merge window Thanks! Maxime drm-misc-next-fixes-2021-04-22: A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 (rev2) URL : https://patchwork.freedesktop.org/series/89348/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning

[Intel-gfx] [PATCH] drm/i915: Invoke BXT _DSM to enable MUX on HP Workstation laptops

2021-04-22 Thread Kai-Heng Feng
On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX to discrete GFX after S3. This is not desirable, because userspace will treat connected display as a new one, losing display settings. The expected behavior is to let discrete GFX drives all external displays. The platform in

Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Mun, Gwan-gyeong
On Thu, 2021-04-22 at 07:39 -0700, Souza, Jose wrote: > On Thu, 2021-04-22 at 12:54 +0300, Gwan-gyeong Mun wrote: > > TGL PSR2 hardware tracking shows momentary flicker and screen shift > > if > > TGL Display stepping is B1 from A0. > > It has been fixed from TGL Display stepping C0. > > > > HSDES

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Souza, Jose
On Thu, 2021-04-22 at 19:05 +0300, Gwan-gyeong Mun wrote: > TGL PSR2 hardware tracking shows momentary flicker and screen shift if > TGL Display stepping is B1 from A0. > It has been fixed from TGL Display stepping C0. > > HSDES: 18015970021 > HSDES: 2209313811 > BSpec: 55378 > > v2: Add checking

[Intel-gfx] [PATCH v2] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Gwan-gyeong Mun
TGL PSR2 hardware tracking shows momentary flicker and screen shift if TGL Display stepping is B1 from A0. It has been fixed from TGL Display stepping C0. HSDES: 18015970021 HSDES: 2209313811 BSpec: 55378 v2: Add checking of PSR2 manual tracking (Jose) Cc: José Roberto de Souza Signed-off-by: G

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make preempt timeout for banned contexts configurable

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : success == Summary == CI Bug Log - changes from CI_DRM_9998 -> Patchwork_19973 Summar

[Intel-gfx] [PULL] drm-intel-fixes

2021-04-22 Thread Rodrigo Vivi
Hi Dave and Daniel, One GVT fix and one display link training fix targeting stable 5.11. Here goes drm-intel-fixes-2021-04-22: - GVT's BDW regression fix for cmd parser (Zhenyu) - Fix modesetting in case of unexpected AUX timeouts (Imre) Thanks, Rodrigo. The following changes since commit bf05b

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Make preempt timeout for banned contexts configurable

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function pa

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 URL : https://patchwork.freedesktop.org/series/89348/ State : success == Summary == CI Bug Log - changes from CI_DRM_9997_full -> Patchwork_19972_full =

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make preempt timeout for banned contexts configurable

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915: Make preempt timeout for banned contexts configurable URL : https://patchwork.freedesktop.org/series/89369/ State : warning == Summary == $ dim checkpatch origin/drm-tip d5c87e77c34a drm/i915: Make preempt timeout for banned contexts configurable -:130: C

[Intel-gfx] [PATCH] drm/i915: Make preempt timeout for banned contexts configurable

2021-04-22 Thread Tvrtko Ursulin
From: Tvrtko Ursulin When we ban a context, for instance when userspace marked itself as non- persistent and has exited, we apply a 1ms grace period after which any belonging workload still on the GPU (did not preempt) will be forcibly terminated (using engine reset). For some workloads period b

Re: [Intel-gfx] [PATCH] vfio/gvt: fix DRM_I915_GVT dependency on VFIO_MDEV

2021-04-22 Thread Jani Nikula
Cc: gvt list & maintainers On Thu, 22 Apr 2021, Jason Gunthorpe wrote: > On Thu, Apr 22, 2021 at 03:35:33PM +0200, Arnd Bergmann wrote: >> From: Arnd Bergmann >> >> The Kconfig dependency is incomplete since DRM_I915_GVT is a 'bool' >> symbol that depends on the 'tristate' VFIO_MDEV. This all

Re: [Intel-gfx] [PATCH v2] drm/i915: Simplify CCS and UV plane alignment handling

2021-04-22 Thread Juha-Pekka Heikkila
look ok to me. Reviewed-by: Juha-Pekka Heikkila On 21.4.2021 20.32, Imre Deak wrote: We can handle the surface alignment of CCS and UV color planes for all modifiers at one place, so do this. An AUX color plane can be a CCS or a UV plane, use only the more specific query functions and remove i

Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Souza, Jose
On Thu, 2021-04-22 at 12:54 +0300, Gwan-gyeong Mun wrote: > TGL PSR2 hardware tracking shows momentary flicker and screen shift if > TGL Display stepping is B1 from A0. > It has been fixed from TGL Display stepping C0. > > HSDES: 18015970021 > HSDES: 2209313811 > BSpec: 55378 > > Cc: José Roberto

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

2021-04-22 Thread Ville Syrjälä
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote: > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Currently we try to detect a symmetric memory configurations > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is > > either

Re: [Intel-gfx] [PATCH v3 01/20] drm/amdgpu: Add error handling to amdgpu_dm_initialize_dp_connector()

2021-04-22 Thread Mikita Lipski
Thanks for the change! Reviewed-by: Mikita Lipski On 2021-04-19 6:55 p.m., Lyude Paul wrote: While working on moving i2c device registration into drm_dp_aux_init() - I realized that in order to do so we need to make sure that drivers calling drm_dp_aux_init() handle any errors it could possibl

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 URL : https://patchwork.freedesktop.org/series/89348/ State : success == Summary == CI Bug Log - changes from CI_DRM_9997 -> Patchwork_19972 S

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE

2021-04-22 Thread Mun, Gwan-gyeong
Looks good to me. Reviewed-by: Gwan-gyeong Mun On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: > EDP_Y_COORDINATE_ENABLE became a reserved register in display 13. > EDP_Y_COORDINATE_VALID have the same fate as EDP_Y_COORDINATE_ENABLE > but as we don't need it, removing the macro

Re: [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec

2021-04-22 Thread Mun, Gwan-gyeong
The changed name looks more accurate to the edp 1.4b spec. Looks good to me. Reviewed-by: Gwan-gyeong Mun On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: > DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture > Indication" in eDP spec has a ambiguous name, so renami

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0 URL : https://patchwork.freedesktop.org/series/89348/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Functi

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Fix state mismatch in drm infoframe (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Fix state mismatch in drm infoframe (rev2) URL : https://patchwork.freedesktop.org/series/89225/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9997 -> Patchwork_19971 Summary -

[Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0

2021-04-22 Thread Gwan-gyeong Mun
TGL PSR2 hardware tracking shows momentary flicker and screen shift if TGL Display stepping is B1 from A0. It has been fixed from TGL Display stepping C0. HSDES: 18015970021 HSDES: 2209313811 BSpec: 55378 Cc: José Roberto de Souza Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

2021-04-22 Thread Daniel Vetter
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Currently we try to detect a symmetric memory configurations > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is > either only set on a very specific subset of machines or it > just does not exist

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Fix state mismatch in drm infoframe (rev2)

2021-04-22 Thread Patchwork
== Series Details == Series: drm/i915/display: Fix state mismatch in drm infoframe (rev2) URL : https://patchwork.freedesktop.org/series/89225/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function param

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA

2021-04-22 Thread Patchwork
== Series Details == Series: Restricted DMA URL : https://patchwork.freedesktop.org/series/89341/ State : failure == Summary == Applying: swiotlb: Fix the type of index error: sha1 information is lacking or useless (kernel/dma/swiotlb.c). error: could not build fake ancestor hint: Use 'git am

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec

2021-04-22 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec URL : https://patchwork.freedesktop.org/series/89328/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9995_full -> Patchwork_19969_full ==

[Intel-gfx] [V2] drm/i915/display: Fix state mismatch in drm infoframe

2021-04-22 Thread Bhanuprakash Modem
While reading the SDP infoframe, we are getting filtered with the encoder type INTEL_OUTPUT_DDI which causes the infoframe mismatch. This patch will drop encoder->type check as we can mask individual infoframe type. [1025.606556] i915 :00:02.0: [drm] *ERROR* mismatch in drm infoframe [1025.607

Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties

2021-04-22 Thread Simon Ser
On Thursday, April 22nd, 2021 at 10:54 AM, Hans de Goede wrote: > I guess Marco was waiting for the kernel bits too land before submitting > these, > but I agree that it would probably be good to have these submitted now, we > can mark them as WIP to avoid them getting merged before the kernel

Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties

2021-04-22 Thread Hans de Goede
Hi, On 4/22/21 10:51 AM, Simon Ser wrote: > Hi, > > On Wednesday, April 21st, 2021 at 10:47 PM, Hans de Goede > wrote: > >> There now is GNOME userspace code using the new properties: >> https://hackmd.io/@3v1n0/rkyIy3BOw > > Thanks for working on this. > > Can these patches be submitted as

Re: [Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties

2021-04-22 Thread Simon Ser
Hi, On Wednesday, April 21st, 2021 at 10:47 PM, Hans de Goede wrote: > There now is GNOME userspace code using the new properties: > https://hackmd.io/@3v1n0/rkyIy3BOw Thanks for working on this. Can these patches be submitted as merge requests against the upstream projects? It would be nice

Re: [Intel-gfx] [PATCH] drm/i915: Fix docbook descriptions for i915_cmd_parser

2021-04-22 Thread Daniel Vetter
On Wed, Apr 21, 2021 at 04:39:10PM +0200, Maarten Lankhorst wrote: > Op 21-04-2021 om 16:32 schreef Daniel Vetter: > > On Wed, Apr 21, 2021 at 2:03 PM Maarten Lankhorst > > wrote: > >> Fixes the following htmldocs warnings: > >> drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function

[Intel-gfx] [PATCH v5 16/16] of: Add plumbing for restricted DMA pool

2021-04-22 Thread Claire Chang
If a device is not behind an IOMMU, we look up the device node and set up the restricted DMA when the restricted-dma-pool is presented. Signed-off-by: Claire Chang --- drivers/of/address.c| 25 + drivers/of/device.c | 3 +++ drivers/of/of_private.h | 5 + 3

[Intel-gfx] [PATCH v5 15/16] dt-bindings: of: Add restricted DMA pool

2021-04-22 Thread Claire Chang
Introduce the new compatible string, restricted-dma-pool, for restricted DMA. One can specify the address and length of the restricted DMA memory region by restricted-dma-pool in the reserved-memory node. Signed-off-by: Claire Chang --- .../reserved-memory/reserved-memory.txt | 24

[Intel-gfx] [PATCH v5 14/16] dma-direct: Allocate memory from restricted DMA pool if available

2021-04-22 Thread Claire Chang
The restricted DMA pool is preferred if available. The restricted DMA pools provide a basic level of protection against the DMA overwriting buffer contents at unexpected times. However, to protect against general data leakage and system memory corruption, the system needs to provide a way to lock

[Intel-gfx] [PATCH v5 13/16] swiotlb: Add restricted DMA alloc/free support.

2021-04-22 Thread Claire Chang
Add the functions, swiotlb_{alloc,free} to support the memory allocation from restricted DMA pool. Signed-off-by: Claire Chang --- include/linux/swiotlb.h | 4 kernel/dma/swiotlb.c| 35 +-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/

[Intel-gfx] [PATCH v5 12/16] dma-direct: Add a new wrapper __dma_direct_free_pages()

2021-04-22 Thread Claire Chang
Add a new wrapper __dma_direct_free_pages() that will be useful later for swiotlb_free(). Signed-off-by: Claire Chang --- kernel/dma/direct.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index 7a88c34d0867..7a27f051

[Intel-gfx] [PATCH v5 11/16] swiotlb: Refactor swiotlb_tbl_unmap_single

2021-04-22 Thread Claire Chang
Add a new function, release_slots, to make the code reusable for supporting different bounce buffer pools, e.g. restricted DMA pool. Signed-off-by: Claire Chang --- kernel/dma/swiotlb.c | 35 --- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/kern

[Intel-gfx] [PATCH v5 10/16] swiotlb: Move alloc_size to find_slots

2021-04-22 Thread Claire Chang
Move the maintenance of alloc_size to find_slots for better code reusability later. Signed-off-by: Claire Chang --- kernel/dma/swiotlb.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c index 96ff36d8ec53..b7d634d7a7eb 100

[Intel-gfx] [PATCH v5 09/16] swiotlb: Bounce data from/to restricted DMA pool if available

2021-04-22 Thread Claire Chang
Regardless of swiotlb setting, the restricted DMA pool is preferred if available. The restricted DMA pools provide a basic level of protection against the DMA overwriting buffer contents at unexpected times. However, to protect against general data leakage and system memory corruption, the system

[Intel-gfx] [PATCH v5 08/16] swiotlb: Update is_swiotlb_active to add a struct device argument

2021-04-22 Thread Claire Chang
Update is_swiotlb_active to add a struct device argument. This will be useful later to allow for restricted DMA pool. Signed-off-by: Claire Chang --- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.c| 2 +- drivers/pci/xen-pcifront.c

[Intel-gfx] [PATCH v5 07/16] swiotlb: Update is_swiotlb_buffer to add a struct device argument

2021-04-22 Thread Claire Chang
Update is_swiotlb_buffer to add a struct device argument. This will be useful later to allow for restricted DMA pool. Signed-off-by: Claire Chang --- drivers/iommu/dma-iommu.c | 12 ++-- drivers/xen/swiotlb-xen.c | 2 +- include/linux/swiotlb.h | 6 +++--- kernel/dma/direct.c |

[Intel-gfx] [PATCH v5 06/16] swiotlb: Add a new get_io_tlb_mem getter

2021-04-22 Thread Claire Chang
Add a new getter, get_io_tlb_mem, to help select the io_tlb_mem struct. The restricted DMA pool is preferred if available. Signed-off-by: Claire Chang --- include/linux/swiotlb.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h in

[Intel-gfx] [PATCH v5 05/16] swiotlb: Add restricted DMA pool initialization

2021-04-22 Thread Claire Chang
Add the initialization function to create restricted DMA pools from matching reserved-memory nodes. Signed-off-by: Claire Chang --- include/linux/device.h | 4 +++ include/linux/swiotlb.h | 3 +- kernel/dma/swiotlb.c| 80 + 3 files changed, 86 inser

[Intel-gfx] [PATCH v5 04/16] swiotlb: Add DMA_RESTRICTED_POOL

2021-04-22 Thread Claire Chang
Add a new kconfig symbol, DMA_RESTRICTED_POOL, for restricted DMA pool. Signed-off-by: Claire Chang --- kernel/dma/Kconfig | 14 ++ 1 file changed, 14 insertions(+) diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 77b405508743..3e961dc39634 100644 --- a/kernel/dma/Kconfig

[Intel-gfx] [PATCH v5 03/16] swiotlb: Refactor swiotlb_create_debugfs

2021-04-22 Thread Claire Chang
Split the debugfs creation to make the code reusable for supporting different bounce buffer pools, e.g. restricted DMA pool. Signed-off-by: Claire Chang --- kernel/dma/swiotlb.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/kernel/dma/swiotlb.c b/kernel/

[Intel-gfx] [PATCH v5 01/16] swiotlb: Fix the type of index

2021-04-22 Thread Claire Chang
Fix the type of index from unsigned int to int since find_slots() might return -1. Fixes: 0774983bc923 ("swiotlb: refactor swiotlb_tbl_map_single") Signed-off-by: Claire Chang --- kernel/dma/swiotlb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/dma/swiotlb.c b/ke

[Intel-gfx] [PATCH v5 02/16] swiotlb: Refactor swiotlb init functions

2021-04-22 Thread Claire Chang
Add a new function, swiotlb_init_io_tlb_mem, for the io_tlb_mem struct initialization to make the code reusable. Note that we now also call set_memory_decrypted in swiotlb_init_with_tbl. Signed-off-by: Claire Chang --- kernel/dma/swiotlb.c | 51 ++-- 1 fi

[Intel-gfx] [PATCH v5 00/16] Restricted DMA

2021-04-22 Thread Claire Chang
This series implements mitigations for lack of DMA access control on systems without an IOMMU, which could result in the DMA accessing the system memory at unexpected times and/or unexpected addresses, possibly leading to data leakage or corruption. For example, we plan to use the PCI-e bus for Wi