> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, March 11, 2021 2:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Souza, Jose ; Roper, Matthew D
> ; Srivatsa, Anusha
> ; Taylor, Clinton A
> ; Heikkila, Juha-pekka pekka.heikk...@intel.com>; Taylor, Clinton A
> Subject:
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits
> for blocks & lines
>
> ADL-P further extends the bits in PLANE_WM
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support
>
> From: Clinton Taylor
>
> Add ADP-P PCH device ID and assign as ADL
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
>
> From: Clinton Taylor
>
> Add 12 known PCI device IDs
>
> Bspec
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth
> increases when VT-d is active
>
> If VT-d is active, the memory band
> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> ; De Marchi, Lucas
>
> Subject: [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
>
> XE_LPD has new AU
On Thu, 11 Mar 2021 14:36:31 -0800, Matt Roper wrote:
>
> From: Umesh Nerlige Ramappa
>
> Enable relevant OA formats for ADL_P.
Reviewed-by: Ashutosh Dixit
> Cc: Ashutosh Dixit
> Signed-off-by: Umesh Nerlige Ramappa
> Signed-off-by: Clinton Taylor
> Signed-off-by: Matt Roper
> ---
> driver
On Fri, Mar 12, 2021 at 12:42:27PM -0800, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Matt
> > Roper
> > Sent: Thursday, March 11, 2021 2:36 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_G
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to
> DISPLAY_VER() as appropriate in intel_pm.c
>
> Although most of the co
On Thu, Mar 11, 2021 at 02:35:42PM -0800, Matt Roper wrote:
> GLK has always been a bit of a special case since it reports INTEL_GEN()
> as 9, but has version 10 display IP. Now we can properly represent the
> display version as 10 and simplify the display generation tests
> throughout the display
== Series Details ==
Series: Default request/fence expiry + watchdog
URL : https://patchwork.freedesktop.org/series/87930/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9854_full -> Patchwork_19789_full
Summary
---
*
On Thu, Mar 11, 2021 at 10:26:12AM -0800, Swathi Dhanavanthri wrote:
> This is a permanent workaround for TGL,RKL,DG1 and ADLS.
>
> Signed-off-by: Swathi Dhanavanthri
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +
> drivers/gpu/drm/i915/i915_reg.h |
On Fri, Mar 12, 2021 at 12:19:42AM +0200, Imre Deak wrote:
> On Thu, Mar 11, 2021 at 09:45:14PM +0200, Ville Syrjälä wrote:
> > On Thu, Mar 11, 2021 at 12:17:31AM +0200, Imre Deak wrote:
> > > Save some place in the GTT VMAs by using a u16 instead of unsigned int
> > > to store the view dimensions.
On Thu, Mar 11, 2021 at 12:17:35AM +0200, Imre Deak wrote:
> Add selftests to test the POT stride padding functionality added in the
> previous patch.
>
> Signed-off-by: Imre Deak
Looks sensible.
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/selftests/i915_vma.c | 93 ++
On Thu, Mar 11, 2021 at 12:17:34AM +0200, Imre Deak wrote:
> An upcoming platform has a restriction that the FB stride must be
> power-of-two aligned. To support framebuffer layouts that are not in
> this layout add a logic that pads the tile rows to the POT aligned size.
>
> The HW won't read the
On Thu, Mar 11, 2021 at 12:17:33AM +0200, Imre Deak wrote:
> An upcoming patch adds a new dst_stride field to the
> intel_remapped_plane_info struct, so for clarity rename the current
> stride field to src_stride.
>
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm
On Thu, Mar 11, 2021 at 02:35:37PM -0800, Matt Roper wrote:
> ILK is the only platform that we consider "gen5" and SNB is the only
> platform we consider "gen6." Add an IS_SANDYBRIDGE() macro and then
> replace numeric platform tests for these two generations with direct
> platform tests with the
== Series Details ==
Series: Default request/fence expiry + watchdog
URL : https://patchwork.freedesktop.org/series/87930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9854 -> Patchwork_19789
Summary
---
**SUCCESS**
== Series Details ==
Series: Default request/fence expiry + watchdog
URL : https://patchwork.freedesktop.org/series/87930/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
865f5ed6eec8 drm/i915: Individual request cancellation
-:256: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"
== Series Details ==
Series: drm/i915/display/psr: Add sink not reliable check to intel_psr_work()
URL : https://patchwork.freedesktop.org/series/87924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9853_full -> Patchwork_19788_full
From: Tvrtko Ursulin
Module parameter is added (request_timeout_ms) to allow configuring the
default request/fence expiry.
Default value is inherited from CONFIG_DRM_I915_REQUEST_TIMEOUT.
Signed-off-by: Tvrtko Ursulin
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8
From: Tvrtko Ursulin
Idea here is to make the watchdog mechanism more useful than for just
default request/fence expiry.
To this effect a new context param I915_CONTEXT_PARAM_WATCHDOG is added
where the value fields allows passing in a timeout in micro-seconds.
This allows userspace to set a li
From: Tvrtko Ursulin
A new Kconfig option CONFIG_DRM_I915_REQUEST_TIMEOUT is added, defaulting
to 10s, and this timeout is applied to _all_ contexts using the previously
added watchdog facility.
Result of this is that any user submission will simply fail after this
time, either causing a reset (
From: Tvrtko Ursulin
Prepares the plumbing for setting request/fence expiration time. All code
is put in place but is never activeted due yet missing ability to actually
configure the timer.
Outline of the basic operation:
A timer is started when request is ready for execution. If the request
c
From: Tvrtko Ursulin
Disallow sentinel requests follow previous sentinels to make request
cancellation work better when faced with a chain of requests which have
all been marked as in error.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
1 file c
From: Chris Wilson
Currently, we cancel outstanding requests within a context when the
context is closed. We may also want to cancel individual requests using
the same graceful preemption mechanism.
v2 (Tvrtko):
* Cancel waiters carefully considering no timeline lock and RCU.
* Fixed selftests
From: Tvrtko Ursulin
"Watchdog" aka "restoring hangcheck" aka default request/fence expiry - first
post of a somewhat controversial feature so may be somewhat rough in commit
messages, commentary and implementation. So only RFC for now.
I parenthesise the "watchdog" becuase in classical sense wa
On 12/03/2021 14:52, Jason Ekstrand wrote:
On Fri, Mar 12, 2021 at 6:17 AM Matthew Auld
wrote:
On Fri, 12 Mar 2021 at 11:47, Tvrtko Ursulin
wrote:
On 12/03/2021 10:56, Matthew Auld wrote:
On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
wrote:
On 11/03/2021 18:17, Jason Ekstrand wrote:
On Fri, Mar 12, 2021 at 6:17 AM Matthew Auld
wrote:
>
> On Fri, 12 Mar 2021 at 11:47, Tvrtko Ursulin
> wrote:
> >
> >
> > On 12/03/2021 10:56, Matthew Auld wrote:
> > > On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
> > > wrote:
> > >>
> > >>
> > >> On 11/03/2021 18:17, Jason Ekstrand wrote:
> > >
== Series Details ==
Series: drm/i915/display/psr: Add sink not reliable check to intel_psr_work()
URL : https://patchwork.freedesktop.org/series/87924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9853 -> Patchwork_19788
== Series Details ==
Series: drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake (rev2)
URL : https://patchwork.freedesktop.org/series/82581/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9853_full -> Patchwork_19787_full
==
On Thu, Mar 11, 2021 at 12:57:25PM -0600, Jason Ekstrand wrote:
> On Thu, Mar 11, 2021 at 12:20 PM Zbigniew Kempczyński
> wrote:
> >
> > On Thu, Mar 11, 2021 at 11:18:11AM -0600, Jason Ekstrand wrote:
> > > On Thu, Mar 11, 2021 at 10:51 AM Zbigniew Kempczyński
> > > wrote:
> > > >
> > > > On Thu,
On Thu, Mar 11, 2021 at 10:31:33PM -0600, Jason Ekstrand wrote:
>
> On March 11, 2021 20:26:06 "Dixit, Ashutosh" wrote:
>
> > On Wed, 10 Mar 2021 13:00:49 -0800, Jason Ekstrand wrote:
> > >
> > > libdrm has supported the newer execbuffer2 ioctl and using it by default
> > > when it exists since
On Fri, 2021-03-12 at 15:34 +0200, Gwan-gyeong Mun wrote:
> If the sink state is not reliable, it does not need to wait for
> PSR "IDLE state" for re-enabling PSR. And it should not try to re-enable
> PSR.
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 3 ++
If the sink state is not reliable, it does not need to wait for
PSR "IDLE state" for re-enabling PSR. And it should not try to re-enable
PSR.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/di
== Series Details ==
Series: drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake (rev2)
URL : https://patchwork.freedesktop.org/series/82581/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9853 -> Patchwork_19787
== Series Details ==
Series: drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake (rev2)
URL : https://patchwork.freedesktop.org/series/82581/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac84453e233c drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake
On Fri, Mar 05, 2021 at 05:36:10PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename a bunch of the skl+ watermark struct members to
> have sensible names. Avoids me having to think what
> plane_res_b/etc. means.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-b
On Fri, Mar 05, 2021 at 05:36:09PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make the code more typo proof by extracting small helpers that
> do the "do we have enough DDB for the WM level?" checks in
> a consistent manner.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
On Fri, 12 Mar 2021 at 11:47, Tvrtko Ursulin
wrote:
>
>
> On 12/03/2021 10:56, Matthew Auld wrote:
> > On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> On 11/03/2021 18:17, Jason Ekstrand wrote:
> >>> The Vulkan driver in Mesa for Intel hardware never uses relocations if
> >
On Fri, Mar 05, 2021 at 05:36:08PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's make all the "do we have enough DDB for this WM level?"
> checks use min_ddb_alloc. To achieve that we need to populate
> this for the transition watermarks as well.
>
> Cc: Stanislav Lisovskiy
> Sign
On Fri, Mar 05, 2021 at 05:36:07PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For non-transition watermarks we are supposed to check min_ddb_alloc
> rather than plane_res_b when determining if we have enough DDB space
> for it. A bit too much copy pasta made me check the wrong thing.
>
On Thu, Mar 11, 2021 at 05:28:43PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 11, 2021 at 04:36:05PM +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Mar 05, 2021 at 05:36:06PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Say we have two planes enabled with watermarks configured
As per b.spec 49274, the IO buffer Wake lines and Fast Wake lines can be
calculated based on the following formula.
IO buffer wake lines = ROUNDUP(PSR2 IO wake time / total line time in
microseconds)
Fast wake lines = ROUNDUP(PSR2 aux transaction time / total line time in
microseconds)
For bo
On 12/03/2021 11:33, Maarten Lankhorst wrote:
Op 2021-03-12 om 11:56 schreef Matthew Auld:
On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
wrote:
On 11/03/2021 18:17, Jason Ekstrand wrote:
The Vulkan driver in Mesa for Intel hardware never uses relocations if
it's running on a version of i915
On 12/03/2021 10:56, Matthew Auld wrote:
On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
wrote:
On 11/03/2021 18:17, Jason Ekstrand wrote:
The Vulkan driver in Mesa for Intel hardware never uses relocations if
it's running on a version of i915 that supports at least softpin which
all versions
Op 2021-03-12 om 04:28 schreef Dixit, Ashutosh:
> On Thu, 11 Mar 2021 12:20:17 -0800, Jason Ekstrand wrote:
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c
>> b/drivers/gpu/drm/i915/i915_gem.c
>> index b2e3b5cfccb4a..78ad5a9dd4784 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gp
Op 2021-03-12 om 11:56 schreef Matthew Auld:
> On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
> wrote:
>>
>> On 11/03/2021 18:17, Jason Ekstrand wrote:
>>> The Vulkan driver in Mesa for Intel hardware never uses relocations if
>>> it's running on a version of i915 that supports at least softpin whic
On Fri, 12 Mar 2021 at 09:50, Tvrtko Ursulin
wrote:
>
>
> On 11/03/2021 18:17, Jason Ekstrand wrote:
> > The Vulkan driver in Mesa for Intel hardware never uses relocations if
> > it's running on a version of i915 that supports at least softpin which
> > all versions of i915 supporting Gen12 do.
On 2/20/2021 4:03 PM, Ville Syrjala wrote:
From: Ville Syrjälä
On HSW/BDW with VT-d active the first tile row scanned out
after the first async flip of the frame often ends up corrupted.
Whether the corruption happens or not depends on the scanline
on which the async flip happens, but the beha
On 11/03/2021 18:17, Jason Ekstrand wrote:
The Vulkan driver in Mesa for Intel hardware never uses relocations if
it's running on a version of i915 that supports at least softpin which
all versions of i915 supporting Gen12 do. On the OpenGL side, Gen12+ is
only supported by iris which never us
On Thu, Mar 11, 2021 at 12:17:33PM -0600, Jason Ekstrand wrote:
> The Vulkan driver in Mesa for Intel hardware never uses relocations if
> it's running on a version of i915 that supports at least softpin which
> all versions of i915 supporting Gen12 do. On the OpenGL side, Gen12+ is
> only support
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