Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

Dear Matt, Yes, it needs the WA in TGL. Not sure the ADL-S and RKL. The issue is different from 1808121037. Previously, it was not found which exact usage condition needs to disable RHWO in studying the Alibaba issue in SG1, so make this change in kernel. Should we move the " disable RHWO " to

Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

On Tue, Mar 02, 2021 at 05:07:28PM -0800, Lucas De Marchi wrote: > From: Zhen Han > > GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang > due to RHWO, but that is what we are observing, even without media > compressible render target. Feedback from HW engineers is to leave RH

Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

Yes, that's the case. It has RCC related silicon issues in gen12-lp. Followings are two consecutive GPU hangs we found in SG1 and DG1 linux which have no media compressible render target. 1. HSD-1508524297 [SG1][DG1] GPU hang in PIPECONTROL in running 1

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Wa_14010826681 does the same as Wa_22010271021

On Tue, Mar 02, 2021 at 05:07:27PM -0800, Lucas De Marchi wrote: > From: Caz Yokoyama > > Add a comment marking Wa_14010826681 as the same as Wa_22010271021 > for easy verification. > > Bspec: 54508, 52890 > > Cc: Clinton Taylor > Cc: Matt Roper > Signed-off-by: Caz Yokoyama > Signed-off-by:

Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: add Wa_22010271021 for all gen11

On Tue, Mar 02, 2021 at 05:07:26PM -0800, Lucas De Marchi wrote: > From: Caz Yokoyama > > Wa_22010271021 does not apply only to EHL, but to all gen11 platforms. It also applies to a bunch of gen12 platforms; we already apply the same workaround in an earlier block of the same function too to han

Re: [Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

On Tue, Mar 02, 2021 at 05:07:25PM -0800, Lucas De Marchi wrote: > From: Caz Yokoyama > > Follow Bspec 31870 to set recommended tuning values for certain GT > register. These values aren't workarounds per-se, but it's best to > handle them in the same general area of the driver, especially since

Re: [Intel-gfx] Public i915 CI shardruns are disabled

Ok, slightly delayed by dinner, but commit caf6912f3f4a ("swap: fix swapfile read/write offset") is out in my tree now. Dave - can you check that the current -git works for your CI people? Thanks, Linus On Tue, Mar 2, 2021 at 5:18 PM Jens Axboe wrote: > > On 3/2/21 6:01 PM, Linus

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On 3/2/21 6:01 PM, Linus Torvalds wrote: > On Tue, Mar 2, 2021 at 4:36 PM Jens Axboe wrote: >> >> Or if you want a pull, just let me know. Have another misc patch to >> flush out anyway that doesn't belong in any of my usual branches. > > Ok, if you have something else pending anyway, let's do th

[Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

From: Zhen Han GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang due to RHWO, but that is what we are observing, even without media compressible render target. Feedback from HW engineers is to leave RHWO disabled. Cc: Jianjun Liu Cc: Chuansheng Liu Cc: Radhakrishna Sripada

[Intel-gfx] [PATCH 2/4] drm/i915/icl: add Wa_22010271021 for all gen11

From: Caz Yokoyama Wa_22010271021 does not apply only to EHL, but to all gen11 platforms. Bspec: 33450, 52887 Cc: Clinton Taylor Cc: Matt Roper Signed-off-by: Caz Yokoyama Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 - 1 file changed, 4 insert

[Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value

From: Caz Yokoyama Follow Bspec 31870 to set recommended tuning values for certain GT register. These values aren't workarounds per-se, but it's best to handle them in the same general area of the driver, especially since there may be real workarounds that update other bits of the same registers

[Intel-gfx] [PATCH 3/4] drm/i915: Wa_14010826681 does the same as Wa_22010271021

From: Caz Yokoyama Add a comment marking Wa_14010826681 as the same as Wa_22010271021 for easy verification. Bspec: 54508, 52890 Cc: Clinton Taylor Cc: Matt Roper Signed-off-by: Caz Yokoyama Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++- 1 file chan

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On Tue, Mar 2, 2021 at 4:36 PM Jens Axboe wrote: > > Or if you want a pull, just let me know. Have another misc patch to > flush out anyway that doesn't belong in any of my usual branches. Ok, if you have something else pending anyway, let's do that. Send me the pull request, and I'll take it asa

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On 3/2/21 5:15 PM, Jens Axboe wrote: > On 3/2/21 4:56 PM, Linus Torvalds wrote: >> On Tue, Mar 2, 2021 at 3:38 PM Dave Airlie wrote: >>> >>> Looks like Jens saw it at least, he posted this on twitter a few mins >>> ago so I assume it'll be incoming soon. >>> >>> https://git.kernel.dk/cgit/linux-bl

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On 3/2/21 4:56 PM, Linus Torvalds wrote: > On Tue, Mar 2, 2021 at 3:38 PM Dave Airlie wrote: >> >> Looks like Jens saw it at least, he posted this on twitter a few mins >> ago so I assume it'll be incoming soon. >> >> https://git.kernel.dk/cgit/linux-block/commit/?h=swap-fix > > Ahh. You use a sw

Re: [Intel-gfx] [PATCH] i915/query: Correlate engine and cpu timestamps with better accuracy

On Tue, Mar 02, 2021 at 10:35:19PM +0200, Lionel Landwerlin wrote: Thanks a bunch for sharing this! On 02/03/2021 20:29, Umesh Nerlige Ramappa wrote: Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these times

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On Tue, Mar 2, 2021 at 3:38 PM Dave Airlie wrote: > > Looks like Jens saw it at least, he posted this on twitter a few mins > ago so I assume it'll be incoming soon. > > https://git.kernel.dk/cgit/linux-block/commit/?h=swap-fix Ahh. You use a swap file. This might be the same thing that I think t

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On Wed, 3 Mar 2021 at 09:28, Linus Torvalds wrote: > > Adding the right people. > > It seems that the three commits that needed reverting are > > f885056a48cc ("mm: simplify swapdev_block") > 3e3126cf2a6d ("mm: only make map_swap_entry available for > CONFIG_HIBERNATION") > 48d15436fde6 ("m

Re: [Intel-gfx] Public i915 CI shardruns are disabled

Adding the right people. It seems that the three commits that needed reverting are f885056a48cc ("mm: simplify swapdev_block") 3e3126cf2a6d ("mm: only make map_swap_entry available for CONFIG_HIBERNATION") 48d15436fde6 ("mm: remove get_swap_bio") and while they look very harmless to me, le

[Intel-gfx] [PATCH] drm/atomic: Add the crtc to affected crtc only if uapi.enable = true

In case of a modeset where a mode gets split across mutiple CRTCs in the driver specific implementation (bigjoiner in i915) we wrongly count the affected CRTCs based on the drm_crtc_mask and indicate the stolen CRTC as an affected CRTC in atomic_check_only(). This triggers a warning since affected

Re: [Intel-gfx] [PATCH] i915/query: Correlate engine and cpu timestamps with better accuracy

Thanks a bunch for sharing this! On 02/03/2021 20:29, Umesh Nerlige Ramappa wrote: Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these timestamps separately and the calculated delta between these timestamps l

Re: [Intel-gfx] Public i915 CI shardruns are disabled

On Wed, 3 Mar 2021 at 03:27, Sarvela, Tomi P wrote: > > The regression has been identified; Chris Wilson found commits touching > > swapfile.c, and reverting them the issue couldn’t be reproduced any more. > > > > https://patchwork.freedesktop.org/series/87549/ > > > > This revert will be applied

Re: [Intel-gfx] [PATCH] drm/i915: Readout conn_state->max_bpc

On Tue, 2021-02-16 at 18:00 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Populate conn_state->max_bpc with something sensible from the start. > Otherwise it's possible that we get to compute_sink_pipe_bpp() with > max_bpc==0. > > The specific scenario goes as follows: > 1. Initial conne

[Intel-gfx] [PATCH] i915/query: Correlate engine and cpu timestamps with better accuracy

Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these timestamps separately and the calculated delta between these timestamps lack enough accuracy. To improve the accuracy of these time measurements to within a f

Re: [Intel-gfx] Public i915 CI shardruns are disabled

The regression has been identified; Chris Wilson found commits touching swapfile.c, and reverting them the issue couldn't be reproduced any more. https://patchwork.freedesktop.org/series/87549/ This revert will be applied to core-for-CI branch. When new CI_DRM has been built, shard-testing will b

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

On Tue, 02 Mar 2021, Ville Syrjälä wrote: > On Tue, Mar 02, 2021 at 12:25:00PM +0200, Jani Nikula wrote: >> On Mon, 22 Feb 2021, Jani Nikula wrote: >> > On Mon, 22 Feb 2021, "Shankar, Uma" wrote: >> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h >> >>> b/drivers/gpu/drm/i915

[Intel-gfx] ✓ Fi.CI.BAT: success for vfio/pci: Add support for opregion v2.0+ (rev4)

== Series Details == Series: vfio/pci: Add support for opregion v2.0+ (rev4) URL : https://patchwork.freedesktop.org/series/84494/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19740 Summary --- **S

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wedge the GPU if command parser setup fails (rev3)

== Series Details == Series: drm/i915: Wedge the GPU if command parser setup fails (rev3) URL : https://patchwork.freedesktop.org/series/87422/ State : success == Summary == CI Bug Log - changes from CI_DRM_9821 -> Patchwork_19745 Summary -

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

On Tue, Mar 02, 2021 at 12:25:00PM +0200, Jani Nikula wrote: > On Mon, 22 Feb 2021, Jani Nikula wrote: > > On Mon, 22 Feb 2021, "Shankar, Uma" wrote: > >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > >>> b/drivers/gpu/drm/i915/display/intel_display_types.h > >>> index 71611b

Re: [Intel-gfx] [PATCH resend 2/2] drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

On Tue, Mar 02, 2021 at 01:00:40PM +0100, Hans de Goede wrote: > As explained by a long comment block, on VLV intel_setup_outputs() > sometimes thinks there might be an eDP panel connected while there is none. > In this case intel_setup_outputs() will call intel_dp_init() to check. > > In this sce

Re: [Intel-gfx] Public i915 CI shardruns are disabled

More information (excuse my top-posting): - Issue happens in igt@gem_tiled_swapping@non-threaded Mlocking phase, before "starting subtest" appears. - Filesystem trashed is the one containing swapfile - If swap is partition, it seems that the swap signature is correct even after running the test,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

== Series Details == Series: drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes URL : https://patchwork.freedesktop.org/series/87542/ State : success == Summary == CI Bug Log - changes from CI_DRM_9820 -> Patchwork_19744

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

== Series Details == Series: drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes URL : https://patchwork.freedesktop.org/series/87542/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won

Re: [Intel-gfx] [PATCH resend 2/2] drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

On Tue, 02 Mar 2021, Hans de Goede wrote: > As explained by a long comment block, on VLV intel_setup_outputs() > sometimes thinks there might be an eDP panel connected while there is none. > In this case intel_setup_outputs() will call intel_dp_init() to check. > > In this scenario vlv_find_free_p

[Intel-gfx] [bug report] drm/i915: buddy allocator

[ Sorry, I don't know why Smatch is complaining about two year old code. The warning is valid enough, though. - dan ] Hello Matthew Auld, The patch 14d1b9a6247c: "drm/i915: buddy allocator" from Aug 9, 2019, leads to the following static checker warning: drivers/gpu/drm/i915/selftests

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for vfio/pci: Add support for opregion v2.0+ (rev4)

Hi, Lakshmi: 1. The test failed on version 4 while passed on version 3. The only difference between v3/v4 lies in the format indent issue :“Alignment should match open parenthesis ” 2. My patch only works in VFIO during a guest virtual machine is launched on VT-d gpu passthru. i,e

Re: [Intel-gfx] [PATCH resend 1/2] drm/i915/display: Add a intel_pipe_is_enabled() helper

On Tue, 02 Mar 2021, Hans de Goede wrote: > Factor the code to check if a pipe is currently enabled out of > assert_pipe() and put it in a new intel_pipe_is_enabled() helper, > so that it can be re-used without copy-pasting it. > > Signed-off-by: Hans de Goede Does what it says on the box. Revi

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Wedge the GPU if command parser setup fails (rev2)

== Series Details == Series: drm/i915: Wedge the GPU if command parser setup fails (rev2) URL : https://patchwork.freedesktop.org/series/87422/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9820 -> Patchwork_19743 Summary -

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: complete eDP MSO support

== Series Details == Series: drm/i915: complete eDP MSO support URL : https://patchwork.freedesktop.org/series/87536/ State : success == Summary == CI Bug Log - changes from CI_DRM_9820 -> Patchwork_19742 Summary --- **SUCCESS** N

[Intel-gfx] [PATCH resend 2/2] drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

As explained by a long comment block, on VLV intel_setup_outputs() sometimes thinks there might be an eDP panel connected while there is none. In this case intel_setup_outputs() will call intel_dp_init() to check. In this scenario vlv_find_free_pps() ends up selecting pipe A for the pps, even thou

[Intel-gfx] [PATCH resend 1/2] drm/i915/display: Add a intel_pipe_is_enabled() helper

Factor the code to check if a pipe is currently enabled out of assert_pipe() and put it in a new intel_pipe_is_enabled() helper, so that it can be re-used without copy-pasting it. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/display/intel_display.c | 20 ++-- drivers/gpu

[Intel-gfx] [PATCH resend 0/2] drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

Hi All, Here is a resend of my patch-set to deal with an "transcoder A assertion failure (expected off, current on)" error + WARN (and backtrace) seen on some Bay Trail devices with a DSI panel. I've rebased it on the latest drm-intel-next, so this time around the CI should be able to actually ap

Re: [Intel-gfx] [PATCH] drm/i915: Verify dma_addr in gen8_ggtt_pte_encode

Quoting Piorkowski, Piotr (2021-02-24 15:29:25) > From: Piotr Piórkowski > > Until now, the gen8_ggtt_pte_encode function, responsible for the preparation > of GGTT PTE, has not verified in any way whether the address given as the > parameter is correct. > By adding a GGTT address mask, we can ea

[Intel-gfx] [CI] drm/i915: Wedge the GPU if command parser setup fails

From: Tvrtko Ursulin Commit 311a50e76a33 ("drm/i915: Add support for mandatory cmdparsing") introduced mandatory command parsing but setup failures were not translated into wedging the GPU which was probably the intent. Possible errors come in two categories. Either the sanity check on internal

[Intel-gfx] Public i915 CI shardruns are disabled

Hello, The linux i915 CI shardruns have been disabled. This is due to the unfortunate filesystem-corrupting bug first seen in linux-next 20210215, which now has been merged to linus 5.12-rc1 and further on to DRM-Tip, first instance seen in CI_DRM_9818. Last changes coming in were: fb3b93df7979 d

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: complete eDP MSO support

== Series Details == Series: drm/i915: complete eDP MSO support URL : https://patchwork.freedesktop.org/series/87536/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/inte

Re: [Intel-gfx] [PATCH] drm/i915: Wedge the GPU if command parser setup fails

Quoting Tvrtko Ursulin (2021-02-26 09:51:54) > From: Tvrtko Ursulin > > Commit 311a50e76a33 ("drm/i915: Add support for mandatory cmdparsing") > introduced mandatory command parsing but setup failures were not > translated into wedging the GPU which was probably the intent. > > Possible errors c

[Intel-gfx] [PATCH v4 4/4] drm/i915/edp: enable eDP MSO during link training

If the source and sink support MSO, enable it during link training. v4: Divide DRRS pixel clock by link count before M/N calculation v3: Adjust timings, refer to splitter v2: Limit MSO to pipe A using ->pipe_mask Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2711 Cc: Nischal Varide

[Intel-gfx] [PATCH v4 3/4] drm/i915/edp: modify fixed and downclock modes for MSO

In the case of MSO (Multi-SST Operation), the EDID contains the timings for a single panel segment. We'll want to hide the fact from userspace, and expose modes that span the entire display. Don't modify the EDID, as the userspace should not use that for modesetting, only modify the actual modes.

[Intel-gfx] [PATCH v4 2/4] drm/i915/mso: add splitter state check

For starters, we expect the state to be zero, as we don't enable MSO anywhere. v2: Refer to splitter. Cc: Nischal Varide Reviewed-by: Uma Shankar Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v4 0/4] drm/i915: complete eDP MSO support

The remaining and updated patches from [1]. Address some review comments from Uma, and fix MSO for downclocked modes. BR, Jani. [1] https://patchwork.freedesktop.org/series/86992/ Jani Nikula (4): drm/i915/mso: add splitter state readout for platforms that support it drm/i915/mso: add spli

[Intel-gfx] [PATCH v4 1/4] drm/i915/mso: add splitter state readout for platforms that support it

Add splitter configuration to crtc state, and read it where supported. Also add splitter state dumping. The stream splitter will be required for eDP MSO. v4: - Catch invalid splitter configuration (Uma) v3: - Convert segment timings to full panel timings. - Refer to splitter instead of mso in crt

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

> -Original Message- > From: Nikula, Jani > Sent: Tuesday, March 2, 2021 3:55 PM > To: Shankar, Uma ; intel-gfx@lists.freedesktop.org > Cc: Varide, Nischal ; Ville Syrjälä > > Subject: RE: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state > readout for > platforms that suppo

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it

On Mon, 22 Feb 2021, Jani Nikula wrote: > On Mon, 22 Feb 2021, "Shankar, Uma" wrote: >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h >>> b/drivers/gpu/drm/i915/display/intel_display_types.h >>> index 71611b596c88..5564db512d22 100644 >>> --- a/drivers/gpu/drm/i915/display/inte

Re: [Intel-gfx] [CI 04/15] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave

On Tue, 17 Nov 2020, Manasi Navare wrote: > Make vdsc work when no output is enabled. The big joiner needs VDSC > on the slave, so enable it and set the appropriate bits. > So remove encoder usage from dsc functions. Hi Manasi - I'm reading intel_vdsc.c code for something else, and stumbled upon