On Tue, Nov 17, 2020 at 10:14:00AM -0800, Umesh Nerlige Ramappa wrote:
This is quite different and much cleane from my original patch :), so
you should be the author. With that, this is
Reviewed-by: Umesh Nerlige Ramappa
any chance to get at least patches 1 and 2 applied?
Lucas De Marchi
== Series Details ==
Series: drm/i915: Fix up TGL+ SAGV watermarks
URL : https://patchwork.freedesktop.org/series/87433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9814 -> Patchwork_19733
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Fix up TGL+ SAGV watermarks
URL : https://patchwork.freedesktop.org/series/87433/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ccc6bba5464d drm/i915: Fix TGL+ plane SAGV watermark programming
f0b33a40d933 drm/i915: Zero out SAGV wm when w
From: Ville Syrjälä
Get rid of the nonsense cursor special case in verify_wm_state()
by just iterating through all the planes. And let's use the
canonical [PLANE:..] style in the debug prints while at it.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/in
From: Ville Syrjälä
We know which WM0 (normal vs. SAGV) we supposedly programmed
into the hardware, so just check against that instead of accepting
either watermark as valid.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 88 +--
From: Ville Syrjälä
Seems to me that if we calculate WM0 using the bumped up SAGV latency
we need to calculate the transition watermark accordingly. Track it
alongside the other watermarks.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
We'll want a SAGV transition watermark as well. Prepare
for that by collecting SAGV wm0 into a sub-strcture.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +--
.../drm/i915/display/intel_display_types.h| 4
From: Ville Syrjälä
Let's consider sagv_wm0 as well when deciding whether to dump
out the watermark changes.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/inte
From: Ville Syrjälä
Let's handle the SAGV WM0 more like the other wm levels and just
totally zero it out when we don't have the DDB space to back it
up.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 11 ++-
1 file changed, 6 insertions(+),
From: Ville Syrjälä
When we switch between SAGV on vs. off we need to reprogram all
plane wateramrks accordingly. Currently skl_wm_add_affected_planes()
totally ignores the SAGV watermark and just assumes we will use
the normal WM0.
Fix this by utilizing skl_plane_wm_level() which picks the
corr
From: Ville Syrjälä
Had a quick glance as the TGL+ watermark code and noticed a
bunch of fail with the SAGV wm handling. Here's an attempt
at fixing it.
Git branch here:
git://github.com/vsyrjala/linux.git tgl_sagv_wm_fixes
Cc: Stanislav Lisovskiy
Ville Syrjälä (7):
drm/i915: Fix TGL+ plane
On Fri, Feb 26, 2021 at 02:51:58PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 26.02.21 um 14:30 schrieb Daniel Vetter:
> > On Fri, Feb 26, 2021 at 10:19 AM Thomas Zimmermann
> > wrote:
> > >
> > > Hi
> > >
> > > Am 25.02.21 um 11:23 schrieb Daniel Vetter:
> > > > Aside from deleting lots of c
Hi
Am 26.02.21 um 14:30 schrieb Daniel Vetter:
On Fri, Feb 26, 2021 at 10:19 AM Thomas Zimmermann wrote:
Hi
Am 25.02.21 um 11:23 schrieb Daniel Vetter:
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
On Thu, Feb 25, 2021 at 05:49:11PM +0100, Maxime Ripard wrote:
> On Mon, Feb 22, 2021 at 11:06:43AM +0100, Daniel Vetter wrote:
> > Some of them have gaps, or fields we don't clear. Native ioctl code
> > does full copies plus zero-extends on size mismatch, so nothing can
> > leak. But compat is mor
On Fri, Feb 26, 2021 at 10:19 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 25.02.21 um 11:23 schrieb Daniel Vetter:
> > Aside from deleting lots of code the real motivation here is to switch
> > the mmap over to VM_PFNMAP, to be more consistent with what real gpu
> > drivers do. They're all VM_PFNMP,
On Fri, Feb 26, 2021 at 10:41 AM Thomas Hellström (Intel)
wrote:
>
>
> On 2/25/21 4:49 PM, Daniel Vetter wrote:
> > On Thu, Feb 25, 2021 at 11:44 AM Daniel Vetter wrote:
> >> On Thu, Feb 25, 2021 at 11:28:31AM +0100, Christian König wrote:
> >>> Am 24.02.21 um 10:31 schrieb Daniel Vetter:
>
== Series Details ==
Series: drm/i915: Wedge the GPU if command parser setup fails
URL : https://patchwork.freedesktop.org/series/87422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9810_full -> Patchwork_19732_full
Summar
== Series Details ==
Series: drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested
during PHY Layer testing. (rev2)
URL : https://patchwork.freedesktop.org/series/80911/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9810_full -> Patchwork_19731_full
===
== Series Details ==
Series: drm/i915: Wedge the GPU if command parser setup fails
URL : https://patchwork.freedesktop.org/series/87422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9810 -> Patchwork_19732
Summary
---
From: Tvrtko Ursulin
Commit 311a50e76a33 ("drm/i915: Add support for mandatory cmdparsing")
introduced mandatory command parsing but setup failures were not
translated into wedging the GPU which was probably the intent.
Possible errors come in two categories. Either the sanity check on
internal
On 2/25/21 4:49 PM, Daniel Vetter wrote:
On Thu, Feb 25, 2021 at 11:44 AM Daniel Vetter wrote:
On Thu, Feb 25, 2021 at 11:28:31AM +0100, Christian König wrote:
Am 24.02.21 um 10:31 schrieb Daniel Vetter:
On Wed, Feb 24, 2021 at 10:16 AM Thomas Hellström (Intel)
wrote:
On 2/24/21 9:45 AM, D
== Series Details ==
Series: drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested
during PHY Layer testing. (rev2)
URL : https://patchwork.freedesktop.org/series/80911/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9810 -> Patchwork_19731
=
Hi
Am 25.02.21 um 11:23 schrieb Daniel Vetter:
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a
== Series Details ==
Series: drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested
during PHY Layer testing. (rev2)
URL : https://patchwork.freedesktop.org/series/80911/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a9246c77517c drm/i915/dp: DPTX writes Swing/Pr
Hi
Am 25.02.21 um 10:53 schrieb Pavel Machek:
Hi!
This is in -next, but I get same behaviour on 5.11; and no, udl does
Thanks for reporting. We are in the process of fixing the issue. The latest
patch is at [1].
Thank you, that fixes the DMA issue, and I can use the udl.
...for a while.
Source needs to write DPCD 103-106 after receiving a PHY request to change
swing/pre-emphasis after reading DPCD 206-207. This is especially needed if
there is a retimer between source and sink and the retimer implements AUX_CH
interception scheme to manage DP PHY settings (e.g. adjusting Swing/Pre
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