From: Juston Li
Like the patch to disable QSES for HDCP 1.4 over MST
https://patchwork.freedesktop.org/patch/415297/ the HDCP2.2 spec
doesn't require QSES as well and we've seen QSES not supported on a
couple HDCP2.2 docks so far (Dell WD19 and Lenovo LDC-G2)
Remove it for now until we get a bet
Floating a stand-alone patch form the below series in order to
merge it.
https://patchwork.freedesktop.org/series/86325/
Juston Li (1):
drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 31 +---
1 file changed, 1 insertio
Pushed to drm-intel-next.
From: Intel-gfx On Behalf Of Patchwork
Sent: Thursday, January 28, 2021 12:36 PM
To: Sean Paul
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: Disable the QSES
check for HDCP 1.4 over MST (rev2)
Patch Details
Series:
d
On Wed, Jan 27, 2021 at 09:13:36PM +0200, Vudum, Lakshminarayana wrote:
> I am not totally sure why shard run is not triggered here
> https://patchwork.freedesktop.org/series/8/#rev2
> @Latvala, Petri any help here?
The results were there but reporting it failed. Re-reported it and
it's now o
== Series Details ==
Series: drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST (rev2)
URL : https://patchwork.freedesktop.org/series/8/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9666_full -> Patchwork_19447_full
===
== Series Details ==
Series: Final set of patches for ADLS enabling (rev2)
URL : https://patchwork.freedesktop.org/series/86322/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9690 -> Patchwork_19525
Summary
---
**SUC
== Series Details ==
Series: Final set of patches for ADLS enabling (rev2)
URL : https://patchwork.freedesktop.org/series/86322/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i
On 1/27/21 8:48 AM, Souza, Jose wrote:
> On Wed, 2021-01-27 at 07:07 -0800, Lucas De Marchi wrote:
>> On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:
>>> From: Caz Yokoyama
>>>
>>> The crwebview indicates on ADL-S that some of our MCHBAR
>>> registers have moved from their tradition
== Series Details ==
Series: Final set of patches for ADLS enabling (rev2)
URL : https://patchwork.freedesktop.org/series/86322/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
36f14b084aab drm/i915/adl_s: Update PHY_MISC programming
8cede37510f4 drm/i915/adl_s: MCHBAR memory inf
On 1/26/21 9:22 PM, Matt Roper wrote:
> On Tue, Jan 26, 2021 at 08:11:58PM -0800, Aditya Swarup wrote:
>> - Extend permanent driver WA Wa_1409767108, Wa_14010685332
>> and Wa_14011294188 to adl-s.
>> - Extend permanent driver WA Wa_1606054188 to adl-s.
>> - Add Wa_14011765242 for adl-s A0 steppin
- Extend permanent driver WA Wa_1409767108, Wa_14010685332
and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.
v2:
- Extend Wa_14011765242 to STEP A1.(mdroper)
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt R
From: Anusha Srivatsa
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
Reviewed-by: Aditya Swarup
---
drivers/gpu/dr
From: Tejas Upadhyay
Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms. Update the values used
by our memory bandwidth calculations accordingly.
v2: Fix minor nitpick for shifting ADLS case above RKL(based on platform
order).(mdroper)
Bspec: 64631
- Extend Wa_1606931601 and Wa_1409804808 to ADL-S.
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)
v2:
- Extend Wa_1409804808 and remove unnecessary branching/redundant
adls workaround placeholder functions.
- Split WAs properly based o
From: José Roberto de Souza
- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
the cursor plane, let's group the handling together under
HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.
BSpec: 49251
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Vill
From: Lucas De Marchi
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
BSpec: 53597
Bspec: 49231
Cc: Imre Deak
Cc: Matt Roper
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Signed-off-by: Aditya Swarup
Reviewed-by: Matt Roper
From: Matt Roper
ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible. Let's re-use TGL's
firmware for ADL-S.
Bspec: 50668
Cc: John Harrison
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
Reviewed-b
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
v2: Simplify logic to a single if else chain and fix indents.(Lucas)
v3: Fix bug due
These are the final set of patches required for enabling ADL-S. The
patches have been tested on platform and all display outputs are
working.
v2: Address minor nitpicks provided by mdroper.
Patch "drm/i915/adl_s: MCHBAR memory info registers are moved"
can be ignored as Jose's submission
https:/
From: Matt Roper
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
Reviewed-by: Aditya Sw
On Wed, Jan 27, 2021 at 08:54:01AM -0800, Jose Souza wrote:
DRAM information is required to properly program display.
Before "drm/i915/gen11+: Only load DRAM information from pcode" we
were failing driver load if unable to fetch DRAM information from
pcode form GEN11+ but we should also extend it
On Wed, Jan 27, 2021 at 08:54:00AM -0800, Jose Souza wrote:
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that
== Series Details ==
Series: drm/i915: Disable runtime power management during shutdown
URL : https://patchwork.freedesktop.org/series/86362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19524_full
S
, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Juston-Li/drm-i915-hdcp-update-cp_irq_count_cached-in-intel_dp_hdcp2_read_msg/20210127-082615
base: git://anongit.freedesktop.org/drm-intel for-
== Series Details ==
Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19523_full
=
On Tue, Dec 15, 2020 at 10:42:19PM +, Andres Calderon Jaramillo wrote:
> From: Andres Calderon Jaramillo
>
> Prevent the ICL HDR plane pipeline from performing YUV color range
> correction twice when the input is in limited range. This is done by
> removing the limited-range code from icl_pro
On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/i915_irq.c | 36 -
> 1 file changed, 27 ins
== Series Details ==
Series: drm/i915/gt: Drop active.lock around active request read inside
execlists
URL : https://patchwork.freedesktop.org/series/86356/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19521_full
===
== Series Details ==
Series: drm: Move struct drm_device.pdev to legacy (rev5)
URL : https://patchwork.freedesktop.org/series/84205/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19519_full
Summary
--
On Wed, Jan 27, 2021 at 09:08:22AM -0500, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> Hopefully this is the last pull request towards 5.12.
>
> Please notice this contains a drm/framebuffer change needed for
> supporting clear color support for TGL Render Decompression.
>
> Here goes drm-intel
On Wed, 2021-01-27 at 20:19 +0200, Imre Deak wrote:
> At least on some TGL platforms PUNIT wants to access some display HW
> registers, but it doesn't handle display power managment (disabling
> DC
> states as required) and so this register access will lead to a hang.
> To
> prevent this disable ru
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for
HDCP 1.4 over MST
URL : https://patchwork.freedesktop.org/series/86325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9686_full -> Patchwork_19513_full
===
Quoting Randy Dunlap (2021-01-27 20:28:05)
> On 1/27/21 11:30 AM, Randy Dunlap wrote:
> > On 1/27/21 11:08 AM, Randy Dunlap wrote:
> >> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
> >>> Hi all,
> >>>
> >>> Note: the patch file has failed to upload :-(
> >>>
> >>> Changes since 20210125:
> >>>
> >>
On Wed, 2021-01-27 at 19:23 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's
On 1/27/21 11:30 AM, Randy Dunlap wrote:
> On 1/27/21 11:08 AM, Randy Dunlap wrote:
>> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Note: the patch file has failed to upload :-(
>>>
>>> Changes since 20210125:
>>>
>>
>> on x86_64:
>>
>> ../drivers/gpu/drm/i915/i915_gem.c: In func
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL : https://patchwork.freedesktop.org/series/86346/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19518_full
Summar
== Series Details ==
Series: drm/i915: Disable runtime power management during shutdown
URL : https://patchwork.freedesktop.org/series/86362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19524
Summary
---
== Series Details ==
Series: drm/i915: Disable runtime power management during shutdown
URL : https://patchwork.freedesktop.org/series/86362/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
207a500f0a86 drm/i915: Disable runtime power management during shutdown
-:7: WARNING:TYPO_
On 1/25/21 9:19 PM, a...@linux-foundation.org wrote:
> The mm-of-the-moment snapshot 2021-01-25-21-18 has been uploaded to
>
>https://www.ozlabs.org/~akpm/mmotm/
>
> mmotm-readme.txt says
>
> README for mm-of-the-moment:
>
> https://www.ozlabs.org/~akpm/mmotm/
>
> This is a snapshot of my
== Series Details ==
Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19523
===
On 1/27/21 11:08 AM, Randy Dunlap wrote:
> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>> Hi all,
>>
>> Note: the patch file has failed to upload :-(
>>
>> Changes since 20210125:
>>
>
> on x86_64:
>
> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
> ../drivers/gpu/drm/i9
I am not totally sure why shard run is not triggered here
https://patchwork.freedesktop.org/series/8/#rev2
@Latvala, Petri any help here?
Thanks,
Lakshmi.
-Original Message-
From: Gupta, Anshuman
Sent: Tuesday, January 26, 2021 11:38 PM
To: Vudum, Lakshminarayana ;
intel-gfx@lists
On 1/27/21 6:44 AM, Stephen Rothwell wrote:
> Hi all,
>
> Note: the patch file has failed to upload :-(
>
> Changes since 20210125:
>
on x86_64:
../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of
fu
== Series Details ==
Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86361/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be check
== Series Details ==
Series: series starting with [v13,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86361/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a69d1c74e99d drm/i915/display: Support PSR Multiple Instances
-:80:
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: Nuke not needed members of
dram_info
URL : https://patchwork.freedesktop.org/series/86360/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19522
==
== Series Details ==
Series: drm/i915/gt: Drop active.lock around active request read inside
execlists
URL : https://patchwork.freedesktop.org/series/86356/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19521
=
At least on some TGL platforms PUNIT wants to access some display HW
registers, but it doesn't handle display power managment (disabling DC
states as required) and so this register access will lead to a hang. To
prevent this disable runtime power management for poweroff and reboot.
Reported-and-te
== Series Details ==
Series: drm/i915/hdcp: mst streams type1 capability check
URL : https://patchwork.freedesktop.org/series/86345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19517_full
Summary
--
Re-reported.
From: Gupta, Anshuman
Sent: Wednesday, January 27, 2021 3:14 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Cc: Li, Juston
Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/4]
drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST
== Series Details ==
Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT
operation
URL : https://patchwork.freedesktop.org/series/86355/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19520
==
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for
HDCP 1.4 over MST
URL : https://patchwork.freedesktop.org/series/86325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9686 -> Patchwork_19513
=
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_statu
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handlin
== Series Details ==
Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT
operation
URL : https://patchwork.freedesktop.org/series/86355/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be chec
== Series Details ==
Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT
operation
URL : https://patchwork.freedesktop.org/series/86355/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5a1abb4304a2 drm/i915: make local-memory probing a GT operation
931
== Series Details ==
Series: drm: Move struct drm_device.pdev to legacy (rev5)
URL : https://patchwork.freedesktop.org/series/84205/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19519
Summary
---
*
== Series Details ==
Series: drm/i915/gt: Prefer local execution_mask for determing viable engines
URL : https://patchwork.freedesktop.org/series/86342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19516_full
== Series Details ==
Series: series starting with [v2,1/4] drm/i915/hdcp: Disable the QSES check for
HDCP 1.4 over MST
URL : https://patchwork.freedesktop.org/series/86325/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9686 -> Patchwork_19513
=
As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.
v2:
- Updated comment on top of "dram_info->wm_lv_0_adjust_needed =
!IS_GEN9_LP(i915);"
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that decided that the best alternative is
always apply the 16gb_dim
DRAM information is required to properly program display.
Before "drm/i915/gen11+: Only load DRAM information from pcode" we
were failing driver load if unable to fetch DRAM information from
pcode form GEN11+ but we should also extend it to GEN9 plaforms.
Signed-off-by: José Roberto de Souza
---
Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_dram.c | 47
On Wed, 2021-01-27 at 07:07 -0800, Lucas De Marchi wrote:
> On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama
> >
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX offsets to
> > new locations. T
== Series Details ==
Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL : https://patchwork.freedesktop.org/series/86346/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19518
Summary
---
On Wed, 2021-01-27 at 06:49 -0800, Lucas De Marchi wrote:
> On Wed, Jan 20, 2021 at 07:16:09AM -0800, Jose Souza wrote:
> > Up to now we were reading some DRAM information from MCHBAR register
> > and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
> > platforms have MCHBAR DRAM
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> Let's prefer to use explicit request tracking and bounded timeouts in
> our selftests.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedeskto
== Series Details ==
Series: drm/i915/bios: tidy up child device debug logging
URL : https://patchwork.freedesktop.org/series/86341/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19515_full
Summary
--
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> In construction the rpcs_query batch we know that it is device coherent
> and ready for execution, the set-to-gtt-domain here is redudant.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
_
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> After the memory-region test completes, it flushes the test by calling
> set-to-cpu-domain. Use the igt_flush_test as it includes a timeout,
> recovery and reports and error for miscreant tests.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mat
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> Since the vma's backing store is flushed upon first creation, remove the
> manual calls to set-to-gtt-domain.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Int
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> After running client_blt, we flush the object by changing its domain.
> This causes us to wait forever instead of an bounded wait suitable for
> the selftest timeout. So do an explicit wait with a suitable timeout --
> which in turn means we ha
On 27/01/2021 15:44, Chris Wilson wrote:
Quoting Chris Wilson (2021-01-27 15:33:05)
Quoting Tvrtko Ursulin (2021-01-27 15:10:43)
On 25/01/2021 14:01, Chris Wilson wrote:
Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a s
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> Instead of manipulating the object's cache domain, just use the device
> coherent map to write the batch buffer.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
On Mon, 25 Jan 2021 at 14:18, Chris Wilson wrote:
>
> Set the cache coherency and status using the set-coherency helper.
> Otherwise, we forget to mark the new pages as cache dirty.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gf
Quoting Chris Wilson (2021-01-27 15:33:05)
> Quoting Tvrtko Ursulin (2021-01-27 15:10:43)
> >
> > On 25/01/2021 14:01, Chris Wilson wrote:
> > > Replace the priolist rbtree with a skiplist. The crucial difference is
> > > that walking and removing the first element of a skiplist is O(1), but
> >
Quoting Tvrtko Ursulin (2021-01-27 15:10:43)
>
> On 25/01/2021 14:01, Chris Wilson wrote:
> > Replace the priolist rbtree with a skiplist. The crucial difference is
> > that walking and removing the first element of a skiplist is O(1), but
>
> I wasn't (and am not) familiar with them, but wikiped
On 25/01/2021 14:01, Chris Wilson wrote:
Wrap cmpxchg64 with a try_cmpxchg()-esque helper. Hiding the old-value
dance in the helper allows for cleaner code.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_utils.h | 32 +++
1 file changed, 32 insertions
Chris Wilson writes:
> As we find the active request for capturing upon a hang, we know that the
> lists are stable as we are inside the execlists tasklet, the only path
> that can modify those lists. As such, we do not need to disable irqs and
> take the active lock for a simple read of the curr
Quoting Pandey, Hariom (2021-01-27 15:10:53)
> Hi Chris,
>
> (i) To your concern on the GPU dying issue gitlab#2743 --> this issue has
> been resolved and not observed in last 3 runs --> The gitlab had been updated
> with the pass results and closed.
> (ii) RocketLate platform has been setup in
On Tue, Jan 26, 2021 at 08:11:56PM -0800, Aditya Swarup wrote:
From: Anusha Srivatsa
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Anusha Srivatsa
Signed-off-b
Hi Chris,
(i) To your concern on the GPU dying issue gitlab#2743 --> this issue has been
resolved and not observed in last 3 runs --> The gitlab had been updated with
the pass results and closed.
(ii) RocketLate platform has been setup in Public CI with the name "
fi-rkl-11500t" --> https://int
On 25/01/2021 14:01, Chris Wilson wrote:
Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but
I wasn't (and am not) familiar with them, but wikipedia page says
removal is O(logN) average case to O(N) wors
On Tue, Jan 26, 2021 at 08:11:52PM -0800, Aditya Swarup wrote:
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
v2: Simplify logic to
== Series Details ==
Series: drm/i915/hdcp: mst streams type1 capability check
URL : https://patchwork.freedesktop.org/series/86345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19517
Summary
---
*
On Wed, Jan 20, 2021 at 07:16:11AM -0800, Jose Souza wrote:
As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dram.c | 10 +-
drivers
Quoting Tvrtko Ursulin (2021-01-27 14:50:19)
>
> On 27/01/2021 14:35, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-27 14:13:11)
> >>
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>> Move the scheduler pretty printer from out of the execlists state to
> >>> match its more common locat
On 27/01/2021 14:35, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-01-27 14:13:11)
On 25/01/2021 14:01, Chris Wilson wrote:
Move the scheduler pretty printer from out of the execlists state to
match its more common location.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/int
== Series Details ==
Series: HDCP 2.2 DP errata
URL : https://patchwork.freedesktop.org/series/86340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687_full -> Patchwork_19514_full
Summary
---
**SUCCESS**
No regr
On Wed, Jan 20, 2021 at 07:16:09AM -0800, Jose Souza wrote:
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that
On Wed, Jan 20, 2021 at 07:29:37PM +, Jose Souza wrote:
On Wed, 2021-01-20 at 10:52 -0800, Lucas De Marchi wrote:
On Wed, Jan 20, 2021 at 10:42:46AM -0800, Jose Souza wrote:
> On Wed, 2021-01-20 at 10:31 -0800, Lucas De Marchi wrote:
> > On Wed, Jan 20, 2021 at 07:16:08AM -0800, Jose Souza w
Quoting Tvrtko Ursulin (2021-01-27 14:13:11)
>
> On 25/01/2021 14:01, Chris Wilson wrote:
> > Move the scheduler pretty printer from out of the execlists state to
> > match its more common location.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34
On Fri, Dec 04, 2020 at 05:08:39PM -0800, Aditya Swarup wrote:
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
v2: Simplify logic to
== Series Details ==
Series: drm/i915/gt: Prefer local execution_mask for determing viable engines
URL : https://patchwork.freedesktop.org/series/86342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19516
Quoting Tvrtko Ursulin (2021-01-27 14:10:55)
>
> + Matt to check on how this fits with GuC. This patch and a few before
> it in this series.
>
> The split between physical and scheduling engine (i915_sched_engine)
> makes sense to me. Gut feeling says it should work for GuC as well, in
> princ
On 25/01/2021 14:01, Chris Wilson wrote:
Move the scheduler pretty printer from out of the execlists state to
match its more common location.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 +--
1 file changed, 19 insertions(+), 15 deletio
+ Matt to check on how this fits with GuC. This patch and a few before
it in this series.
The split between physical and scheduling engine (i915_sched_engine)
makes sense to me. Gut feeling says it should work for GuC as well, in
principle.
A small comment or two below:
On 25/01/2021 14:
Hi Dave and Daniel,
Hopefully this is the last pull request towards 5.12.
Please notice this contains a drm/framebuffer change needed for
supporting clear color support for TGL Render Decompression.
Here goes drm-intel-next-2021-01-27:
- HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman)
- F
As we find the active request for capturing upon a hang, we know that the
lists are stable as we are inside the execlists tasklet, the only path
that can modify those lists. As such, we do not need to disable irqs and
take the active lock for a simple read of the current request.
Suggested-by: Mik
== Series Details ==
Series: drm/i915/bios: tidy up child device debug logging
URL : https://patchwork.freedesktop.org/series/86341/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9687 -> Patchwork_19515
Summary
---
*
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