On Fri, Nov 27, 2020 at 02:57:48PM +, Chris Wilson wrote:
We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
hotplug. These are early gen3 and gen2 devices that now explode on boot
as they try to access non-existent registers.
humn... true, my bad. But I don't think a reve
== Series Details ==
Series: drm/i915: Disable outputs during unregister
URL : https://patchwork.freedesktop.org/series/84371/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19008
Summary
---
**FAILU
== Series Details ==
Series: drm/i915/gem: Differentiate oom failures from invalid map types
URL : https://patchwork.freedesktop.org/series/84365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9401_full -> Patchwork_19006_full
==
== Series Details ==
Series: drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly"
URL : https://patchwork.freedesktop.org/series/84368/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19007
Switch off the scanout during driver unregister, so we can shutdown the
HW immediately for unbind.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 320856b66
== Series Details ==
Series: drm/i915/gem: Differentiate oom failures from invalid map types
URL : https://patchwork.freedesktop.org/series/84365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19006
Summar
While we want the capture to last long enough to delay the concurrent
client, we don't want to wait forever for the capture to complete to
proceed with the testing.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2559
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_capture.c | 12 +
On Fri, 2020-11-27 at 21:00 +, Chris Wilson wrote:
> We know a problem exists in the ifwi shipped with the early
> pre-production Tigerlake and DG1 prototypes, later revisions are fine.
> However, CI still relies on the earlier ifwi and we grow tired of
> the volume of warnings as we wait for r
We know a problem exists in the ifwi shipped with the early
pre-production Tigerlake and DG1 prototypes, later revisions are fine.
However, CI still relies on the earlier ifwi and we grow tired of
the volume of warnings as we wait for replacements.
Since the warning is a bug, we do not want to los
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev8)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19004_full
=
Quoting Pandey, Hariom (2020-10-28 11:55:04)
> Ok, I have initiated the steps to upgrade the CI machine's silicon & BIOS.
The single ehl we have in CI is still failing to enter rc6, both in the
selftest and runtime testing. And I note that RAPL doesn't recognise it,
so it doesn't report the power
Quoting Matthew Auld (2020-11-27 12:04:42)
> From: Daniele Ceraolo Spurio
>
> These functions are independent from the backend used and can therefore
> be split out of the exelists submission file, so they can be re-used by
> the upcoming GuC submission backend.
>
> Based on a patch by Chris Wil
Quoting Matthew Auld (2020-11-27 12:04:41)
> From: Chris Wilson
>
> We want to separate the utility functions for controlling the logical
> ring context from the execlists submission mechanism (which is an
> overgrown scheduler).
>
> This is similar to Daniele's work to split up the files, but b
Quoting Matthew Auld (2020-11-27 12:04:40)
> From: Chris Wilson
>
> Cleanup intel_lrc.h by moving some of the residual common register
> definitions into intel_lrc_reg.h, prior to rebranding and splitting off
> the submission backends.
>
> v2: keep the SCHEDULE enum in the old file, since it is
After a cursory check on the parameters to i915_gem_object_pin_map(),
where we return a precise error, if the backend rejects the mapping we
always return PTR_ERR(-ENOMEM). Let us also return a more precise error
here so we can differentiate between running out of memory and
programming errors (or
== Series Details ==
Series: Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
URL : https://patchwork.freedesktop.org/series/84352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19003_full
== Series Details ==
Series: drm/i915: remove trailing semicolon in macro definition
URL : https://patchwork.freedesktop.org/series/84354/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19005
Summary
--
Quoting Matthew Auld (2020-11-27 12:04:37)
> In igt_ppgtt_sanity_check we should also exercise the non-contiguous
> option for LMEM, since this will give us slightly different sg layouts
> and alignment.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
-Chris
___
Quoting t...@redhat.com (2020-11-27 16:28:28)
> From: Tom Rix
>
> The macro use will already have a semicolon.
>
> Signed-off-by: Tom Rix
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device
Quoting Matthew Auld (2020-11-27 12:06:08)
> +int
> +i915_gem_create_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
> +{
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i9
== Series Details ==
Series: drm/i915: remove trailing semicolon in macro definition
URL : https://patchwork.freedesktop.org/series/84354/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ba9e1a69788c drm/i915: remove trailing semicolon in macro definition
-:19: CHECK:MACRO_ARG_PR
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev8)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19004
S
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19001_full
Summary
== Series Details ==
Series: Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
URL : https://patchwork.freedesktop.org/series/84352/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19003
Summary
-
On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > Hi Daniel, Jani,
> >
> > is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missin
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84350/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19002
=
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with
direct call to tasklet
URL : https://patchwork.freedesktop.org/series/84345/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9398_full -> Patchwork_19000_full
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84350/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19001
Summary
---
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14)
URL : https://patchwork.freedesktop.org/series/68081/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14)
URL : https://patchwork.freedesktop.org/series/68081/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7f90737a12fb drm/i915/display: Add HDR Capability detection for LSPCON
a44d7eb6654e drm/i915/disp
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev7)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9398_full -> Patchwork_18998_full
=
From: Tom Rix
The macro use will already have a semicolon.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e67cec8f
Since we try and estimate how long we require to update the registers to
perform a plane update, it is of vital importance that we measure the
distribution of plane updates to better guide our estimate. If we
underestimate how long it takes to perform the plane update, we may
slip into the next sca
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with
direct call to tasklet
URL : https://patchwork.freedesktop.org/series/84345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_19000
==
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with
direct call to tasklet
URL : https://patchwork.freedesktop.org/series/84345/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit w
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18999
Summary
---
**FAILURE**
Serious unknown
On Fri, 27 Nov 2020, Chris Wilson wrote:
> We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
> hotplug. These are early gen3 and gen2 devices that now explode on boot
> as they try to access non-existent registers.
>
> Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for
On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> Hi Daniel, Jani,
>
> is it ok to merge this patch along with 2/2 via the i915 tree?
Ack from mesa (userspace in general, but mesa is kinda mandatory) is
missing I think. With that
Acked-by: Daniel Vetter
>
> --Imre
>
> On Mon, Nov
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter
or member 'ww' not described in 'i9
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem_execbuffer.
We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
hotplug. These are early gen3 and gen2 devices that now explode on boot
as they try to access non-existent registers.
Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for hpd_irq_setup")
Signed-off-by: Chris Wilson
Cc: Lu
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecc99f864651 drm/i915/selftest: also consider non-contiguous objects
3c1e72a3ebbe drm/i915/selftest: assert we get 2M GTT pages
-
On Fri, Nov 27, 2020 at 02:33:10AM +0530, Uma Shankar wrote:
> Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
> Create a separate mechanism for lspcon compared to HDMI in order to
> address the same and ensure future scalability.
>
> v2: Streamlined this as per Ville's sugge
On Fri, Nov 27, 2020 at 02:33:13AM +0530, Uma Shankar wrote:
> Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes.
> Check for that when using LSPCON.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
> 1 file changed, 9 inserti
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev7)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18998
S
On Wed, Nov 25, 2020 at 05:52:10PM +, Souza, Jose wrote:
> On Wed, 2020-11-25 at 18:17 +0200, Ville Syrjälä wrote:
> > On Tue, Nov 24, 2020 at 10:03:35PM +, Souza, Jose wrote:
> > > On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > > > There are some corner cases wrt underrun when w
Quoting Matthew Auld (2020-11-27 12:07:16)
> From: Venkata Ramana Nayana
>
> This is to fix a bug in upstream
> commit a6326a4f8ffb ("drm/i915/gt: Keep a no-frills swappable copy of the
> default context state")
>
> We allocate context state obj ce->state from lmem, so in
> __engines_record_de
Quoting Matthew Auld (2020-11-27 12:07:13)
> From: Tvrtko Ursulin
>
> Current code uses jiffie time to do the accounting and then does:
>
> diff = jiffies - start;
> msec = diff * 1000 / HZ;
> ...
> atomic_long_add(msec, &i915->time_swap_out_ms);
>
> If we assume jiffie can be as non-gr
Quoting Matthew Auld (2020-11-27 12:07:06)
> From: CQ Tang
>
> When cache_level is NONE, we check HAS_LLC(i915).
> But additionally for DGFX, we also need to check
> HAS_SNOOP(i915) on system memory object to use
> I915_BO_CACHE_COHERENT_FOR_READ. on dg1, has_llc=0, and
> has_snoop=1. Otherwise,
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/d
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Add the calculations to set plane selective fetch registers depending
in the value of the area damaged.
It is still using the whole plane area as damaged but that will change
in next patches.
v2:
- fixed new_plane_state->uapi.dst.y2 typo in
intel_psr2_sel_fetch_update()
- do not shifthing new_plan
Quoting Matthew Auld (2020-11-27 12:07:04)
> From: Venkata Ramana Nayana
>
> In suspend mode use blitter eviction before disable the runtime
> interrupts and in resume use blitter after the gem resume happens.
Consider add it to the suspend prepare function.
-Chris
__
Hi Daniel, Jani,
is it ok to merge this patch along with 2/2 via the i915 tree?
--Imre
On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> From: Radhakrishna Sripada
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the dri
Quoting Matthew Auld (2020-11-27 12:07:03)
> From: Venkata Ramana Nayana
>
> If record default objects are created in LMEM and in suspend
> pin the pages of obj (src) and use blitter for eviction. But
> during request creation using blitter context and try to pin the same
> default object, to res
Quoting Matthew Auld (2020-11-27 12:07:02)
> From: Prathap Kumar Valsan
>
> During suspend we will lose all page tables as they are allocated in
> LMEM. In-order to make sure that the contexts do not access the
> corrupted page table after we restore, we are evicting all vma's that
> are bound t
Quoting Matthew Auld (2020-11-27 12:07:00)
> From: Venkata Ramana Nayana
>
> We are only doing it now for kernel_context. We also need to do for the
> copy engine blitter context.
>
> Signed-off-by: Venkata Ramana Nayana
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +
> 1 file ch
Quoting Matthew Auld (2020-11-27 12:06:59)
> +static int intel_dmem_evict_buffers(struct drm_device *dev, bool in_suspend)
> +{
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct drm_i915_gem_object *obj;
> + struct intel_memory_region *mem;
> + int id, ret = 0;
>
Quoting Matthew Auld (2020-11-27 12:06:57)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 82f431cc38cd..6f0ab363bdee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1225,6 +1225,11 @@ struct drm_i915_private {
>
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev7)
URL : https://patchwork.freedesktop.org/series/84174/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
36f4f615f69a drm/i915/display: Record the plane update times for debugging
-:73:
Quoting Matthew Auld (2020-11-27 12:06:56)
> From: Ramalingam C
>
> window_blt_copy feature is used for swapin and swapout based on the i915
> module parameter called enable_eviction.
A module parameter?
-Chris
___
Intel-gfx mailing list
Intel-gfx@list
Quoting Matthew Auld (2020-11-27 12:06:53)
> +int i915_window_blt_copy(struct drm_i915_gem_object *dst,
> +struct drm_i915_gem_object *src)
> +{
> + struct drm_i915_private *i915 = to_i915(src->base.dev);
> + struct intel_context *ce = i915->gt.engine[BCS0]->blit
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18997
=
== Series Details ==
Series: drm/i915/gt: Declare gen9 has 64 mocs entries!
URL : https://patchwork.freedesktop.org/series/84339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9397_full -> Patchwork_18996_full
Summary
-
Quoting Matthew Auld (2020-11-27 12:06:50)
> From: Sudeep Dutt
>
> Signed-off-by: Sudeep Dutt
> ---
> drivers/gpu/drm/i915/gem/i915_gem_region.c | 16 ++--
> drivers/gpu/drm/i915/i915_debugfs.c| 3 +++
> drivers/gpu/drm/i915/i915_drv.h| 2 ++
> 3 files changed,
On Fri, 2020-11-27 at 12:50 +0200, Gwan-gyeong Mun wrote:
> From: José Roberto de Souza
>
> The calculation the offsets of the main surface will be needed by PSR2
> selective fetch code so here splitting and exporting it.
> No functional changes were done here.
>
> v3: Rebased
>
> Cc: Gwan-gyeo
Quoting Matthew Auld (2020-11-27 12:06:49)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1366b53ac8c9..7b1e95d494e6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1214,6 +1214,9 @@ struct drm_i915_private {
>
Quoting Matthew Auld (2020-11-27 12:06:44)
> From: CQ Tang
>
> Function i915_gem_shrink_memory_region() is changed to
> intel_memory_region_evict() and moved from i915_gem_shrinker.c
> to intel_memory_region.c, this function is used to handle local
> memory swapping, in addition to evict purgeabl
Quoting Matthew Auld (2020-11-27 12:06:42)
> From: Bommu Krishnaiah
>
> Update shmem available memory in “intel_memory_region”
Was avail ever set?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/l
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, November 27, 2020 7:15 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v12 08/15] drm/i915/display: Enable colorspace programming for
> LSPCON devices
>
> On Fri, Nov 27, 2020 at 02:33:07AM +0530, U
Quoting Matthew Auld (2020-11-27 12:06:41)
> From: Venkata Sandeep Dhanalakota
>
> when allocating pages to lmem object of size 4G or greater
> we allocate memory blocks from buddy system.
Any lmem object is from the buddy system.
> In this scenario
> buddy sytem can allocate blocks that can ha
Quoting Matthew Auld (2020-11-27 12:06:40)
> From: Michel Thierry
Rationale goes here.
Is this wise? HWSP is very frequently read by the CPU, and expected to
be cached on the CPU.
What do the performance profiles indicate?
-Chris
___
Intel-gfx mailing
Enable HDMI Colorspace for LSPCON based devices. Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
v2: Dropped state managed in drm core as pe
Content type is supported on HDMI sink devices. Attached the
property for the same for LSPCON based devices.
v2: Added the content type programming when we are attaching
the property to connector, as suggested by Ville.
v3: Need to attach content type on intel_dp_add_properties
as creating of new
Quoting Matthew Auld (2020-11-27 12:06:34)
> From: Imre Deak
>
> On DG1 A0/B0 steppings the first 1MB of local memory must be reserved.
> One reason for this is that the 0xA-0xB range is not accessible
> by the display, probably since this region is redirected to another
> memory location
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0519f1c556bc drm/i915/display/psr: Calculate selective
Hi
Am 27.11.20 um 14:20 schrieb Joonas Lahtinen:
Quoting Thomas Zimmermann (2020-11-24 13:38:16)
Using struct drm_device.pdev is deprecated. Convert i915 to struct
drm_device.dev. No functional changes.
Signed-off-by: Thomas Zimmermann
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
On Fri, Nov 27, 2020 at 02:33:07AM +0530, Uma Shankar wrote:
> Enable HDMI Colorspace for LSPCON based devices. Sending Colorimetry
> data for HDR using AVI infoframe. LSPCON firmware expects this and though
> SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
> which transfer
Quoting Matthew Auld (2020-11-27 12:06:19)
> Based on a patch from Michel Thierry.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 31 ++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
>
Quoting Matthew Auld (2020-11-27 12:06:17)
> For the PTEs we get an LM bit, to signal whether the page resides in
> SMEM or LMEM.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Niranjana Vishwanathapura
> Si
Quoting Matthew Auld (2020-11-27 12:06:14)
> We need to general our accessor for the page directories and tables from
> using the simple kmap_atomic to support local memory, and this setup
> must be done on acquisition of the backing storage prior to entering
> fence execution contexts. Here we rep
Quoting Matthew Auld (2020-11-27 12:06:13)
> From: Zbigniew Kempczyński
>
> IGTs should be able to choose testing strategy depending on memory
> regions and its sizes. Add region instance number to make this
> easier and descriptive.
>
> Cc: Matthew Auld
> Cc: Ramalingam C
> Cc: Tvrtko Ursulin
Quoting Matthew Auld (2020-11-27 12:06:09)
> From: Michel Thierry
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/gt/intel_ring.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
Hi Dave & Daniel -
Last feature pull for v5.11.
drm-intel-next-queued-2020-11-27:
drm/i915 features for v5.11:
Highlights:
- Enable big joiner to join two pipes to one port to overcome pipe restrictions
(Manasi, Ville, Maarten)
Display:
- More DG1 enabling (Lucas, Aditya)
- Fixes to cases wi
Quoting Zhenyu Wang (2020-11-24 05:13:59)
> On 2020.11.23 11:32:38 +0200, Joonas Lahtinen wrote:
> > Quoting Zhenyu Wang (2020-11-23 11:05:17)
> > >
> > > Hi,
> > >
> > > Here's gvt next pull for v5.11. Mostly it's for host suspend/resume
> > > fix with vGPU active and with some other enhancement
Quoting Matthew Auld (2020-11-27 12:06:08)
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support setting an immutable-priority-list of potential
> placements, at creation time.
>
> If
Quoting Thomas Zimmermann (2020-11-24 13:38:16)
> Using struct drm_device.pdev is deprecated. Convert i915 to struct
> drm_device.dev. No functional changes.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
Any chance of sharing used a cocci scri
Quoting Xing Zhengjun (2020-11-27 01:51:41)
>
>
> On 11/27/2020 5:34 AM, Chris Wilson wrote:
> > Quoting Xing Zhengjun (2020-11-26 01:44:55)
> >>
> >>
> >> On 11/25/2020 4:47 AM, Chris Wilson wrote:
> >>> Quoting Oliver Sang (2020-11-19 07:20:18)
> On Fri, Nov 13, 2020 at 04:27:13PM +0200, J
+ intel-gfx mailing list
Quoting ira.we...@intel.com (2020-11-24 08:07:41)
> From: Ira Weiny
>
> The pattern of kmap/mem*/kunmap is repeated. Use the new mem*_page()
> calls instead.
>
> Cc: Patrik Jakobsson
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Ira We
Since schedule-in and schedule-out are now both always under the tasklet
bitlock, we can reduce the individual atomic operations to simple
instructions and worry less.
This notably eliminates the race observed with intel_context_inflight in
__engine_unpark().
Closes: https://gitlab.freedesktop.or
Rather than having special case code for opportunistically calling
process_csb() and performing a direct submit while holding the engine
spinlock for submitting the request, simply call the tasklet directly.
This allows us to retain the direct submission path, including the CS
draining to allow fas
== Series Details ==
Series: drm/i915/gt: Declare gen9 has 64 mocs entries!
URL : https://patchwork.freedesktop.org/series/84339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9397 -> Patchwork_18996
Summary
---
**SU
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c| 15
drivers/gpu/drm/i915/i915_params.c | 5 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_memory_region.c | 11 +--
drivers/gpu/drm/i915/intel_region_lmem.c | 96 ---
From: Venkata Ramana Nayana
Use I915_MAP_WC when default state object is allocated on LMEM.
Signed-off-by: Venkata Ramana Nayana
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c
b/drivers/gpu
From: Venkata Ramana Nayana
Add ww locks during suspend/resume.
Signed-off-by: Venkata Ramana Nayana
---
drivers/gpu/drm/i915/i915_drv.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i91
From: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c3d9b36ef651..603976b9a973 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/driv
From: Venkata Ramana Nayana
This is to fix a bug in upstream
commit a6326a4f8ffb ("drm/i915/gt: Keep a no-frills swappable copy of the
default context state")
We allocate context state obj ce->state from lmem, so in
__engines_record_defaults(),
we call shmem_create_from_object(). Because it is
1 - 100 of 279 matches
Mail list logo
