== Series Details ==
Series: drm/i915/tgl, rkl, dg1: Apply WA_1406941453 to TGL, RKL and DG1
URL : https://patchwork.freedesktop.org/series/83383/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18836_full
==
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18835_full
===
== Series Details ==
Series: End to end Big Joiner enabling
URL : https://patchwork.freedesktop.org/series/83379/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18834_full
Summary
---
**FAILURE*
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes (rev2)
URL : https://patchwork.freedesktop.org/series/83373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18833_full
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for
emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18832_full
== Series Details ==
Series: drm/i915/display: Use initial_fastset_check() to compute and apply the
initial PSR state
URL : https://patchwork.freedesktop.org/series/83375/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18831_full
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev3)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic changes. [Uma]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
between commit:
e8a982355f96 ("drm/amd/display: Add tracepoint for amdgpu_dm")
from the amdgpu tree and commit:
29b77ad7b9ca ("drm/atomic: Pass the full state to CR
== Series Details ==
Series: drm/i915/tgl, rkl, dg1: Apply WA_1406941453 to TGL, RKL and DG1
URL : https://patchwork.freedesktop.org/series/83383/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18836
Summar
== Series Details ==
Series: drm/i915/ehl: Remove invalid PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/83292/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18829_full
Summary
---
On 11/2/20 7:52 PM, Tvrtko Ursulin wrote:
On 02/11/2020 02:00, Lu Baolu wrote:
Hi Tvrtko,
On 10/12/20 4:44 PM, Tvrtko Ursulin wrote:
On 29/09/2020 01:11, Lu Baolu wrote:
Hi Tvrtko,
On 9/28/20 5:44 PM, Tvrtko Ursulin wrote:
On 27/09/2020 07:34, Lu Baolu wrote:
Hi,
The previous post of th
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18835
=
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83382/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_psr.c:1737: warning:
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83382/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83382/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4a0e36485e2f drm/i915/display: Support PSR Multiple Transcoders
-:207:
This workaround is applicable only for tgl,rkl and dg1.
Bspec: 52890, 53273, 53508.
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handlin
== Series Details ==
Series: End to end Big Joiner enabling
URL : https://patchwork.freedesktop.org/series/83379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18834
Summary
---
**SUCCESS**
No re
== Series Details ==
Series: End to end Big Joiner enabling
URL : https://patchwork.freedesktop.org/series/83379/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_re
Hi all,
After merging the drm-misc-fixes tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
drivers/gpu/drm/vc4/vc4_drv.c: In function 'vc4_drm_unbind':
drivers/gpu/drm/vc4/vc4_drv.c:322:18: warning: unused variable 'vc4'
[-Wunused-variable]
322 | struct vc4_dev *v
== Series Details ==
Series: End to end Big Joiner enabling
URL : https://patchwork.freedesktop.org/series/83379/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a52bb0c934e9 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
8b0f35b9e8c3 drm/i915: Move enco
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v9:
* pipe_mode in state dump nd state check (Ville)
v8:
* Add pipe_mode in readou
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
From: Maarten Lankhorst
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
* hw.r
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.
From: Maarten Lankhorst
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Signed
No functional changes, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file chang
Maarten Lankhorst (6):
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
drm/i915: Try to make bigjoiner work in atomic check
drm/i915: Link planes in a bigjoiner configuration, v3.
drm/i915: Add bigjoin
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+),
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
b
From: Maarten Lankhorst
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, w
From: Maarten Lankhorst
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied fr
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
On Mon, 2020-11-02 at 13:09 +0530, Tejas Upadhyay wrote:
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
>
> Bspec : 33451
>
> Changes since V1:
> - Modifi
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes (rev2)
URL : https://patchwork.freedesktop.org/series/83373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18833
==
== Series Details ==
Series: drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
URL : https://patchwork.freedesktop.org/series/83362/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9246_full -> Patchwork_18828_full
== Series Details ==
Series: drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms (rev2)
URL : https://patchwork.freedesktop.org/series/83233/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9246_full -> Patchwork_18827_full
=
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes (rev2)
URL : https://patchwork.freedesktop.org/series/83373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
22e7ae4c328f drm/i915/dp: Some reshuffl
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for
emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18832
==
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v9:
* pipe_mode in state dump nd state check (Ville)
v8:
* Add pipe_mode in readou
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for
emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each comm
== Series Details ==
Series: drm/i915/display: Use initial_fastset_check() to compute and apply the
initial PSR state
URL : https://patchwork.freedesktop.org/series/83375/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18831
==
In a simple test case that writes to scratch and then busy-waits for the
batch to be signaled, we observe that the signal is before the write is
posted. That is bad news.
Splitting the flush + write_dword into two separate flush_dw prevents
the issue from being reproduced, we can presume the post-
Replace the previous approach to force compute the initial PSR state
after i915 take over from firmware by the better and recently added
initial_fastset_check() hook.
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
drivers/gpu/drm/i915
Add another lower level to emit_ggtt_write so that the GGTT nature of
the write is not hardcoded into the emitter.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 55 --
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/d
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18830
=
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b5a70599ee92 drm/i915/dp: Some reshuffling in
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6 insertions(+),
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
No functional changes, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file chang
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v9:
* pipe_mode in state dump nd state check (Ville)
v8:
* Add pipe_mode in readou
== Series Details ==
Series: drm/i915/ehl: Remove invalid PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/83292/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18829
Summary
---
**SUCCES
On Mon, Nov 02, 2020 at 10:48:54AM +0100, Hans de Goede wrote:
> Hi,
>
> On 11/1/20 6:41 PM, rwri...@hpe.com wrote:
> > From: Randy Wright
> >
> > For several months, I've been experiencing GPU hangs when starting
> > Cinnamon on an HP Pavilion Mini 300-020 if I try to run an upstream
> > kerne
Update the EHL PCI IDs from BSpec.
Remove the invalid ones.
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..ac8
== Series Details ==
Series: drm/i915/ehl: Remove invalid PCI ID
URL : https://patchwork.freedesktop.org/series/83292/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9230 -> Patchwork_18820
Summary
---
**SUCCESS**
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, November 2, 2020 9:29 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID
>
> On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Srivatsa wrote:
> > Update t
On Thu, 2020-10-29 at 21:37 +, Mun, Gwan-gyeong wrote:
> On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> > Add the calculations to set plane selective fetch registers depending
> > in the value of the area damaged.
> > It is still using the whole plane area as damaged but that
Quoting Tvrtko Ursulin (2020-11-02 17:14:24)
>
> On 02/11/2020 15:33, Chris Wilson wrote:
> > + if (!f) {
> > + f = read_timestamp_frequency(fd);
> > + if (intel_gen(intel_get_drm_devid(fd)) == 11)
> > + f = 1250; /* icl!!! are you feeling alrigh
On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Srivatsa wrote:
> Update the EHL PCI IDs from BSpec.
> Remove the invalid ones.
>
> Cc: Ville Syrjälä
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
Pls sort out the ci fail so we can merge this.
> ---
> include/drm/i915_pciids.h
== Series Details ==
Series: drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
URL : https://patchwork.freedesktop.org/series/83362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9246 -> Patchwork_18828
Summary
--
On 02/11/2020 15:33, Chris Wilson wrote:
Use MI_MATH and MI_COND_BBE we can construct a loop that runs for a
precise number of clock cycles, as measured by the CTX_TIMESTAMP. We use
the CTX_TIMESTAMP (as opposed to the CS_TIMESTAMP) so that the elapsed
time is measured local to the context, and
== Series Details ==
Series: drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
URL : https://patchwork.freedesktop.org/series/83362/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
906ed3e10d17 drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
-:18: WARNING:BA
On 10/26/20 9:35 PM, Lucas De Marchi wrote:
> On Mon, Oct 26, 2020 at 09:32:26PM -0700, Lucas De Marchi wrote:
>> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
>> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
>> single macro that chooses the correct
== Series Details ==
Series: drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms (rev2)
URL : https://patchwork.freedesktop.org/series/83233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9246 -> Patchwork_18827
===
On 02/11/2020 16:19, Chris Wilson wrote:
Since __vma_release is run by a kworker after the fence has been
signaled, it is no longer protected by the active reference on the vma,
and so the alias of vw->pinned to vma->obj is also not protected by a
reference on the object. Add an explicit refere
Since __vma_release is run by a kworker after the fence has been
signaled, it is no longer protected by the active reference on the vma,
and so the alias of vw->pinned to vma->obj is also not protected by a
reference on the object. Add an explicit reference for vw->pinned so it
will always be safe.
== Series Details ==
Series: vfio/pci: Refine Intel IGD OpRegion support (rev3)
URL : https://patchwork.freedesktop.org/series/79293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9242_full -> Patchwork_18825_full
Summary
-
Use MI_MATH and MI_COND_BBE we can construct a loop that runs for a
precise number of clock cycles, as measured by the CTX_TIMESTAMP. We use
the CTX_TIMESTAMP (as opposed to the CS_TIMESTAMP) so that the elapsed
time is measured local to the context, and the length of the batch is
unaffected by pre
On Wed, Oct 28, 2020 at 04:15:26PM -0300, Jason Gunthorpe wrote:
> Since commit 9a40401cfa13 ("lib/scatterlist: Do not limit max_segment to
> PAGE_ALIGNED values") the max_segment input to sg_alloc_table_from_pages()
> does not have to be any special value. The new algorithm will always
> create so
== Series Details ==
Series: drm/i915/rkl: new rkl ddc map for different PCH (rev3)
URL : https://patchwork.freedesktop.org/series/83154/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9245 -> Patchwork_18826
Summary
---
On Mon, Nov 02, 2020 at 10:28:34AM +0100, Daniel Vetter wrote:
> > --- a/include/linux/swiotlb.h
> > +++ b/include/linux/swiotlb.h
> > @@ -5,6 +5,9 @@
> > #include
> > #include
> > #include
> > +#ifndef CONFIG_SWIOTLB
> > +#include
> > +#endif
No conditional includes please. And the proper
== Series Details ==
Series: drm/i915/rkl: new rkl ddc map for different PCH (rev3)
URL : https://patchwork.freedesktop.org/series/83154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0a38bfa9c23 drm/i915/rkl: new rkl ddc map for different PCH
-:11: WARNING:UNKNOWN_COMMIT_ID:
After boot into kernel. Driver configured ddc pin mapping based on
predefined table in parse_ddi_port(). Now driver configure rkl
ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
give incorrect gmbus port number to cause HDMI can't work.
Refer to commit d0a89527d06 ("drm/i915/rkl
On Mon, November 2, 2020 2:12 PM Matt Roper wrote:
>On Fri, Oct 30, 2020 at 07:55:35PM -0700, Lee, Shawn C wrote:
>> On Fri, Oct. 30, 2020, 5:35 p.m., Matt Roper wrote:
>> >On Fri, Oct 30, 2020 at 09:41:37PM +0800, Lee Shawn C wrote:
>> >> After boot into kernel. Driver configured ddc pin mapping
Similar bug:
drivers/gpu/drm/i915/display/intel_color.c:794 bdw_load_luts() error: we
previously assumed 'gamma_lut' could be null (see line 784)
regards,
dan carpenter
On Mon, Nov 02, 2020 at 04:07:36PM +0300, Dan Carpenter wrote:
> Hello Ville Syrjälä,
>
> This is a semi-automatic email abou
Hello Ville Syrjälä,
This is a semi-automatic email about new static checker warnings.
The patch 7852ddd5d60a: "drm/i915: Replace some gamma_mode ifs with
switches" from Sep 25, 2020, leads to the following Smatch complaint:
drivers/gpu/drm/i915/display/intel_color.c:765 ivb_load_luts()
On 02/11/2020 02:00, Lu Baolu wrote:
Hi Tvrtko,
On 10/12/20 4:44 PM, Tvrtko Ursulin wrote:
On 29/09/2020 01:11, Lu Baolu wrote:
Hi Tvrtko,
On 9/28/20 5:44 PM, Tvrtko Ursulin wrote:
On 27/09/2020 07:34, Lu Baolu wrote:
Hi,
The previous post of this series could be found here.
https://lor
== Series Details ==
Series: vfio/pci: Refine Intel IGD OpRegion support (rev3)
URL : https://patchwork.freedesktop.org/series/79293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9242 -> Patchwork_18825
Summary
---
On Mon, Nov 02, 2020 at 10:27:11AM +, Christoph Hellwig wrote:
> On Mon, Nov 02, 2020 at 10:28:34AM +0100, Daniel Vetter wrote:
> > > --- a/include/linux/swiotlb.h
> > > +++ b/include/linux/swiotlb.h
> > > @@ -5,6 +5,9 @@
> > > #include
> > > #include
> > > #include
> > > +#ifndef CONFIG_
On Mon, Nov 2, 2020 at 11:23 AM Michael S. Tsirkin wrote:
>
> On Mon, Nov 02, 2020 at 10:28:34AM +0100, Daniel Vetter wrote:
> > On Mon, Nov 2, 2020 at 2:43 AM Stephen Rothwell
> > wrote:
> > >
> > > Hi all,
> > >
> > > After merging the drm-misc tree, today's linux-next build (arm
> > > multi_v
On Mon, Nov 02, 2020 at 10:28:34AM +0100, Daniel Vetter wrote:
> On Mon, Nov 2, 2020 at 2:43 AM Stephen Rothwell wrote:
> >
> > Hi all,
> >
> > After merging the drm-misc tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> > In file included from drivers/gpu/drm/nou
On Mon, Nov 02, 2020 at 12:43:27PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> In file included from drivers/gpu/drm/nouveau/nouveau_ttm.c:26:
> include/linux/swiotlb.h: In function 'swiotl
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
From: Thomas Hellström
Stolen objects need to lock, and we may call put_pages when
refcount drops to 0, ensure all calls are handled correctly.
Idea-from: Thomas Hellström
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
pin_map needs the ww lock, so ensure we pin both before submission.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 3 +
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++
.../gpu/drm/i915/gt/selftest
Bypass the IGD initialization when -ENODEV returns,
that should be the case if opregion is not available for IGD
or within discrete graphics device's option ROM,
or host/lpc bridge is not found.
Then use of -ENODEV here means no special device resources found
which needs special care for VFIO, but
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
We are removing obj->mm.lock, and need to take the reservation lock
before we can pin pages. Move the pinning pages into the helper, and
merge gtt pwrite/pread preparation and cleanup paths.
The fence lock is also removed; it will conflict with fen
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
We need to lock the object to move it to the correct domain,
add the missing lock.
Signed-off-by: Maarten Lankhorst
---
Reviewed-by: Thomas Hellström
___
Intel-gfx mailing list
Intel-gfx@lists.freed
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
We need to take the obj lock to pin pages, so wait until the callers
have done so, before making the object unshrinkable.
Signed-off-by: Maarten Lankhorst
---
Reviewed-by: Thomas Hellström
___
Intel-gf
Hi,
On 11/1/20 6:41 PM, rwri...@hpe.com wrote:
> From: Randy Wright
>
> For several months, I've been experiencing GPU hangs when starting
> Cinnamon on an HP Pavilion Mini 300-020 if I try to run an upstream
> kernel. I reported this recently in
> https://gitlab.freedesktop.org/drm/intel/-/is
== Series Details ==
Series: drm/i915/jsl: Disable cursor clock gating in HDR mode (rev2)
URL : https://patchwork.freedesktop.org/series/83142/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9238_full -> Patchwork_18824_full
On Mon, Nov 2, 2020 at 2:43 AM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> In file included from drivers/gpu/drm/nouveau/nouveau_ttm.c:26:
> include/linux/swiotlb.h: In function 'swiotlb_max_mapp
On 11/2/20 9:48 AM, Maarten Lankhorst wrote:
Op 30-10-2020 om 16:08 schreef Thomas Hellström:
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
Pin in the caller, not in the work itself. This should also
work better for dma-fence annotations.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/
Hi Ram ,
Below series is reviewed by Uma and CI results are green.
New HDCP MST test are skipping since there is no HDCP and DP-MST coverage in CI.
But it have tested the new IGT test locally.
Could you please take a look at this in order to merge the series.
There is a typo require to fix in patch
Op 30-10-2020 om 15:18 schreef Thomas Hellström (Intel):
>
> On 10/30/20 11:11 AM, Maarten Lankhorst wrote:
>> Op 30-10-2020 om 10:26 schreef Thomas Hellström (Intel):
>>> On 10/16/20 12:43 PM, Maarten Lankhorst wrote:
We should not allow this any more, as it will break with the new userptr
>>
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