[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) URL : https://patchwork.freedesktop.org/series/82173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9100_full -> Patchwork_18630_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) URL : https://patchwork.freedesktop.org/series/82173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9098_full -> Patchwork_18629_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) URL : https://patchwork.freedesktop.org/series/82173/ State : success == Summary == CI Bug Log - changes from CI_DRM_9100 -> Patchwork_18630 ==

Re: [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:42 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA > Lspcon > > On Tue, Sep 15, 2020 at 02:30:38AM +0530, Uma Sh

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be chec

[Intel-gfx] [PATCH v3 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 s

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

On Tue, Oct 06, 2020 at 02:37:58AM +0300, Ville Syrjälä wrote: > On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote: > > On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote: > > > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote: > > > > The BIOS of at least one ASUS-Z170M

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote: > On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote: > > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote: > > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs > > > the 101b WRPLL PDIV divider v

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

On Sat, 2020-10-03 at 01:26 +, Patchwork wrote: > Patch Details > Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer > modifications > URL: https://patchwork.freedesktop.org/series/82351/ > State:failure > Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patc

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with fake lmem

On Thu, Oct 01, 2020 at 08:39:43AM +, Patchwork wrote: == Series Details == Series: series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with fake lmem URL : https://patchwork.freedesktop.org/series/82283/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9085_ful

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Mon, Oct 05, 2020 at 11:46:17PM +0300, Imre Deak wrote: > On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote: > > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > > Atm, if a full modeset is performed during the initial modeset the link > > > training will happen with un

Re: [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:49 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org; Anand, Vipin > Subject: Re: [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon > > On Tue, Sep 15, 2020 at 02:30:41AM +0530, U

Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:44 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 > devices > > On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma

Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:51 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for > LSPCON > > On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shan

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) URL : https://patchwork.freedesktop.org/series/82173/ State : success == Summary == CI Bug Log - changes from CI_DRM_9098 -> Patchwork_18629 ==

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Update gen12 forcewake table

On Fri, 2020-10-02 at 20:29 -0700, Matt Roper wrote: > The bspec's forcewake page was very stale and out of date for recent > platforms. The hardware team finally provided us with an updated gen12 > table (which applies to TGL, RKL, and DG1) and there are a lot of > changes. > > Bspec: 66696 > Cc

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)

== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be chec

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Rename i915_{save,restore}_state()

== Series Details == Series: drm/i915: Rename i915_{save,restore}_state() URL : https://patchwork.freedesktop.org/series/82388/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18628_full Summary ---

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Mon, Oct 05, 2020 at 11:51:02PM +0300, Ville Syrjälä wrote: > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > Atm, if a full modeset is performed during the initial modeset the link > > training will happen with uninitialized max DP rate and lane count. Make > > sure the correspon

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote: > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote: > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs > > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with > > bit#0 incorrectly s

[Intel-gfx] [PATCH v3 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be

[Intel-gfx] [PATCH v2 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be

[Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks

Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. v2: Fix negated condition in gen11_dsi_initial_fastset_check(). v3: Make sure to

Re: [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:48 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON > devices > > On Tue, Sep 15, 2020 at 02:30:40AM +0530, Uma Shank

Re: [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON

> -Original Message- > From: Ville Syrjälä > Sent: Tuesday, September 29, 2020 9:53 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v6 07/11] drm/i915/display: Implement DRM infoframe read for > LSPCON > > On Tue, Sep 15, 2020 at 02:30:43AM +0530, Uma Shank

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote: > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > Atm, if a full modeset is performed during the initial modeset the link > > training will happen with uninitialized max DP rate and lane count. Make > > sure the correspon

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Mon, Oct 05, 2020 at 11:40:44PM +0300, Ville Syrjälä wrote: > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > Atm, if a full modeset is performed during the initial modeset the link > > training will happen with uninitialized max DP rate and lane count. Make > > sure the correspon

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4)

== Series Details == Series: drm/i915/display/ehl: Limit eDP to HBR2 (rev4) URL : https://patchwork.freedesktop.org/series/82162/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18627_full Summary -

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18626_full Summary ---

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > Atm, if a full modeset is performed during the initial modeset the link > training will happen with uninitialized max DP rate and lane count. Make > sure the corresponding encoder state is initialized by adding an encoder > hook called du

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2)

== Series Details == Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2) URL : https://patchwork.freedesktop.org/series/82351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18625_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Rename i915_{save,restore}_state()

== Series Details == Series: drm/i915: Rename i915_{save,restore}_state() URL : https://patchwork.freedesktop.org/series/82388/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18628 Summary --- **SUCC

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > Atm, if a full modeset is performed during the initial modeset the link > training will happen with uninitialized max DP rate and lane count. Make > sure the corresponding encoder state is initialized by adding an encoder > hook called du

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit

On Sat, Oct 03, 2020 at 03:18:44AM +0300, Imre Deak wrote: > Some BIOSes set an unsupported/imprecise DP link rate (for instance on > TGL A stepping). Make sure that we do an encoder recompute and a modeset > in this case. > > Cc: Ville Syrjälä > Signed-off-by: Imre Deak Reviewed-by: Ville Syrj

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename i915_{save,restore}_state()

== Series Details == Series: drm/i915: Rename i915_{save,restore}_state() URL : https://patchwork.freedesktop.org/series/82388/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4c7a7c4e0a80 drm/i915: Rename i915_{save,restore}_state() -:120: CHECK:CAMELCASE: Avoid CamelCase: #120

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4)

== Series Details == Series: drm/i915/display/ehl: Limit eDP to HBR2 (rev4) URL : https://patchwork.freedesktop.org/series/82162/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18627 Summary --- **SU

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82383/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18624_full Summary ---

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks

On Mon, Oct 05, 2020 at 11:24:56PM +0300, Ville Syrjälä wrote: > On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote: > > Move the checks to decide whether a fastset is possible during the > > initial commit to an encoder hook. This check is really encoder specific > > and the next patch will

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > Atm, if a full modeset is performed during the initial modeset the link > training will happen with uninitialized max DP rate and lane count. Make > sure the corresponding encoder state is initialized by adding an encoder > hook called du

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks

On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote: > Move the checks to decide whether a fastset is possible during the > initial commit to an encoder hook. This check is really encoder specific > and the next patch will also require this adding a DP encoder specific > check. > > v2: Fix n

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18626 Summary --- **SUCC

Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote: > The BIOS of at least one ASUS-Z170M system with an SKL I have programs > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with > bit#0 incorrectly set. > > This happens with the > > "3840x2160": 30 262750 3840 3888 39

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i9

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0d2e2bc8cea7 drm/i915/jsl: Split EHL/JSL platform info and PCI ids -:163: CHECK:UNNECESSARY_PARENTHESES:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2)

== Series Details == Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2) URL : https://patchwork.freedesktop.org/series/82351/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18625

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JSL Voltage swing table

== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82383/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18624 Summary --- **SUCC

[Intel-gfx] [PATCH] drm/i915: Rename i915_{save,restore}_state()

From: Ville Syrjälä i915_{save,restore}_state() are actually all about the display. Currently they are split into display part + SWF part. But since the SWF part is also related to the display let's just move that part into its own thing and flip the roles around so that the current display part

[Intel-gfx] [PATCH CI] drm/i915/display/ehl: Limit eDP to HBR2

Recent update in documentation defeatured eDP HBR3 for EHL and JSL. v2: - Remove dead code in ehl_get_combo_buf_trans() v3: - Rebase BSpec: 32247 Cc: Matt Roper Cc: Vidya Srinivas Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 9

[Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

Split the basic platform definition, macros, and PCI IDs to differentiate between EHL and JSL platforms. Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERL

[Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

JSL has update in vswing table for eDP. BSpec: 21257 Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EH - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE - Corrected mistake of using IS_ELKHARTLAKE twice and missing IS_JASPERLAKE

[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table

Patch series covers following thigns: 1. Split and differentiate between EHL and JSL platfrom 2. Update voltage swing table for eDP on JSL platform Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELK

[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table

Patch series covers following thigns: 1. Split and differentiate between EHL and JSL platfrom 2. Update voltage swing table for eDP on JSL platform Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELK

[Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

JSL has update in vswing table for eDP. BSpec: 21257 Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EH - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE - Corrected mistake of using IS_ELKHARTLAKE twice and missing IS_JASPERLAKE

[Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

Split the basic platform definition, macros, and PCI IDs to differentiate between EHL and JSL platforms. Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERL

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: reduce context clear batch size to avoid gpu hang

== Series Details == Series: drm/i915/gt: reduce context clear batch size to avoid gpu hang URL : https://patchwork.freedesktop.org/series/82377/ State : failure == Summary == Applying: drm/i915/gt: reduce context clear batch size to avoid gpu hang error: patch failed: drivers/gpu/drm/i915/gt/

[Intel-gfx] [RFC] drm/i915/gt: reduce context clear batch size to avoid gpu hang

Hello, For several months, I've been experiencing GPU hangs when starting Cinnamon on an HP Pavilion Mini 300-020 if I try to run an upstream kernel. I reported this recently in https://gitlab.freedesktop.org/drm/intel/-/issues/2413 where I have attached the requested evidence including the stat

Re: [Intel-gfx] [PATCH] drm/i915: Implement display WA #1142:kbl, cfl, cml

On Fri, Sept. 25, 2020, 11 a.m., Ville Syrjälä wrote: >On Thu, Sep 24, 2020 at 08:43:33PM +, Souza, Jose wrote: >> On Thu, 2020-09-24 at 22:48 +0300, Ville Syrjala wrote: >> > From: Ville Syrjälä < >> > ville.syrj...@linux.intel.com >> > > >> > >> > Implement display w/a #1142. This supposedly