[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove unused inline function drain_delayed_work()

== Series Details == Series: drm/i915: Remove unused inline function drain_delayed_work() URL : https://patchwork.freedesktop.org/series/79502/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18172_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove unused inline function drain_delayed_work()

== Series Details == Series: drm/i915: Remove unused inline function drain_delayed_work() URL : https://patchwork.freedesktop.org/series/79502/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18172 Summary -

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove unused inline function drain_delayed_work()

== Series Details == Series: drm/i915: Remove unused inline function drain_delayed_work() URL : https://patchwork.freedesktop.org/series/79502/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. ___

[Intel-gfx] [PATCH -next] drm/i915: Remove unused inline function drain_delayed_work()

It is not used since commit 058179e72e09 ("drm/i915/gt: Replace hangcheck by heartbeats") Signed-off-by: YueHaibing --- drivers/gpu/drm/i915/i915_utils.h | 13 - 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: remove debug message from error path

== Series Details == Series: drm/i915/display: remove debug message from error path URL : https://patchwork.freedesktop.org/series/79500/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18171_full Summa

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

== Series Details == Series: series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. URL : https://patchwork.freedesktop.org/series/79498/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18170_full

[Intel-gfx] ✓ Fi.CI.IGT: success for Add support for KeemBay DRM driver

== Series Details == Series: Add support for KeemBay DRM driver URL : https://patchwork.freedesktop.org/series/79495/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18169_full Summary --- **SUCC

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ (rev2)

== Series Details == Series: drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ (rev2) URL : https://patchwork.freedesktop.org/series/79489/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18168_full =

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

== Series Details == Series: drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock URL : https://patchwork.freedesktop.org/series/79486/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747_full -> Patchwork_18165_full ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: remove debug message from error path

== Series Details == Series: drm/i915/display: remove debug message from error path URL : https://patchwork.freedesktop.org/series/79500/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18171 Summary ---

Re: [Intel-gfx] [PATCH v5 1/2] drm/i915/display: Implement HOBL

On Tue, 2020-07-14 at 17:03 +, Souza, Jose wrote: > On Tue, 2020-07-14 at 19:43 +0300, Ville Syrjälä wrote: > > On Mon, Jul 13, 2020 at 04:53:33PM -0700, José Roberto de Souza wrote: > > > Hours Of Battery Life is a new GEN12+ power-saving feature that allows > > > supported motherboards to use

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

== Series Details == Series: series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. URL : https://patchwork.freedesktop.org/series/79498/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18170 ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

== Series Details == Series: series starting with [v2,1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. URL : https://patchwork.freedesktop.org/series/79498/ State : warning == Summary == $ dim checkpatch origin/drm-tip e9ba9f18591d dma-buf/sw_sync: Avoid recursive lock during f

[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for KeemBay DRM driver

== Series Details == Series: Add support for KeemBay DRM driver URL : https://patchwork.freedesktop.org/series/79495/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18169 Summary --- **SUCCESS** N

[Intel-gfx] [PATCH] drm/i915/display: remove debug message from error path

First check in the function is if swsci() is supported. All the error paths are easy to figure out the reason, so remove the extra debug message: it's normal not to support swsci() e.g. in dgfx. v2: Rather than special case dgfx, just remove the debug message (from Ville) Signed-off-by: Lucas

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for KeemBay DRM driver

== Series Details == Series: Add support for KeemBay DRM driver URL : https://patchwork.freedesktop.org/series/79495/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8c3c65637a2a drm/kmb: Add support for KeemBay Display -:42: WARNING:FILE_PATH_CHANGES: added, moved or deleted fil

Re: [Intel-gfx] [PATCH] drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

Hi Ville, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip v5.8-rc5 next-20200714] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ (rev2)

== Series Details == Series: drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ (rev2) URL : https://patchwork.freedesktop.org/series/79489/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18168 S

[Intel-gfx] [PATCH v2 1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

From: Bas Nieuwenhuizen Calltree: timeline_fence_release drm_sched_entity_wakeup dma_fence_signal_locked sync_timeline_signal sw_sync_ioctl Releasing the reference to the fence in the fence signal callback seems reasonable to me, so this patch avoids the locking issue in sw_sync. d386

[Intel-gfx] sw_sync callback deadlock

Take 2. dma_fence_parent() relied on fence->lock pointing into the sync_timeline which is no more, so we need a sync_pt->timeline backpointer instead. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailma

[Intel-gfx] [PATCH v2 3/3] dma-buf/selftests: Add locking selftests for sw_sync

While sw_sync is purely a debug facility for userspace to create fences and timelines it can control, nevertheless it has some tricky locking semantics of its own. In particular, Bas Nieuwenhuizen reported that we had reintroduced a deadlock if a signal callback attempted to destroy the fence. So l

[Intel-gfx] [PATCH v2 2/3] dma-buf/sw_sync: Separate signal/timeline locks

Since we decouple the sync_pt from the timeline tree upon release, in order to allow releasing the sync_pt from a signal callback we need to separate the sync_pt signaling lock from the timeline tree lock. v2: Mark up the unlocked read of the current timeline value. v3: Store a timeline pointer in

[Intel-gfx] [PATCH v2 49/59] drm/kmb: Disable ping pong mode

Disable ping pong mode otherwise video corruption results, use continuous mode and also fetch the dma addresses before disabling dma. For now, only initialize the dma and planes once and for next plane updates only update the addresses for dma. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob P

[Intel-gfx] [PATCH v2 47/59] drm/kmb: Don’t inadvertantly disable LCD controller

setbits instead of write dword for LCD_CONTROL register this was inadvertantly disabling the LCD controller. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/

[Intel-gfx] [PATCH v2 48/59] drm/kmb: SWAP R and B LCD Layer order

Set swap bit for the colors to display correctly when the format is RGB and not set when its BGR. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --gi

[Intel-gfx] [PATCH v2 25/59] drm/kmb: Display clock enable/disable

Get clock info from DT and enable it during initialization. Also changed name of the driver to "kmb,display" to match other entries in the DT. v2: fixed error in clk_disable Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 41 +++

[Intel-gfx] [PATCH v2 53/59] drm/kmb: disable the LCD layer in EOF irq handler

When disabling/enabling LCD layers, the change takes effect immediately and does not wait for EOF (end of frame). If we disable an LCD layer in kmb_plane_atomic_disable, then the frame reappears with incorrect display offsets. The solution is to mark the plane as disabled when kmb_plane_atomic_dis

[Intel-gfx] [PATCH v2 30/59] drm/kmb: call bridge init in the very beginning

of probe and return probe_defer early on, so that all the other initializations can be done after adv driver is loaded successfully. Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 74 +- drivers/gpu/drm/kmb/kmb_dsi.c | 144 ++---

[Intel-gfx] [PATCH v2 58/59] drm/kmb: Get System Clock from SCMI

System clock is different for A0 and B0 silicons, so get it directly from clk_PLL0 through SCMI calls. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 11 +++ drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 12 +

[Intel-gfx] [PATCH v2 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg.

From: Edmund Dea Note that we enable clk_msscam but do not set clk_msscam. However, we do enable and set clk_mipi_ecfg and clk_mipi_cfg. Verify that LCD and MIPI clocks are set successfully. Signed-off-by: Edmund Dea --- drivers/gpu/drm/kmb/kmb_drv.c | 112

[Intel-gfx] [PATCH v2 10/59] drm/kmb: Part 2 of Mipi Tx Initialization

Mipi TX Frame generator timing configuration Compute and set frame generator timings like hactive, front porch, back porch etc. v2: minor code review changes Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 132 +

[Intel-gfx] [PATCH v2 32/59] drm/kmb: Revert dsi_host back to a static variable

From: Edmund Dea revert dsi_host to static and instead add dsi_host_unregister. Signed-off-by: Edmund Dea Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 6 +++--- drivers/gpu/drm/kmb/kmb_drv.h | 1 - drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++-- drivers/gpu/drm/kmb/kmb_dsi.h | 1 +

[Intel-gfx] [PATCH v2 43/59] drm/kmb: Changed name of driver to kmb-drm

name change Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/Makefile | 4 ++-- drivers/gpu/drm/kmb/kmb_drv.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile index 8102bc9..527

[Intel-gfx] [PATCH v2 14/59] drm/kmb: Correct address offsets for mipi registers

Mipi HS registers start at an additional offset of 0x400 which needs to be added at the register macro definition and not at the read/write function level. v2: replaced calculations with macro to make code simpler Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb

[Intel-gfx] [PATCH v2 45/59] drm/kmb: Enable LCD interrupts

Enabled vblank interrupts for LCD. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_crtc.c | 36 +++- drivers/gpu/drm/kmb/kmb_drv.c | 41 + drivers/gpu/drm/

[Intel-gfx] [PATCH v2 57/59] drm/kmb: workaround for dma undeflow issue

Initial issue was that display remains shifted after undeflow, this fix is to recover the dma after underflow so display is clean. Major changes are reduce LCD_CLK to 200Mhz and some changes in the lcd timing params run recovery sequence at the EOF after underflow happens do nothing in plan_update(

[Intel-gfx] [PATCH v2 17/59] drm/kmb: Part7 of Mipi Tx Initialization

This completes the DPHY initialization and Tx initialization. v2: minor code review changes Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 65 ++ drivers/gpu/drm/kmb/kmb_dsi.h | 18 drivers/gpu

[Intel-gfx] [PATCH v2 27/59] drm/kmb: minor name change to match device tree

name change Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 78cb91b..4afdb9c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/dr

[Intel-gfx] [PATCH v2 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START

Myriadx code has it set to these values. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_crtc.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/km

[Intel-gfx] [PATCH v2 38/59] drm/kmb: Mipi DPHY initialization changes

Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI - Fix test_mode_send when sending normal mode test codes - Change dphy_wait_fsm to check for IDLE status rather than LOCK status for 2-lane MIPI v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Signed-off-by: Edmund Dea --- dri

[Intel-gfx] [PATCH v2 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi

Added handlers for lcd and mipi, it only finds and clears the interrupt as of now, more functionality can be added as needed. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 55 +++---

[Intel-gfx] [PATCH v2 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable

Also moved num_planes init before load, time out for dsi fixed kmb regs read/write to only pass dev_p and few other minor changes. Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 32 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 34 +--

[Intel-gfx] [PATCH v2 29/59] drm/kmb: Defer Probe

Register DSI host first and then defer probe until ADV bridge is initialized. Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 144 ++ drivers/gpu/drm/kmb/kmb_dsi.c | 46 -- drivers/gpu/drm/kmb/kmb_dsi.h | 3 +- 3 files

[Intel-gfx] [PATCH v2 51/59] drm/kmb: Write to LCD_LAYERn_CFG only once

From: Edmund Dea Video artifacts appear during playback as horizontal lines that sporadically appear every few frames. Issue was caused by writing to LCD_LAYERn_CFG register twice during plane updates. Issue is fixed by writing to LCD_LAYERn_CFG only once. Removed plane_init_status so that there

[Intel-gfx] [PATCH v2 50/59] drm/kmb: Do the layer initializations only once

The issue was video starts fine, but towards the end, the color disappers. Do the layer initializations only once, but update the DMA registers for every frame. Also changed DRM_INFO to DRM_DEBUG. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 15

[Intel-gfx] [PATCH v2 24/59] drm/kmb: Add ADV7535 bridge

Find ADV 7535 from the device tree and get the bridge driver and attach it to the DRM and the MIPI encoder. v2: check for valid encoder node Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 27 ++- drivers/gpu/drm/kmb/kmb_dsi

[Intel-gfx] [PATCH v2 15/59] drm/kmb: Part5 of Mipi Tx Intitialization

This is part1 of DPHY initialization. v2: remove kmb_write() as the function provides no benefit over calling writel() directly. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.h | 5 - drivers/gpu/drm/kmb/kmb_dsi.c | 346 ++

[Intel-gfx] [PATCH v2 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI

Enable clocks for LCD, mipi common and mipi tx0 Renamed MSS_CAM_CLK_CTRL and also fixed bug in the call to set this register. Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 8 drivers/gpu/drm/kmb/kmb_drv.h | 14 ++ drivers/gpu/drm/kmb/kmb_dsi.c |

[Intel-gfx] [PATCH v2 55/59] drm/kmb: Added useful messages in LCD ISR

Print messages for LCD DMA FIFO errors. v2: corrected spelling Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 68 +++-- drivers/gpu/drm/kmb/kmb_plane.h | 2 ++ 2 files changed, 60 insertions(+), 10 deletions(-) diff --git a/drivers/

[Intel-gfx] [PATCH v2 41/59] drm/kmb: Changes for LCD to Mipi

Also free dsi resources on driver unload. System clock frequency change for llp ratio calculation. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_crtc.c | 25 drivers/gpu/drm/kmb/kmb_drv.c | 6 +- drivers/gpu/drm/kmb/kmb_drv.h | 1 + d

[Intel-gfx] [PATCH v2 26/59] drm/kmb: rebase to newer kernel version

cleanup code Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 5 +++-- drivers/gpu/drm/kmb/kmb_drv.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 71fdb94..78cb91b 100644 --- a/driver

[Intel-gfx] [PATCH v2 23/59] drm/kmb: Additional register programming to update_plane

These changes are ported from Myriadx which has additional registers updated for planes. This change does the following reinitialize plane interrupts program Cb/Cr for planar formats set LCD_CTRL_VHSYNC_IDLE_LVL set output format and configure csc v2: code review changes v3: corrected spelling Si

[Intel-gfx] [PATCH v2 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation

From: Edmund Dea Added test pattern generator function. Enable this at compile time to test if mipi is working. mipi->hdmi section Signed-off-by: Edmund Dea Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++ drivers/gpu/drm/kmb/kmb_dsi.h | 7 +++

[Intel-gfx] [PATCH v2 11/59] drm/kmb: Use correct mmio offset from data book

Also added separate macros for lcd and mipi register accesses that use the corrected mmio offset. mmio oofset will be read from the device tree in the future. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_crtc.c | 49 ++---

[Intel-gfx] [PATCH v2 20/59] drm/kmb: Register IRQ for LCD

This code is commented out until firmware is updated to redirect LCD IRQ from MSSCPU to A53. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb

[Intel-gfx] [PATCH v2 40/59] drm/kmb: Added LCD_TEST config

To run modetest without ADV driver, enable LCD_TEST and FCC_TEST. Also made front porches 0, and some changes in the plane init. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++ drivers/gpu/drm/kmb/kmb_drv.c | 6 +-- drivers/gpu/dr

[Intel-gfx] [PATCH v2 19/59] drm/kmb: Added ioremap/iounmap for register access

Register physical addresses are remapped and the register mmio addresses for lcd,mipi and msscam are saved in drm_private. All register reads/writes are updated to get the mmio offset from this structure. We are using hardcoded values for register physical addresses and this will be modified to rea

[Intel-gfx] [PATCH v2 42/59] drm/kmb: Update LCD programming to match MIPI

Mipi input expects the memory layout to be unpacked with 8 bits per pixel in RGB (BRG) order. If the LCD is not configured properly, corrupted output results, changed dma_unpacked to 0 in mipi FG. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_crtc.c | 6

[Intel-gfx] [PATCH v2 12/59] drm/kmb: Part3 of Mipi Tx initialization

This initializes the multichannel fifo in the mipi transmitter and sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6 v2: code review changes to make code simpler Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.h | 25 +++

[Intel-gfx] [PATCH v2 52/59] drm/kmb: Cleaned up code

From: Edmund Dea to remove compiler warnings and general clean up v2: minor code review changes v3: upclassed dev_private, corrected spelling Signed-off-by: Edmund Dea --- drivers/gpu/drm/kmb/kmb_crtc.c | 46 +- drivers/gpu/drm/kmb/kmb_crtc.h |6 +- drivers/gpu/drm/kmb/kmb_drv.c |

[Intel-gfx] [PATCH v2 18/59] drm/kmb: Part8 of Mipi Tx Initialization

This initializes the interrupts for DSI. This is the final part of mipi DSI initialization. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 1 + drivers/gpu/drm/kmb/kmb_drv.h | 30 +++- drivers/gpu/drm/kmb/kmb_dsi.c | 46

[Intel-gfx] [PATCH v2 13/59] drm/kmb: Part4 of Mipi Tx Initialization

This initializes the mipi high speed transmitter CTRL and SYNC configuration registers. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 55 -- drivers/gpu/drm/kmb/kmb_regs.h | 29 +- 2 fil

[Intel-gfx] [PATCH v2 44/59] drm/kmb: Mipi settings from input timings

Removed hardcoded timings, set timings based on the current mode's input timings. Also calculate and set the lane rate based on the timings. Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++- drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++

[Intel-gfx] [PATCH v2 54/59] drm/kmb: Initialize uninitialized variables

general cleaning Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 6e38f16..2599ed2 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drive

[Intel-gfx] [PATCH v2 31/59] drm/kmb: Cleanup probe functions

From: Edmund Dea - Removed deprecated code blocks within probe functions - In kmb_remove, unregister MIPI DSI host - In kmb_probe, if kmb_load fails, then unregister MIPI DSI host - Change kmb_dsi_host_bridge_init to return error codes using ERR_PTR - Do clock intitialization earlier - Rename kmb

[Intel-gfx] [PATCH v2 16/59] drm/kmb: Part6 of Mipi Tx Initialization

This is part2 of DPHY initialization- sets up DPHY PLLs. v2: simplified mipi_tx_get_vco_params() based on review v3: added WARN_ON for invalid freq v4: fixed bug in mipi_tx_get_vco_params Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 194 +++

[Intel-gfx] [PATCH v2 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi

From: Edmund Dea Made it conditionally compiled. Signed-off-by: Edmund Dea --- drivers/gpu/drm/kmb/kmb_drv.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 90db07c..861aa97 100644 --- a/drivers/gpu/

[Intel-gfx] [PATCH v2 59/59] drm/kmb: work around for planar formats

Set the DMA Vstride and Line width for U and V planes to the same as the Y plane and not the actual pitch. Bit18 of layer config does not have any effect when U and V planes are swapped, so swap it in the driver. Signed-off-by: Anitha Chrisanthus Reviewed-by: Edmund Dea --- drivers/gpu/drm/kmb/

[Intel-gfx] [PATCH v2 39/59] drm/kmb: Fixed driver unload

unmap MSSCAM registers Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 15 +++ drivers/gpu/drm/kmb/kmb_drv.h | 1 - drivers/gpu/drm/kmb/kmb_regs.h | 2 +- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers

[Intel-gfx] [PATCH v2 46/59] drm/kmb: Enable LCD interrupts during modeset

The issue was that spurious interrupts were happening before the LCD controller was enabled and system hangs. Fix is to clear LCD interrupts and disable them before modeset and re enable them after enabling LCD controller. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Reviewed-by:

[Intel-gfx] [PATCH v2 28/59] drm/kmb: Changed MMIO size

Also added debug messages Signed-off-by: Anitha Chrisanthus --- drivers/gpu/drm/kmb/kmb_drv.c | 16 ++-- drivers/gpu/drm/kmb/kmb_regs.h | 6 +++--- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 4a

[Intel-gfx] [PATCH v2 56/59] kmb/drm: Prune unsupported modes

KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only accepts 4-lane input from mipi. With 4-lane mipi, KMB hardware can only support 1080p resolution. Therefore, limit supported mode to 1080p. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/k

[Intel-gfx] [PATCH v2 02/59] drm/kmb: Added id to kmb_plane

This is to keep track of the id of the plane as there are 4 planes in Kmb and when update() is called, we need to know which plane need to be updated so that the corresponding plane's registers can be programmed. v2: moved extern to .h, upclassed dev_private, minor changes from code review. S

[Intel-gfx] [PATCH v2 08/59] drm/kmb: Added mipi_dsi_host initialization

Added mipi DSI host initialization functions Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++ drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/kmb/

[Intel-gfx] [PATCH v2 01/59] drm/kmb: Add support for KeemBay Display

Initial check-in for basic display driver for KeemBay family of SOCs. This is not tested and does not work and also there are many TBDs in the code which will be implemented in future commits. v2: moved extern to .h, removed license text use drm_dev_init, upclassed dev_private, removed HAVE_IR

[Intel-gfx] [PATCH v2 05/59] drm/kmb: Updated kmb_plane_atomic_check

Check if format is supported and size is within limits. v2: simplified the code as per code review Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 111 +++- 1 file changed, 65 insertions(+), 46 deletions(-) di

[Intel-gfx] [PATCH v2 04/59] drm/kmb: Use biwise operators for register definitions

Did some general clean up and organization. v2: corrected spelling Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_drv.c | 3 +- drivers/gpu/drm/kmb/kmb_regs.h | 852 +++-- 2 files changed, 307 insertions(+), 548 dele

[Intel-gfx] [PATCH v2 06/59] drm/kmb: Initial check-in for Mipi DSI

Basic frame work for mipi encoder and connector. More hardware specific details will be added in the future commits. Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/Makefile | 2 +- drivers/gpu/drm/kmb/kmb_drv.c | 2 + drivers/gpu/drm/kmb/kmb_dsi.c | 94

[Intel-gfx] [PATCH v2 07/59] drm/kmb: Set OUT_FORMAT_CFG register

v2: code review changes Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 14 +- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/

[Intel-gfx] [PATCH v2 00/59] Add support for KeemBay DRM driver

This is a new DRM driver for Intel's KeemBay SOC. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This driver is tested with the KMB EVM board which is the refernce baord for Keem Bay SOC. The SOC's display pipeline is as follows +--++-++-

[Intel-gfx] [PATCH v2 03/59] drm/kmb: Set correct values in the LAYERn_CFG register

During update plane, set the layer format, bpp, fifo level, RGB order, Cb/Cr order etc. in the LAYER_CFG register. v2: Return val in set_pixel and set_bpp instead of passing in pointer, Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_plane.c | 145

[Intel-gfx] [PATCH v2 09/59] drm/kmb: Part 1 of Mipi Tx Initialization

Mipi TX frame section configuration This is the first part in the MIPI controller initialization. Compute and set the right values in MIPI TX frame section configuration registers like packet header(PH), unpacked bytes and line config. v2: added more comments to clarify assumptions v3: improved c

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. (rev2)

== Series Details == Series: series starting with [1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. (rev2) URL : https://patchwork.freedesktop.org/series/79492/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18167 ==

Re: [Intel-gfx] [PATCH v2] drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

Quoting Ville Syrjala (2020-07-14 21:19:45) > From: Ville Syrjälä > > Since g4x the CFB base only takes a 28bit offset into stolen. > Not sure if the CFB is allowed to start below that limit but > then extend beyond it. Let's assume not and just restrict the > allocation to the first 256MiB (in t

Re: [Intel-gfx] [PATCH 3/3] dma-buf/selftests: Add locking selftests for sw_sync

Awsome, thanks for adding the tests! Got to say I'm not that familiar with the self-test framework idioms, but from my perspective patches 2 and 3 are Reviewed-by: Bas Nieuwenhuizen as well. On Tue, Jul 14, 2020 at 10:06 PM Chris Wilson wrote: > > While sw_sync is purely a debug facility for

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. (rev2)

== Series Details == Series: series starting with [1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal. (rev2) URL : https://patchwork.freedesktop.org/series/79492/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4c0522b51aec dma-buf/sw_sync: Avoid recursive lock duri

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

Quoting Umesh Nerlige Ramappa (2020-07-14 21:10:02) > On Tue, Jul 14, 2020 at 12:28:15PM +0100, Chris Wilson wrote: > >Quoting Umesh Nerlige Ramappa (2020-07-14 08:22:39) > >> From: Piotr Maciejewski > >> > >> i915 used to support time based sampling mode which is good for overall > >> system moni

[Intel-gfx] [PATCH v2] drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

From: Ville Syrjälä Since g4x the CFB base only takes a 28bit offset into stolen. Not sure if the CFB is allowed to start below that limit but then extend beyond it. Let's assume not and just restrict the allocation to the first 256MiB (in the unlikely case we have more stolen than that). v2: s/

Re: [Intel-gfx] [PATCH 1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

Thanks for updating the patch. LGTM On Tue, Jul 14, 2020 at 10:07 PM Chris Wilson wrote: > > From: Bas Nieuwenhuizen > > Calltree: > timeline_fence_release > drm_sched_entity_wakeup > dma_fence_signal_locked > sync_timeline_signal > sw_sync_ioctl > > Releasing the reference to the fenc

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Avoid modeset when content protection changes

== Series Details == Series: drm/i915: Avoid modeset when content protection changes URL : https://patchwork.freedesktop.org/series/79484/ State : success == Summary == CI Bug Log - changes from CI_DRM_8745_full -> Patchwork_18164_full Summ

[Intel-gfx] [PATCH v2] dma-buf/sw_sync: Separate signal/timeline locks

Since we decouple the sync_pt from the timeline tree upon release, in order to allow releasing the sync_pt from a signal callback we need to separate the sync_pt signaling lock from the timeline tree lock. v2: Mark up the unlocked read of the current timeline value. Suggested-by: Bas Nieuwenhuize

Re: [Intel-gfx] [PATCH 1/1] drm/i915/perf: Map OA buffer to user space

On Tue, Jul 14, 2020 at 12:28:15PM +0100, Chris Wilson wrote: Quoting Umesh Nerlige Ramappa (2020-07-14 08:22:39) From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single draw ca

[Intel-gfx] [PATCH 3/3] dma-buf/selftests: Add locking selftests for sw_sync

While sw_sync is purely a debug facility for userspace to create fences and timelines it can control, nevertheless it has some tricky locking semantics of its own. In particular, Bas Nieuwenhuize reported that we had reintroduced a deadlock if a signal callback attempted to destroy the fence. So le

[Intel-gfx] [PATCH 1/3] dma-buf/sw_sync: Avoid recursive lock during fence signal.

From: Bas Nieuwenhuizen Calltree: timeline_fence_release drm_sched_entity_wakeup dma_fence_signal_locked sync_timeline_signal sw_sync_ioctl Releasing the reference to the fence in the fence signal callback seems reasonable to me, so this patch avoids the locking issue in sw_sync. d386

[Intel-gfx] [PATCH 2/3] dma-buf/sw_sync: Separate signal/timeline locks

Since we decouple the sync_pt from the timeline tree upon release, in order to allow releasing the sync_pt from a signal callback we need to separate the sync_pt signaling lock from the timeline tree lock. Suggested-by: Bas Nieuwenhuizen Signed-off-by: Chris Wilson Cc: Bas Nieuwenhuizen --- dr

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

== Series Details == Series: drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ URL : https://patchwork.freedesktop.org/series/79489/ State : warning == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h CC [

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

== Series Details == Series: drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+ URL : https://patchwork.freedesktop.org/series/79489/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18166 Summary

Re: [Intel-gfx] [PATCH] drm/i915/fbc: Limit cfb to the first 256MiB of stolen on g4x+

On Tue, Jul 14, 2020 at 08:13:03PM +0100, Chris Wilson wrote: > Quoting Ville Syrjala (2020-07-14 19:51:28) > > From: Ville Syrjälä > > > > Since g4x the CFB base only takes a 28bit offset into stolen. > > Not sure if the CFB is allowed to start below that limit but > > then extend beyond it. Let

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

== Series Details == Series: drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock URL : https://patchwork.freedesktop.org/series/79486/ State : success == Summary == CI Bug Log - changes from CI_DRM_8747 -> Patchwork_18165

Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory

On Wed, 15 Jul 2020 at 02:57, Tang, CQ wrote: > > > > > -Original Message- > > From: Auld, Matthew > > Sent: Tuesday, July 14, 2020 8:02 AM > > To: Dave Airlie > > Cc: Intel Graphics Development ; Tang, CQ > > ; Joonas Lahtinen ; > > Abdiel Janulgue ; Wilson, Chris P > > ; Balestrieri, F

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