On 10/07/2020 00:53, Chris Wilson wrote:
Perf implements a GPU delay (noa_wait) by looping until the CS timestamp
has passed a certain point. This use MI_MATH and the general purpose
registers of the user's context, and since it is clobbering the user
state it must carefully save and restore the
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/perf: Use GTT when
saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79320/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8724_full -> Patchwork_18130_full
===
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add has_master_unit_irq flag
URL : https://patchwork.freedesktop.org/series/79316/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8724_full -> Patchwork_18128_full
=
== Series Details ==
Series: drm/i915/perf: Use GTT when saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8723_full -> Patchwork_18127_full
Summ
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/perf: Use GTT when
saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79320/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8724 -> Patchwork_18130
=
== Series Details ==
Series: drm/i915/selftest: Check that GPR are restored across noa_wait
URL : https://patchwork.freedesktop.org/series/79317/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8724 -> Patchwork_18129
Summary
Perf implements a GPU delay (noa_wait) by looping until the CS timestamp
has passed a certain point. This use MI_MATH and the general purpose
registers of the user's context, and since it is clobbering the user
state it must carefully save and restore the user's data around the
noa_wait. We can ver
From: Umesh Nerlige Ramappa
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the engine general purpose
registers to and from the GT scratch. Since GT scratch is mapped to
ggtt, we need to set an additional bit in the command to use GTT.
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add has_master_unit_irq flag
URL : https://patchwork.freedesktop.org/series/79316/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8724 -> Patchwork_18128
S
== Series Details ==
Series: drm/i915/gt: Optimise aliasing-ppgtt allocations
URL : https://patchwork.freedesktop.org/series/79307/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8721_full -> Patchwork_18126_full
Summary
---
== Series Details ==
Series: series starting with [CI,1/6] drm/i915: Add has_master_unit_irq flag
URL : https://patchwork.freedesktop.org/series/79316/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e4cf5d2b2a11 drm/i915: Add has_master_unit_irq flag
343e6cd5cf65 drm/i915/dg1: a
Perf implements a GPU delay (noa_wait) by looping until the CS timestamp
has passed a certain point. This use MI_MATH and the general purpose
registers of the user's context, and since it is clobbering the user
state it must carefully save and restore the user's data around the
noa_wait. We can ver
From: Anusha Srivatsa
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i
From: Stuart Summers
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada
Cc: Daniele Spurio Ceraolo
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/
From: Abdiel Janulgue
Bspec: 33617, 33617
v2: s/intel_dg1_info/dg1_info/ as done for other platforms before and
try to shut up compiler about ununsed variable that we know
shouldn't be used (Lucas)
Cc: José Roberto de Souza
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Vanshidhar
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Reviewed-by: An
From: Abdiel Janulgue
Add the PCI ID for DG1, but keep it out of the table we use to register
the driver. At this point we can't consider the driver ready to bind to
the device since we basically miss support for everything. When more
support is merged we can enable it to work partially for examp
Quoting Lionel Landwerlin (2020-07-09 21:50:30)
> On 09/07/2020 23:46, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2020-07-09 21:42:39)
> >> On 09/07/2020 23:37, Chris Wilson wrote:
> >>> Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_ME
On Thu, Jul 9, 2020 at 1:01 PM Lucas De Marchi
wrote:
>
> On Wed, Jul 1, 2020 at 11:01 PM kernel test robot wrote:
> >
> > Hi Lucas,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on drm-intel/for-linux-next]
> > [also build test ERROR on drm-tip/drm-tip
On 09/07/2020 23:46, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-07-09 21:42:39)
On 09/07/2020 23:37, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the e
== Series Details ==
Series: drm/i915/perf: Use GTT when saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8723 -> Patchwork_18127
Summary
--
Quoting Lionel Landwerlin (2020-07-09 21:42:39)
> On 09/07/2020 23:37, Chris Wilson wrote:
> > Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> >> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> >> translation to use when saving restoring the engine general purpose
> >> reg
On 09/07/2020 23:37, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the engine general purpose
registers to and from the GT scratch. Since GT scratch is mapped to
g
On 09/07/2020 22:58, Umesh Nerlige Ramappa wrote:
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the engine general purpose
registers to and from the GT scratch. Since GT scratch is mapped to
ggtt, we need to set an additional bit in the
Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> translation to use when saving restoring the engine general purpose
> registers to and from the GT scratch. Since GT scratch is mapped to
> ggtt, we need to set an additional bi
On Thu, 2020-07-09 at 17:58 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> According to the DP spec a DPTX must support vswing/pre-emphasis
> up to and including level 2. Level 3 is optional (actually DP 1.4a
> seems to make even level 3 mandatory for HBR2/3, while leaving it
> optional fo
On Wed, Jul 1, 2020 at 11:01 PM kernel test robot wrote:
>
> Hi Lucas,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on drm-intel/for-linux-next]
> [also build test ERROR on drm-tip/drm-tip next-20200701]
> [cannot apply to v5.8-rc3]
> [If your patch is applied
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the engine general purpose
registers to and from the GT scratch. Since GT scratch is mapped to
ggtt, we need to set an additional bit in the command to use GTT.
Fixes: daed3e44396d17 ("drm/i9
== Series Details ==
Series: drm/i915/selftests: Fix compare functions provided for sorting
URL : https://patchwork.freedesktop.org/series/79304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_18125_full
===
On Thu, 2020-07-09 at 17:24 +0300, Ville Syrjälä wrote:
> On Wed, Jul 08, 2020 at 01:55:11PM -0700, José Roberto de Souza wrote:
> > Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> > supported motherboards to use a special voltage swing table for eDP
> > panels that uses le
On Thu, 2020-07-09 at 18:59 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/5] drm/i915/display: Replace
> drm_i915_private in voltage swing functions by intel_encoder (rev2)
> URL : https://patchwork.freedesktop.org/series/79265/
> State : success
>
> ==
== Series Details ==
Series: drm/i915/gt: Optimise aliasing-ppgtt allocations
URL : https://patchwork.freedesktop.org/series/79307/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8721 -> Patchwork_18126
Summary
---
**
Since the aliasing-ppgtt remains the default for gen6/gen7, it is worth
optimising the ppgtt allocation for it. In this case, we do not need to
flush the GGTT page directories entries as they are fixed during setup.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
dri
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace
drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_
== Series Details ==
Series: drm/i915: WARN if max vswing/pre-emphasis violates the DP spec
URL : https://patchwork.freedesktop.org/series/79299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_18123_full
===
== Series Details ==
Series: series starting with [1/3] drm/edid: Allow looking for ext blocks
starting from a specified index (rev2)
URL : https://patchwork.freedesktop.org/series/77699/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8708_full -> Patchwork_18081_full
== Series Details ==
Series: series starting with [1/3] drm/edid: Allow looking for ext blocks
starting from a specified index (rev2)
URL : https://patchwork.freedesktop.org/series/77699/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8708_full -> Patchwork_18081_full
== Series Details ==
Series: drm/i915/selftests: Fix compare functions provided for sorting
URL : https://patchwork.freedesktop.org/series/79304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719 -> Patchwork_18125
Summary
On Thu, 2020-07-09 at 04:12 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Implement WAs 18011464164 and 22010931296
> URL : https://patchwork.freedesktop.org/series/79268/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8717_full -> Patchwork
Quoting Sudeep Holla (2020-07-09 16:49:31)
> Both cmp_u32 and cmp_u64 are comparing the pointers instead of the value
> at those pointers. This will result in incorrect/unsorted list. Fix it
> by deferencing the pointers before comparison.
>
> Cc: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace
drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719 -> Patchwork_18124
Both cmp_u32 and cmp_u64 are comparing the pointers instead of the value
at those pointers. This will result in incorrect/unsorted list. Fix it
by deferencing the pointers before comparison.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Sudeep Holla
---
drivers/gpu/drm/i915/gt/selftest_rps
Am 09.07.20 um 14:31 schrieb Daniel Vetter:
On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote:
On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
Comes up every few years, gets so
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/display: Replace
drm_i915_private in voltage swing functions by intel_encoder (rev2)
URL : https://patchwork.freedesktop.org/series/79265/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.
Hi,
On 7/9/20 4:50 PM, Andy Shevchenko wrote:
On Wed, Jul 08, 2020 at 11:14:22PM +0200, Hans de Goede wrote:
The datasheet specifies that programming the base_unit part of the
ctrl register to 0 results in a contineous low signal.
Adjust the get_state method to reflect this by setting pwm_stat
On 06/07/2020 07:19, Chris Wilson wrote:
The prospect of locking the entire submission sequence under a wide
ww_mutex re-imposes some key restrictions, in particular that we must
not call copy_(from|to)_user underneath the mutex (as the faulthandlers
themselves may need to take the ww_mutex). T
== Series Details ==
Series: dma-fence annotations, round 3 (rev6)
URL : https://patchwork.freedesktop.org/series/79212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8718_full -> Patchwork_18122_full
Summary
---
**S
== Series Details ==
Series: drm/i915: WARN if max vswing/pre-emphasis violates the DP spec
URL : https://patchwork.freedesktop.org/series/79299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8719 -> Patchwork_18123
Summary
On Fri, 10 Jul 2020 01:37:07 +0800
Fred Gao wrote:
> Bypass the IGD initialization for Intel's dgfx devices with own expansion
> ROM and the host/LPC bridge config space are no longer accessed.
>
> Cc: Zhenyu Wang
> Cc: Xiong Zhang
> Cc: Hang Yuan
> Cc: Stuart Summers
> Signed-off-by: Lucas
Hi,
On Thu, Jul 09, 2020 at 04:40:56PM +0200, Hans de Goede wrote:
> Hi,
>
> On 7/9/20 4:14 PM, Sam Ravnborg wrote:
> > Hi Hans.
> >
> > On Wed, Jul 08, 2020 at 11:14:16PM +0200, Hans de Goede wrote:
> > > Hi All,
> > >
> > > Here is v4 of my patch series converting the i915 driver's code for
>
From: Ville Syrjälä
According to the DP spec a DPTX must support vswing/pre-emphasis
up to and including level 2. Level 3 is optional (actually DP 1.4a
seems to make even level 3 mandatory for HBR2/3, while leaving it
optional for RBR/HBR1).
WARN if out encoders' .voltage_max()/.preemph_max() re
== Series Details ==
Series: series starting with [1/3] drm/edid: Allow looking for ext blocks
starting from a specified index (rev2)
URL : https://patchwork.freedesktop.org/series/77699/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8708 -> Patchwork_18081
==
On Thu, Jul 09, 2020 at 04:33:50PM +0200, Hans de Goede wrote:
> On 7/9/20 4:21 PM, Andy Shevchenko wrote:
> > On Thu, Jul 09, 2020 at 03:23:13PM +0200, Hans de Goede wrote:
...
> > You can use clamp_val().
>
> I did not know about that, that will work nicely I will switch to clamp_val
> for the
On Wed, Jul 08, 2020 at 11:14:22PM +0200, Hans de Goede wrote:
> The datasheet specifies that programming the base_unit part of the
> ctrl register to 0 results in a contineous low signal.
>
> Adjust the get_state method to reflect this by setting pwm_state.period
> to 1 and duty_cycle to 0.
...
== Series Details ==
Series: series starting with [1/6] drm/i915: Add a couple of missing
i915_active_fini()
URL : https://patchwork.freedesktop.org/series/79297/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8718_full -> Patchwork_18121_full
=
Hi,
On 7/9/20 4:14 PM, Sam Ravnborg wrote:
Hi Hans.
On Wed, Jul 08, 2020 at 11:14:16PM +0200, Hans de Goede wrote:
Hi All,
Here is v4 of my patch series converting the i915 driver's code for
controlling the panel's backlight with an external PWM controller to
use the atomic PWM API. See below
Op 06-07-2020 om 08:19 schreef Chris Wilson:
> Sometimes we have to be very careful not to allocate underneath a mutex
> (or spinlock) and yet still want to track activity. Enter
> i915_active_acquire_for_context(). This raises the activity counter on
> i915_active prior to use and ensures that the
Hi,
On 7/9/20 4:21 PM, Andy Shevchenko wrote:
On Thu, Jul 09, 2020 at 03:23:13PM +0200, Hans de Goede wrote:
On 7/9/20 2:53 PM, Andy Shevchenko wrote:
On Wed, Jul 08, 2020 at 11:14:20PM +0200, Hans de Goede wrote:
When the user requests a high enough period ns value, then the
calculations in
On Wed, Jul 08, 2020 at 01:55:11PM -0700, José Roberto de Souza wrote:
> Hours Of Battery Life is a new GEN12+ power-saving feature that allows
> supported motherboards to use a special voltage swing table for eDP
> panels that uses less power.
>
> So here if supported by HW, OEM will set it in VB
== Series Details ==
Series: series starting with [1/3] drm/edid: Allow looking for ext blocks
starting from a specified index (rev2)
URL : https://patchwork.freedesktop.org/series/77699/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8708 -> Patchwork_18081
==
On Thu, Jul 09, 2020 at 03:23:13PM +0200, Hans de Goede wrote:
> On 7/9/20 2:53 PM, Andy Shevchenko wrote:
> > On Wed, Jul 08, 2020 at 11:14:20PM +0200, Hans de Goede wrote:
> > > When the user requests a high enough period ns value, then the
> > > calculations in pwm_lpss_prepare() might result in
Am 09.07.20 um 15:54 schrieb Steven Price:
On 09/07/2020 09:48, Christian König wrote:
Am 08.07.20 um 18:19 schrieb Daniel Vetter:
On Wed, Jul 8, 2020 at 6:11 PM Daniel Vetter wrote:
On Wed, Jul 8, 2020 at 5:05 PM Christian König
wrote:
Am 08.07.20 um 17:01 schrieb Daniel Vetter:
On Wed, Ju
Hi Hans.
On Wed, Jul 08, 2020 at 11:14:16PM +0200, Hans de Goede wrote:
> Hi All,
>
> Here is v4 of my patch series converting the i915 driver's code for
> controlling the panel's backlight with an external PWM controller to
> use the atomic PWM API. See below for the changelog.
Why is it that i
On Wed, Jul 08, 2020 at 01:55:09PM -0700, José Roberto de Souza wrote:
> This information can be get directly from intel_encoder so no need
> of those parameters.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33
On Wed, Jul 08, 2020 at 01:55:08PM -0700, José Roberto de Souza wrote:
> intel_encoder will be needed inside of vswing functions in a future
> patch, so here doing this change in all vswing functions since HSW.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
> ---
> driver
== Series Details ==
Series: series starting with [1/3] drm/edid: Allow looking for ext blocks
starting from a specified index (rev2)
URL : https://patchwork.freedesktop.org/series/77699/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8708 -> Patchwork_18081
==
On Wed, Jul 08, 2020 at 02:29:47PM -0700, José Roberto de Souza wrote:
> As today those 2 WAs have different implementation between TGL and DG1
> WA pages but checking the HSD it is clear that DG1 implementation
> should be used for both,
I couldn't really find any conclusions in any of the hsds t
Op 06-07-2020 om 08:19 schreef Chris Wilson:
> Our goal is to pull all memory reservations (next iteration
> obj->ops->get_pages()) under a ww_mutex, and to align those reservations
> with other drivers, i.e. control all such allocations with the
> reservation_ww_class. Currently, this is under the
On Thu, Jul 09, 2020 at 02:33:39PM +0200, Daniel Vetter wrote:
> Exactly matches the one in the helpers.
>
> This avoids me having to roll out dma-fence critical section
> annotations to this copy.
>
> Signed-off-by: Daniel Vetter
> Cc: David Airlie
> Cc: Gerd Hoffmann
> Cc: virtualizat...@lis
On Thu, Jul 09, 2020 at 12:19:07AM +, Souza, Jose wrote:
> On Wed, 2020-07-08 at 16:12 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > GLK supposedly does not need WaFbcTurnOffFbcWatermark,
> > so let's not apply it.
>
> WA 0562 from BSpec 21664 says it applies to all GEN9 but it
On 09/07/2020 09:48, Christian König wrote:
Am 08.07.20 um 18:19 schrieb Daniel Vetter:
On Wed, Jul 8, 2020 at 6:11 PM Daniel Vetter wrote:
On Wed, Jul 8, 2020 at 5:05 PM Christian König
wrote:
Am 08.07.20 um 17:01 schrieb Daniel Vetter:
On Wed, Jul 8, 2020 at 4:37 PM Christian König
wrote
Hi,
On 7/9/20 3:36 PM, Andy Shevchenko wrote:
On Wed, Jul 08, 2020 at 11:14:21PM +0200, Hans de Goede wrote:
Before this commit a suspend + resume of the LPSS PWM controller
would result in the controller being reset to its defaults of
output-freq = clock/256, duty-cycle=100%, until someone cha
On Wed, Jul 08, 2020 at 11:14:21PM +0200, Hans de Goede wrote:
> Before this commit a suspend + resume of the LPSS PWM controller
> would result in the controller being reset to its defaults of
> output-freq = clock/256, duty-cycle=100%, until someone changes
> to the output-freq and/or duty-cycle
== Series Details ==
Series: dma-fence annotations, round 3 (rev6)
URL : https://patchwork.freedesktop.org/series/79212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8718 -> Patchwork_18122
Summary
---
**SUCCESS**
Hi,
On 7/9/20 2:53 PM, Andy Shevchenko wrote:
On Wed, Jul 08, 2020 at 11:14:20PM +0200, Hans de Goede wrote:
When the user requests a high enough period ns value, then the
calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
But according to the data-sheet the way the PWM
On 2020-07-02 at 20:07:36 +0530, Anshuman Gupta wrote:
> On 2020-06-30 at 12:48:34 -0400, Sean Paul wrote:
> > On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta
> > wrote:
> > >
> > > On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote:
> > > Hi Sean,
> > > I am new to DP MST stuff, I am looking to DP
== Series Details ==
Series: dma-fence annotations, round 3 (rev6)
URL : https://patchwork.freedesktop.org/series/79212/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/amd/amdgpu/
== Series Details ==
Series: dma-fence annotations, round 3 (rev6)
URL : https://patchwork.freedesktop.org/series/79212/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6993be4b66a4 dma-fence: basic lockdep annotations
-:23: ERROR:GIT_COMMIT_ID: Please use git commit description
On Wed, Jul 08, 2020 at 11:14:20PM +0200, Hans de Goede wrote:
> When the user requests a high enough period ns value, then the
> calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
>
> But according to the data-sheet the way the PWM controller works is that
> each input clo
On Thu, Jul 09, 2020 at 02:33:39PM +0200, Daniel Vetter wrote:
> Exactly matches the one in the helpers.
>
> This avoids me having to roll out dma-fence critical section
> annotations to this copy.
>
> Signed-off-by: Daniel Vetter
> Cc: David Airlie
> Cc: Gerd Hoffmann
> Cc: virtualizat...@lis
Hi,
On 7/8/20 11:25 PM, Alex Deucher wrote:
On Wed, Jul 8, 2020 at 12:43 PM Hans de Goede wrote:
Hi All,
Here is the privacy-screen related code which we discussed a while ago.
This series consists of a number of different parts:
1. A new version of Rajat's privacy-screen connector properti
On 2020-07-09 at 16:07:12 +0530, Ramalingam C wrote:
> On 2020-06-23 at 11:59:07 -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Now that all the groundwork has been laid, we can turn on HDCP 1.4 over
> > MST. Everything except for toggling the HDCP signalling and HDCP 2.2
> > support is the
Exactly matches the one in the helpers.
This avoids me having to roll out dma-fence critical section
annotations to this copy.
Signed-off-by: Daniel Vetter
Cc: David Airlie
Cc: Gerd Hoffmann
Cc: virtualizat...@lists.linux-foundation.org
---
drivers/gpu/drm/virtio/virtgpu_display.c | 20 --
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads or workloads where userspace fencing is allowe
On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote:
>
> On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
> > On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
> > > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> > > > Comes up every few years, gets somewhat tedious to discuss, l
== Series Details ==
Series: vfio/pci: Refine Intel IGD OpRegion support
URL : https://patchwork.freedesktop.org/series/79293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8718_full -> Patchwork_18120_full
Summary
---
On Thu, Jul 09, 2020 at 02:47:10PM +0300, Imre Deak wrote:
> On Wed, Jan 08, 2020 at 08:12:40PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > With SDVO the pipe config pixel_multiplier only concerns itself with the
> > data on the SDVO bus. Any HDMI specific pixel repeat must be han
== Series Details ==
Series: series starting with [1/6] drm/i915: Add a couple of missing
i915_active_fini()
URL : https://patchwork.freedesktop.org/series/79297/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8718 -> Patchwork_18121
===
On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote:
> On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote:
> > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote:
> > > Comes up every few years, gets somewhat tedious to discuss, let's
> > > write this down once and for all.
> >
> > Thanks fo
Quoting Tvrtko Ursulin (2020-07-09 12:59:51)
>
> On 09/07/2020 12:07, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-07-09 12:01:29)
> >>
> >> On 08/07/2020 16:36, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2020-07-08 15:24:20)
> And what is the effective behaviour you get with N
On Thu, Jul 09, 2020 at 02:01:19PM +0300, Imre Deak wrote:
> On Wed, Jan 08, 2020 at 08:12:39PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The code assumes that DRM_MODE_FLAG_DBLCLK means that we enable the
> > pixel repeat feature. That only works with HDMI since it requires
> >
On 09/07/2020 12:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-09 12:01:29)
On 08/07/2020 16:36, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-07-08 15:24:20)
And what is the effective behaviour you get with N contexts - emit N
concurrent operations and for N + 1 block in execb
== Series Details ==
Series: series starting with [1/6] drm/i915: Add a couple of missing
i915_active_fini()
URL : https://patchwork.freedesktop.org/series/79297/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b4522cf919dd drm/i915: Add a couple of missing i915_active_fini()
36
Am 07.07.20 um 22:12 schrieb Daniel Vetter:
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads
On Wed, Jan 08, 2020 at 08:12:42PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> .get_modes() is supposed to return the number of modes added to the
> probed_modes list (not that anyone actually checks for anything
> except zero vs. not zero). Let's do that.
>
> Signed-off-by: Ville Syrj
On Wed, Jan 08, 2020 at 08:12:41PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> .get_modes() is supposed to return the number of modes added to the
> probed_modes list (not that anyone actually checks for anything
> except zero vs. not zero). Let's do that. Also switch over to using
> in
On Wed, Jan 08, 2020 at 08:12:40PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With SDVO the pipe config pixel_multiplier only concerns itself with the
> data on the SDVO bus. Any HDMI specific pixel repeat must be handled by
> the SDVO device itself. To do that simply configure the SDV
Whenever an i915_active idles, we prune its tree of old fence slots to
prevent a gradual leak should it be used to track many, many timelines.
The downside is that we then have to frequently reallocate the rbtree.
A compromise is that we keep the most recently used fence slot, and
reuse that for th
If no active callback is defined for i915_active, we do not need to
serialise its enabling with the mutex. We still do only want to call the
debug activate once, and must still serialise with a concurrent retire.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 25 +++
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