On Tue, 21 Apr 2020, Guru Das Srinagesh wrote:
> [REQUEST]
>
> Would it be possible for the patches that have already received Acked-by's in
> this series to be accepted and applied to the tree? I lost an Acked-by (in
> intel-panel.c) because it had a merge conflict with a new change that came in
On Thu, 23 Apr 2020, Guru Das Srinagesh wrote:
> On Thu, Apr 23, 2020 at 12:48:57PM +0100, Lee Jones wrote:
> > What's the merge plan for this set?
>
> I'm not sure what you mean. My assumption is that first all the patches
> need to get an Acked-by and only then will the series get applied by
>
On Thu, 23 Apr 2020, Guru Das Srinagesh wrote:
> On Thu, Apr 23, 2020 at 12:48:57PM +0100, Lee Jones wrote:
> > What's the merge plan for this set?
>
> I'm not sure what you mean. My assumption is that first all the patches
> need to get an Acked-by and only then will the series get applied by
>
On Tue, 21 Apr 2020, Guru Das Srinagesh wrote:
> Since the PWM framework is switching struct pwm_state.duty_cycle's
> datatype to u64, prepare for this transition by using DIV_ROUND_UP_ULL
> to handle a 64-bit dividend.
>
> To: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: David Airlie
> Cc: Daniel V
== Series Details ==
Series: drm/i915: Add engine scratch register to live_lrc_fixed
URL : https://patchwork.freedesktop.org/series/76415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8357_full -> Patchwork_17450_full
Summ
== Series Details ==
Series: drm/i915: Add engine scratch register to live_lrc_fixed
URL : https://patchwork.freedesktop.org/series/76415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8357 -> Patchwork_17450
Summary
--
From: Brian Starkey
Add a test which makes commits using the writeback connector, and
checks the output buffer hash to make sure it is/isn't written as
appropriate.
Changes since V7 (Maxime Ripard):
* Make fb_fill cross-platform
Changes since v6 (Simon Ser):
* Add a descriptive error message if
From: Brian Starkey
Add tests for the WRITEBACK_PIXEL_FORMATS, WRITEBACK_OUT_FENCE_PTR and
WRITEBACK_FB_ID properties on writeback connectors, ensuring their
behaviour is correct.
Changes since V7 (Maxime Ripard and Petri Latvala):
* Utilizes `to_user_pointer` to avoid cast compilation error on
From: Brian Starkey
To use writeback buffers as a CRC source, we need to be able to hash
them. Implement a simple FVA-1a hashing routine for this purpose.
Doing a bytewise hash on the framebuffer directly can be very slow if
the memory is noncached. By making a copy of each line in the FB first
From: Brian Starkey
Add support in igt_kms for writeback connectors, with the ability
to attach framebuffers.
v5: Rebase and add DRM_CLIENT_CAP_WRITEBACK_CONNECTORS before
drmModeGetResources()
Signed-off-by: Brian Starkey
[rebased and updated to the latest igt style]
Signed-off-by: Liviu Duda
Hi,
A couple of months ago, I updated and re-submitted a patchset made by
Brian Starkey and Liviu Dudau for adding a writeback connectors test to
IGT. It is important to highlight that DRM already have writeback
connectors support, which is a way to expose in DRM the hardware
functionality from di
From: Mika Kuoppala
General purpose registers are per engine and
in a fixed location. Add to live_lrc_fixed.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 12
drivers/gpu/drm/i915/gt/selftest_lrc.c
== Series Details ==
Series: drm/i915/selftests: Add context batchbuffers registers to
live_lrc_fixed (rev4)
URL : https://patchwork.freedesktop.org/series/76407/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17449
===
From: Mika Kuoppala
Add per ctx bb and indirect ctx bb register locations to live_lrc_fixed
for verification.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 128 ++--
drivers/gpu/drm/i915/gt
== Series Details ==
Series: drm/i915/selftests: Add context batchbuffers registers to
live_lrc_fixed (rev3)
URL : https://patchwork.freedesktop.org/series/76407/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17448
===
== Series Details ==
Series: drm/edid: Fix off-by-one in DispID DTD pixel clock
URL : https://patchwork.freedesktop.org/series/76399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352_full -> Patchwork_17442_full
Summary
-
On Thu, Apr 23, 2020 at 12:48:57PM +0100, Lee Jones wrote:
> What's the merge plan for this set?
I'm not sure what you mean. My assumption is that first all the patches
need to get an Acked-by and only then will the series get applied by
Thierry... Could Thierry or Uwe weigh in on this point pleas
From: Mika Kuoppala
Add per ctx bb and indirect ctx bb register locations to live_lrc_fixed
for verification.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 128 ++--
drivers/gpu/drm/i915/gt
== Series Details ==
Series: drm/edid: Fix off-by-one in DispID DTD pixel clock
URL : https://patchwork.freedesktop.org/series/76399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17442
Summary
---
== Series Details ==
Series: drm/i915/selftests: Add context batchbuffers registers to
live_lrc_fixed (rev2)
URL : https://patchwork.freedesktop.org/series/76407/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17447
===
== Series Details ==
Series: drm/i915/icl+: Prevent using non-TypeC AUX channels on TypeC ports
URL : https://patchwork.freedesktop.org/series/76405/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8354_full -> Patchwork_17444_full
===
Hi Chris,
> > > +static int s_many(void *arg)
> > > +{
> > > + struct perf_series *ps = arg;
> >
> > why do we need to go through void... all functions are taking a
> > perf_series structure.
>
> The kthread API defines the function pointer as int (*fn)(void *arg);
In the parallel tes, not
From: Mika Kuoppala
Add per ctx bb and indirect ctx bb register locations to live_lrc_fixed
for verification.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 110
drivers/gpu/drm/i915/gt
== Series Details ==
Series: drm/i915/selftests: Add context batchbuffers registers to live_lrc_fixed
URL : https://patchwork.freedesktop.org/series/76407/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17446
===
== Series Details ==
Series: series starting with [1/6] drm/i915: Add engine scratch register to
live_lrc_fixed
URL : https://patchwork.freedesktop.org/series/76406/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17445
== Series Details ==
Series: series starting with [1/6] drm/i915: Add engine scratch register to
live_lrc_fixed
URL : https://patchwork.freedesktop.org/series/76406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56bad9b0154e drm/i915: Add engine scratch register to live_lrc_fi
== Series Details ==
Series: drm/i915/icl+: Prevent using non-TypeC AUX channels on TypeC ports
URL : https://patchwork.freedesktop.org/series/76405/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8354 -> Patchwork_17444
Sum
Hi Dave and Daniel,
Here goes drm-intel-fixes-2020-04-23:
- Tigerlake Workaround - disabling media recompression (Matt)
- Fix RPS interrupts for right GPU frequency (Chris)
- HDCP fix prime check (Oliver)
- Tigerlake Thunderbolt power well fix (Matt)
- Tigerlake DP link training fixes (Jose)
- Do
On Thu, Apr 23, 2020 at 06:38:46PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 22, 2020 at 12:20:06PM -0700, Manasi Navare wrote:
> > On Wed, Apr 22, 2020 at 07:19:14PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Make things a bit more abstract by replacing the pch_pfit.pos/si
On Thu, Apr 23, 2020 at 06:17:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DispID DTD pixel clock is documented as:
> "00 00 00 h → FF FF FF h | Pixel clock ÷ 10,000 0.01 → 167,772.16 Mega Pixels
> per Sec"
> Which seems to imply that we to add one to the raw value.
>
> Realit
Add per ctx bb and indirect ctx bb to a live_lrc_fixed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 14 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 +++
3 files changed, 30 ins
From: Mika Kuoppala
Add per ctx bb and indirect ctx bb register locations to live_lrc_fixed
for verification.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 110
drivers/gpu/drm/i915/gt
Indirect ctx batchbuffers are a hw feature of which
batch can be run, by hardware, during context restoration stage.
Driver can setup a batchbuffer and also an offset into the
context image. When context image is marshalled from
memory to registers, and when the offset from the start of
context reg
More often than not, we need a byte offset into lrc
register state from the start of the hw state. Make it so.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 3 +--
drivers/gpu/drm/i915/gt/intel_lrc.c | 8
drivers/gp
General purpose registers are per engine and
in a fixed location. Add to live_lrc_fixed.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel
Restoration of a previous timestamp can collide
with updating the timestamp, causing a value corruption.
Combat this issue by using indirect ctx bb to
modify the context image during restoring process.
We can preload value into scratch register. From which
we then do the actual write with LRR. LR
Use indirect ctx bb to load cmd buffer control value
from context image to avoid corruption.
v2: add to lrc layout (Chris)
v3: end to a cacheline (Chris)
Testcase: igt/i915_selftest/gt_lrc
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 99 -
d
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8353_full -> Patchwork_17443_full
Summary
Using an AUX channel which by default belongs to a non-TypeC PHY won't
work on a TypeC PHY, since - as a side-effect besides providing an AUX
channel - the AUX channel power well affects power manangement specific
to the TypeC subsystem. Using a TypeC AUX channel on a non-TypeC PHY
would probably a
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8353 -> Patchwork_17443
Summary
---
== Series Details ==
Series: drm/i915: Show per-engine default property values in sysfs
URL : https://patchwork.freedesktop.org/series/76396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352_full -> Patchwork_17441_full
S
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev5)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0b8abccda505 drm/i915/selftests: Verify context isolation
-:345: WARNING:LINE_SPACING: Missing a
On 23/04/2020 16:17, Chris Wilson wrote:
Quoting Chris Wilson (2020-04-23 16:16:09)
Quoting Tvrtko Ursulin (2020-04-23 15:47:58)
On 23/04/2020 09:59, Chris Wilson wrote:
When recording the default context state, we submit an ordinary context
and then steal the context image for our defaults
Hi,
Here is this week (and the first) drm-misc-fixes PR.
Maxime
drm-misc-fixes-2020-04-23:
A few resources-related fixes (tidss, dp_mst, scheduler), probe fixes and
DT bindings adjustments.
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12
On 4/21/20 5:21 PM, Jason Gunthorpe wrote:
From: Jason Gunthorpe
The API is a bit complicated for the uses we actually have, and
disucssions for simplifying have come up a number of times.
This small series removes the customizable pfn format and simplifies the
return code of hmm_range_fault
On Wed, Apr 22, 2020 at 09:49:34AM +0100, Daniel Thompson wrote:
> On Tue, Apr 21, 2020 at 07:57:12PM -0700, Guru Das Srinagesh wrote:
> > [REQUEST]
> >
> > Would it be possible for the patches that have already received Acked-by's
> > in
> > this series to be accepted and applied to the tree? I
== Series Details ==
Series: drm/edid: Fix off-by-one in DispID DTD pixel clock
URL : https://patchwork.freedesktop.org/series/76399/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17442
Summary
---
No unprivileged context should ever be allowed to modify logical state
that is visible to another; there should be no backchannels available or
control leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should o
On Wed, Apr 22, 2020 at 12:20:06PM -0700, Manasi Navare wrote:
> On Wed, Apr 22, 2020 at 07:19:14PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make things a bit more abstract by replacing the pch_pfit.pos/size
> > raw register values with a drm_rect. Makes it slighly more conveni
== Series Details ==
Series: drm/edid: Fix off-by-one in DispID DTD pixel clock
URL : https://patchwork.freedesktop.org/series/76399/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72984b49da56 drm/edid: Fix off-by-one in DispID DTD pixel clock
-:10: WARNING:COMMIT_LOG_LONG_LINE
== Series Details ==
Series: drm/i915: Show per-engine default property values in sysfs
URL : https://patchwork.freedesktop.org/series/76396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17441
Summary
---
From: Ville Syrjälä
The DispID DTD pixel clock is documented as:
"00 00 00 h → FF FF FF h | Pixel clock ÷ 10,000 0.01 → 167,772.16 Mega Pixels
per Sec"
Which seems to imply that we to add one to the raw value.
Reality seems to agree as there are tiled displays in the wild
which currently show a
Quoting Chris Wilson (2020-04-23 16:16:09)
> Quoting Tvrtko Ursulin (2020-04-23 15:47:58)
> >
> > On 23/04/2020 09:59, Chris Wilson wrote:
> > > When recording the default context state, we submit an ordinary context
> > > and then steal the context image for our defaults. To be able to steal
> >
Quoting Tvrtko Ursulin (2020-04-23 15:47:58)
>
> On 23/04/2020 09:59, Chris Wilson wrote:
> > When recording the default context state, we submit an ordinary context
> > and then steal the context image for our defaults. To be able to steal
> > the state, we must have total ownership of the contex
Quoting Tvrtko Ursulin (2020-04-23 15:53:44)
>
> On 23/04/2020 12:58, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_request.c
> > b/drivers/gpu/drm/i915/i915_request.c
> > index 22635bbabf06..e9fd20242438 100644
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/
On 23/04/2020 12:53, Chris Wilson wrote:
During the virtual engine's submission tasklet, we take the request and
insert into the submission queue on each of our siblings. This seems
quite simply, and so no problems with ordering. However, the sibling
execlists' submission tasklets may run concu
Quoting Andi Shyti (2020-04-23 15:18:47)
> Hi Chris,
>
> > > > +static int s_many(void *arg)
> > > > +{
> > > > + struct perf_series *ps = arg;
> > >
> > > why do we need to go through void... all functions are taking a
> > > perf_series structure.
> >
> > The kthread API defines the functio
== Series Details ==
Series: drm/i915: Show per-engine default property values in sysfs
URL : https://patchwork.freedesktop.org/series/76396/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6074c77973f3 drm/i915: Show per-engine default property values in sysfs
-:124: CHECK:PAREN
On 23/04/2020 12:58, Chris Wilson wrote:
As the i915_request.engine may be updated by a virtual engine to either
point to the virtual engine or the real physical engine on submission,
we have to be wary that the engine pointer may change.
[ 213.317076] BUG: KCSAN: data-race in execlists_deque
On 23/04/2020 09:59, Chris Wilson wrote:
When recording the default context state, we submit an ordinary context
and then steal the context image for our defaults. To be able to steal
the state, we must have total ownership of the context. During CI we
want to make this error extremely obvious,
== Series Details ==
Series: drm/i915/gt: Carefully order virtual_submission_tasklet
URL : https://patchwork.freedesktop.org/series/76391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352_full -> Patchwork_17438_full
Summ
On 23/04/2020 09:59, Chris Wilson wrote:
intel_gt_wait_for_idle() tries to wait until all the outstanding requests
are retired and the GPU is idle. As a side effect of retiring requests,
we may submit more work to flush any pm barriers, and so the
wait-for-idle tries to flush the background pm
Hi Mika,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.7-rc2 next-20200423]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also
Why?
/sys/class/drm/card0/engine/rcs0/
├── capabilities
├── class
├── .defaults
│ ├── heartbeat_interval_ms
│ ├── max_busywait_duration_ns
│ ├── preempt_timeout_ms
│ ├── stop_timeout_ms
│ └── timeslice_duration_ms
├── heartbeat_interval_ms
├── instance
├── known_capabilities
├── max_busy
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev4)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17440
Summary
---
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev4)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bfe16faeae8a drm/i915/selftests: Verify context isolation
-:342: WARNING:LINE_SPACING: Missing a
== Series Details ==
Series: drm/i915: Mark up racy read of rq->engine
URL : https://patchwork.freedesktop.org/series/76392/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17439
Summary
---
**FAILURE
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Check carefully for an idle
engine in wait-for-idle
URL : https://patchwork.freedesktop.org/series/76384/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8351_full -> Patchwork_17436_full
==
== Series Details ==
Series: drm/i915/gt: Carefully order virtual_submission_tasklet
URL : https://patchwork.freedesktop.org/series/76391/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8352 -> Patchwork_17438
Summary
--
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20200423]
[cannot apply to v5.7-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system
No unprivileged context should ever be allowed to modify logical state
that is visible to another; there should be no backchannels available or
control leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should o
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8351 -> Patchwork_17437
Summary
---
On 04/22, Maxime Ripard wrote:
> Hi!
>
> On Tue, Apr 21, 2020 at 05:07:05PM -0400, Rodrigo Siqueira wrote:
> > On 04/15, Maxime Ripard wrote:
> > > On Mon, Oct 21, 2019 at 10:00:39PM -0300, Brian Starkey wrote:
> > > > Add a test which makes commits using the writeback connector, and
> > > > check
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8351 -> Patchwork_17437
Summary
---
As the i915_request.engine may be updated by a virtual engine to either
point to the virtual engine or the real physical engine on submission,
we have to be wary that the engine pointer may change.
[ 213.317076] BUG: KCSAN: data-race in execlists_dequeue [i915] /
i915_request_wait [i915]
[ 213.
During the virtual engine's submission tasklet, we take the request and
insert into the submission queue on each of our siblings. This seems
quite simply, and so no problems with ordering. However, the sibling
execlists' submission tasklets may run concurrently with the virtual
engine's tasklet, su
On Tue, 21 Apr 2020, Guru Das Srinagesh wrote:
> [REQUEST]
>
> Would it be possible for the patches that have already received Acked-by's in
> this series to be accepted and applied to the tree? I lost an Acked-by (in
> intel-panel.c) because it had a merge conflict with a new change that came in
On Wed, Apr 22, 2020 at 05:55:58PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/icl: Fix timeout handling during TypeC AUX power well
> enabling
> URL : https://patchwork.freedesktop.org/series/76336/
> State : success
Pushed, thanks for the review.
>
> == Summary ==
>
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8350_full -> Patchwork_17434_full
Summary
---
**SUCCESS
On Wed, Apr 22, 2020 at 12:40:02PM -0700, José Roberto de Souza wrote:
> It was missing the step 7.b - "If not type-C static connection,
> configure PORT_CL_DW10 Static Power Down to power up all lanes of the
> DDI".
>
> BSpec: 53339
> BSpec: 49191
> Signed-off-by: José Roberto de Souza
> ---
>
== Series Details ==
Series: drm/i915/selftests: Verify context isolation (rev3)
URL : https://patchwork.freedesktop.org/series/76339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7d2826951e5a drm/i915/selftests: Verify context isolation
-:319: WARNING:LINE_SPACING: Missing a
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Check carefully for an idle
engine in wait-for-idle
URL : https://patchwork.freedesktop.org/series/76384/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8351 -> Patchwork_17436
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-04-21 14:16:31)
>> Indirect ctx batchbuffers are a hw feature of which
>> batch can be run, by hardware, during context restoration stage.
>> Driver can setup a batchbuffer and also an offset into the
>> context image. When context image is marsh
On Wed, Apr 22, 2020 at 12:40:01PM -0700, José Roberto de Souza wrote:
> Getting it only once also removing intel_hdmi that is used only once
> and can be easily accessed by dig_port->hdmi.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/in
== Series Details ==
Series: pci/msi: Stop warning for MSI enabling failure
URL : https://patchwork.freedesktop.org/series/76382/
State : failure
== Summary ==
Applying: pci/msi: Stop warning for MSI enabling failure
Using index info to reconstruct a base tree...
M drivers/pci/msi.c
Fall
No unprivileged context should ever be allowed to modify state that is
visible to another; there should be no backchannels available or control
leakage for malicious actors.
This test tries to write to a set of random registers using
non-privileged instructions (ala userspace). It should only be a
Quoting Li Zhijian (2020-04-23 10:38:38)
> Hi guys
>
> 0Day noticed that dumb_buffer@clear_create triggers OOM since commit:
> 0b0eaa353 ("tests/dumb_buffer: Try to compute the largest possible dumb
> buffer")
So VM_FAULT_OOM -> pagefault_out_of_memory()
But a failed allocation for 2G out of
Hi guys
0Day noticed that dumb_buffer@clear_create triggers OOM since commit:
0b0eaa353 ("tests/dumb_buffer: Try to compute the largest possible dumb
buffer")
our platform is
- CPU: Intel(R) Xeon(R) CPU D-1541 @ 2.10GHz
- memory: 48G
- kernel: v5.5, v5.6, v5.7-rc2
i tried to add some debug
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8350 -> Patchwork_17434
Summary
---
**SUCCESS**
No r
On Wed, Apr 22, 2020 at 04:37:55PM -0700, Guru Das Srinagesh wrote:
> On Wed, Apr 22, 2020 at 09:49:34AM +0100, Daniel Thompson wrote:
> > On Tue, Apr 21, 2020 at 07:57:12PM -0700, Guru Das Srinagesh wrote:
> > > [REQUEST]
> > >
> > > Would it be possible for the patches that have already received
== Series Details ==
Series: SAGV support for Gen12+ (rev27)
URL : https://patchwork.freedesktop.org/series/75129/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f963df93cc7d drm/i915: Introduce skl_plane_wm_level accessor.
75ab029a2591 drm/i915: Use bw state for per crtc SAGV e
intel_gt_wait_for_idle() tries to wait until all the outstanding requests
are retired and the GPU is idle. As a side effect of retiring requests,
we may submit more work to flush any pm barriers, and so the
wait-for-idle tries to flush the background pm work and catch the new
requests. However, if
When recording the default context state, we submit an ordinary context
and then steal the context image for our defaults. To be able to steal
the state, we must have total ownership of the context. During CI we
want to make this error extremely obvious, as otherwise we will fail the
user's module
If the MSI is already enabled, trying to enable it again results in an
-EINVAL and on the first attempt a WARN. That WARN causes our CI to
abort the run [on each first attempt to suspend]:
<4> [463.142025] WARNING: CPU: 0 PID: 2225 at drivers/pci/msi.c:1074
__pci_enable_msi_range+0x3cb/0x420
<4>
== Series Details ==
Series: drm/i915/gt: Check carefully for an idle engine in wait-for-idle
URL : https://patchwork.freedesktop.org/series/76362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8350_full -> Patchwork_17433_full
=
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä
Signed-off-by
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of ato
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