U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some PCI
IDs were removed in BSpec for CML. This patch is used
to eliminate the unsed ID.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
in
On Tue, 10 Dec 2019, Kirti Wankhede wrote:
> On 12/9/2019 7:31 PM, Jani Nikula wrote:
>> On Tue, 03 Dec 2019, Jani Nikula wrote:
>>> Now that the fbops member of struct fb_info is const, we can start
>>> making the ops const as well.
>>>
>>> v2: fix typo (Christophe de Dinechin)
>>>
>>> Cc: K
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7523_full -> Patchwork_15661_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/gt: Detect if we miss WaIdleLiteRestore (rev3)
URL : https://patchwork.freedesktop.org/series/70605/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7521_full -> Patchwork_15653_full
Summ
On Thu, 2019-11-07 at 16:24 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For the sake of symmetry with the crtc stuff let's add
> a helper to reset the plane state to sane default values.
> For the moment this only gets caller from the plane init.
>
Reviewed-by: José Roberto de Souza
On Thu, 2019-11-07 at 16:24 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have a few places where we want to reset a crtc state to its
> default values. Let's add a helper for that. We'll need the new
> __drm_atomic_helper_crtc_state_reset() helper for this to allow
> us to just reset
On Mon, 2019-12-09 at 21:43 +0200, Ville Syrjälä wrote:
> On Mon, Dec 09, 2019 at 06:45:43PM +, Souza, Jose wrote:
> > On Mon, 2019-12-09 at 18:40 +0200, Ville Syrjälä wrote:
> > > On Fri, Dec 06, 2019 at 05:18:29PM -0800, José Roberto de Souza
> > > wrote:
> > > > On TGL the blending of all th
On Thu, 2019-11-07 at 16:24 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We already have alloc/free helpers for planes, add the same for
> crtcs. The main benefit is we get to move all the annoying state
> initialization out of the main crtc_init() flow.
>
Reviewed-by: José Roberto de
On Thu, 2019-11-07 at 16:24 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's get rid of the redundant intel_ prefix on our variables.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32 ++--
> -
Quoting Andi Shyti (2019-12-09 22:35:55)
> From: Andi Shyti
>
> Add two helpers that for reading the actual GT's frequency. The
> two helpers are:
>
> - intel_cagf_read: reads the frequency and returns it not
>normalized
>
> - intel_cagf_freq_read: provides the frequency in Hz.
>
> Use t
> > +int intel_gt_pm_debugfs_register(struct intel_gt *gt)
> > +{
> > + struct drm_minor *minor = gt->i915->drm.primary;
> > +
> > + return drm_debugfs_create_files(i915_gt_pm_debugfs_list,
> > + ARRAY_SIZE(i915_gt_pm_debugfs_list),
> > +
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7523 -> Patchwork_15661
Summary
---
**SUCCESS**
No regress
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
112b55276b89 drm/i915/rps: Add frequency translation helpers
77e7a15ebe7b drm/i915/gt: Move power management debugfs files
== Series Details ==
Series: linux-next: build failure after merge of the drm-intel tree (rev3)
URL : https://patchwork.freedesktop.org/series/42839/
State : failure
== Summary ==
Applying: linux-next: build failure after merge of the drm-intel tree
Using index info to reconstruct a base tree.
== Series Details ==
Series: drm/i915: Implement pps w/a #1124 for bxt+
URL : https://patchwork.freedesktop.org/series/70655/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7523 -> Patchwork_15659
Summary
---
**FAILUR
From: Andi Shyti
Hi,
this two patches are few debugfs improvements. The first adds
some helpers for reading the GT frequency, while the second patch
moves all the power management debufs functions into gt/
Thanks,
Andi
Andi Shyti (2):
drm/i915/rps: Add frequency translation helpers
drm/i9
From: Andi Shyti
rc6, rps and llc debugfs files are gt related, move them into the
gt directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 593 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debu
Quoting Andi Shyti (2019-12-09 22:35:56)
> +int intel_gt_pm_debugfs_register(struct intel_gt *gt)
> +{
> + struct drm_minor *minor = gt->i915->drm.primary;
> +
> + return drm_debugfs_create_files(i915_gt_pm_debugfs_list,
> + ARRAY_SIZE(i915_gt_pm_de
Hi all,
[Just adding Dave Airlie to the cc list]
On Tue, 10 Dec 2019 09:39:57 +1100 Stephen Rothwell
wrote:
>
> After merging the drm-intel tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> In file included from include/linux/spinlock_types.h:18,
> f
Hi all,
After merging the drm-intel tree, today's linux-next build (x86_64
allmodconfig) failed like this:
In file included from include/linux/spinlock_types.h:18,
from include/linux/mutex.h:16,
from include/linux/kernfs.h:12,
from include/linux/
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_cagf_read: reads the frequency and returns it not
normalized
- intel_cagf_freq_read: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-off-by: Andi Shy
Thanks for the reviews, pushed.
Daniele
On 12/9/19 11:32 AM, Daniele Ceraolo Spurio wrote:
On 12/6/19 1:05 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/guc: Drop leftover
preemption code
URL : https://patchwork.freedesktop.org/series/70525/
St
== Series Details ==
Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev3)
URL : https://patchwork.freedesktop.org/series/70530/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7522 -> Patchwork_15658
Sum
From: Ville Syrjälä
The panel power sequencer can get confused if we follow a
PP_ON_DELAYS write with a PP_CONTROL power state target write.
Apparently it can latch the old PP_ON_DELAYS value instead of
the new one. Instead of mucking about with clock gating disables
until we enable the power seq
== Series Details ==
Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev3)
URL : https://patchwork.freedesktop.org/series/70530/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96a36e9a97da drm: Add support for DP 1.4 Compliance edid corruption test
-:47: ERR
On 12/5/2019 14:02, Daniele Ceraolo Spurio wrote:
We now only use 1 client without any plan to add more. The client is
also only holding information about the WQ and the process desc, so we
can just move those in the intel_guc structure and always use stage_id
0.
v2: fix comment (John)
v3: fix t
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev6)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7521 -> Patchwork_15657
Summary
---
**FAILURE**
Seri
Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.
This behavior is not accurate; actually, we need to return
the actual CRC value when co
== Series Details ==
Series: drm/i915/display: cleanup intel_bw_state on i915 module removal
URL : https://patchwork.freedesktop.org/series/70634/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7521 -> Patchwork_15655
Summar
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev6)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a23b05a241fc drm/i915/bios: pass devdata to parse_ddi_port
a0590902b587 drm/i915/bios: parse compression parameters b
== Series Details ==
Series: series starting with [xf86-video-intel,1/2] sna: Fix dirtyfb detection
URL : https://patchwork.freedesktop.org/series/70636/
State : failure
== Summary ==
Applying: sna: Fix dirtyfb detection
error: sha1 information is lacking or useless (src/sna/kgem.c).
error: co
On 12/5/2019 14:02, Daniele Ceraolo Spurio wrote:
We already have a couple of use-cases in the code and another one will
come in one of the later patches in the series.
v2: use the new function for the CT object as well
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harri
== Series Details ==
Series: drm/i915: Improve execbuf debug
URL : https://patchwork.freedesktop.org/series/70625/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7521 -> Patchwork_15654
Summary
---
**FAILURE**
Seri
On Mon, Dec 09, 2019 at 06:45:43PM +, Souza, Jose wrote:
> On Mon, 2019-12-09 at 18:40 +0200, Ville Syrjälä wrote:
> > On Fri, Dec 06, 2019 at 05:18:29PM -0800, José Roberto de Souza
> > wrote:
> > > On TGL the blending of all the streams have moved from DDI to
> > > transcoder, so now every tr
On 12/6/19 1:05 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/guc: Drop leftover preemption
code
URL : https://patchwork.freedesktop.org/series/70525/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7493_full -> Patchwork_15617_ful
On Mon, 2019-12-09 at 19:19 +0200, Ville Syrjälä wrote:
> On Fri, Dec 06, 2019 at 05:18:30PM -0800, José Roberto de Souza
> wrote:
> > Due to DDB overlaps the pipe enabling sequence is not always
> > crescent.
> > As the previous patch selects the first pipe/transcoder in the MST
> > stream to the
On Mon, 2019-12-09 at 18:40 +0200, Ville Syrjälä wrote:
> On Fri, Dec 06, 2019 at 05:18:29PM -0800, José Roberto de Souza
> wrote:
> > On TGL the blending of all the streams have moved from DDI to
> > transcoder, so now every transcoder working over the same MST port
> > must
> > send its stream to
On 12/9/2019 7:31 PM, Jani Nikula wrote:
On Tue, 03 Dec 2019, Jani Nikula wrote:
Now that the fbops member of struct fb_info is const, we can start
making the ops const as well.
v2: fix typo (Christophe de Dinechin)
Cc: Kirti Wankhede
Cc: k...@vger.kernel.org
Reviewed-by: Daniel Vetter
Si
== Series Details ==
Series: drm/i915/gt: Detect if we miss WaIdleLiteRestore (rev3)
URL : https://patchwork.freedesktop.org/series/70605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7521 -> Patchwork_15653
Summary
--
On Fri, Dec 06, 2019 at 05:18:30PM -0800, José Roberto de Souza wrote:
> Due to DDB overlaps the pipe enabling sequence is not always crescent.
> As the previous patch selects the first pipe/transcoder in the MST
> stream to the MST master and it needs to be enabled first this
> changes were needed
On Mon, Dec 09, 2019 at 11:16:27AM -0500, Sean Paul wrote:
> On Mon, Dec 9, 2019 at 10:21 AM Ville Syrjälä
> wrote:
> >
> > On Fri, Dec 06, 2019 at 08:52:33AM -0500, Sean Paul wrote:
> > > On Thu, Dec 05, 2019 at 09:39:35PM +0200, Ville Syrjälä wrote:
> > > > On Tue, Dec 03, 2019 at 12:36:27PM -05
On Fri, Dec 06, 2019 at 05:18:29PM -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port must
> send its stream to a master transcoder and master will send to DDI
> respecting the time
On Mon, Dec 9, 2019 at 10:21 AM Ville Syrjälä
wrote:
>
> On Fri, Dec 06, 2019 at 08:52:33AM -0500, Sean Paul wrote:
> > On Thu, Dec 05, 2019 at 09:39:35PM +0200, Ville Syrjälä wrote:
> > > On Tue, Dec 03, 2019 at 12:36:27PM -0500, Sean Paul wrote:
> > > > From: Sean Paul
> > > >
> > > > Now that
On Mon, Dec 9, 2019 at 10:18 AM Ville Syrjälä
wrote:
>
> On Fri, Dec 06, 2019 at 08:55:09AM -0500, Sean Paul wrote:
> > On Thu, Dec 05, 2019 at 09:33:19PM +0200, Ville Syrjälä wrote:
> > > On Tue, Dec 03, 2019 at 12:36:26PM -0500, Sean Paul wrote:
> > > > From: Sean Paul
> > > >
> > > > Currently
When DSC is enabled, we need to adjust the horizontal timings to account
for the compressed (and therefore reduced) link speed.
The compressed frequency ratio simplifies down to the ratio between
compressed and non-compressed bpp.
Bspec: 49263
Suggested-by: Vandita Kulkarni
Cc: Vandita Kulkarni
We'll be expanding afe_clk() to take DSC into account. Switch to using
it where DSC matters. Which is really everywhere that
intel_dsi_bitrate() is currently used in ICL DSI code.
The functional difference is that we round the result closest instead of
down.
Cc: Vandita Kulkarni
Cc: Ville Syrjäl
When compression is enabled, configure the DSI transcoder to use
compressed format.
Suggested-by: Vandita Kulkarni
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++
1 fil
Add basic hardware state readout for DSC, and check the most relevant
details in the state checker.
As a side effect, this should also get the power domains for the enabled
DSC on takeover, and subsequently disable DSC if it's not needed.
Cc: Manasi Navare
Cc: Vandita Kulkarni
Signed-off-by: Ja
Enable DSC for DSI, if specified in VBT.
This still lacks DSC aware get config implementation, and therefore
state checker will fail. Also mode valid is not there yet.
v5:
- add dsc get config call
v4:
- convert_rgb = true (Vandita)
- ignore max cdclock check (Vandita)
- rename pipe_config to cr
From: Vandita Kulkarni
When DSC is enabled consider the compression ratio that was used during
horizontal timing calculations.
This may still lead to warns due to rounding errors in the round-trip.
v2 by Jani:
- rebase on top of the more generic dsc state readout
Signed-off-by: Vandita Kulkarn
The ICL DSI pipe_bpp currently comes from
compute_baseline_pipe_bpp(). Fix it.
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i9
We'll make more use of it in the future.
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
Turns out this isn't compatible with DSI, where we use the value from
VBT. No functional changes.
Cc: Manasi Navare
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 12
drivers/gpu/drm
Add DSI specific computation and transmission to display of PPS.
With hopes that this approach will work for both DP and DSI encoders.
Cc: Manasi Navare
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vds
Turns out future DSI specific parameters aren't workable with the
approach of having the encoder specific functions in intel_vdsc.c. Make
intel_dsc_compute_params() a helper that does the encoder independent
parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
to intel_dp.c as i
Pass crtc_state to afe_clk() to be able to take compression into account
in the computation. Once we enable compression, that is.
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 40 +++
On Thu, 05 Dec 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Kulkarni, Vandita
>> ; Ville Syrjälä
>> Subject: [PATCH v3 13/13] drm/i915/dsi: add support
Add function for retrieving the DSC data for an encoder.
Initially, this is DSI specific, as DP does not use VBT settings for DSC
at all. It's also not very pretty.
In the future we might have a pointer from encoder to the child device,
which would make the child device list query here so much mo
Check for child devices that specify compression, and store the device
specific compression parameters in the display device data struct for
later use. Warn if compression is requested but not available.
Use fairly rigid checks for compression data for starters. These can be
made more dynamic late
v4 of https://patchwork.freedesktop.org/series/69540/
Added patches 7 and 14 (by Vandita) to improve state checking. We may
still need to improve the checks for horizontal timings due to potential
round-trip errors, but we're progressing. Otherwise mostly unchanged
from v3.
BR,
Jani.
Jani Nikul
Allow accessing the parent structure later on. Drop const for allowing
future modification as well.
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 7 ---
1 file changed, 4 insertions(+), 3 del
On Thu, Dec 05, 2019 at 04:29:37PM +0530, Ramalingam C wrote:
> On 2019-12-04 at 20:05:45 +0200, Ville Syrjala wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index af7f6d670e07..1a7d69843c12 100644
> > --- a/drivers/gpu/drm
On Thu, 05 Dec 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Kulkarni, Vandita
>> ; Ville Syrjälä
>> Subject: [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp
On Mon, Dec 09, 2019 at 03:13:13PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-12-09 15:01:37)
> > From: Ville Syrjälä
> >
> > The modparam checks performed by sna_mode_wants_tear_free() don't
> > generally work when the server is running as a regular user. Hence
> > we can't rely on
On Thu, 05 Dec 2019, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Navare, Manasi D
>> ; Kulkarni, Vandita
>> ; Ville Syrjälä
>> Subject: [PATCH v3 06/13] drm/
On Fri, Dec 06, 2019 at 08:52:33AM -0500, Sean Paul wrote:
> On Thu, Dec 05, 2019 at 09:39:35PM +0200, Ville Syrjälä wrote:
> > On Tue, Dec 03, 2019 at 12:36:27PM -0500, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > Now that we can rely on transcoder disable to toggle signalling off,
> > > i
On Fri, Dec 06, 2019 at 08:55:09AM -0500, Sean Paul wrote:
> On Thu, Dec 05, 2019 at 09:33:19PM +0200, Ville Syrjälä wrote:
> > On Tue, Dec 03, 2019 at 12:36:26PM -0500, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > Currently we rely on intel_hdcp_disable() to disable HDCP signalling in
> >
Quoting Ville Syrjala (2019-12-09 15:01:36)
> From: Ville Syrjälä
>
> Fix the accidentally swapped bpp and depth values passed to
> the addfb ioctl when we're testing for dirtyfb presence.
> Currently the addfb fails every time so we don't even test
> the actual dirtyfb ioctl.
>
> Signed-off-by:
Quoting Ville Syrjala (2019-12-09 15:01:37)
> From: Ville Syrjälä
>
> The modparam checks performed by sna_mode_wants_tear_free() don't
> generally work when the server is running as a regular user. Hence
> we can't rely on them to indicate whether FBC/PSR/etc is enabled.
> A lso the "Panel Self-
From: Ville Syrjälä
Fix the accidentally swapped bpp and depth values passed to
the addfb ioctl when we're testing for dirtyfb presence.
Currently the addfb fails every time so we don't even test
the actual dirtyfb ioctl.
Signed-off-by: Ville Syrjälä
---
src/sna/kgem.c | 4 ++--
1 file changed
From: Ville Syrjälä
The modparam checks performed by sna_mode_wants_tear_free() don't
generally work when the server is running as a regular user. Hence
we can't rely on them to indicate whether FBC/PSR/etc is enabled.
A lso the "Panel Self-Refresh" connector property doesn't actually
exist so we
intel_bw_state allocated memory is not getting freed even after
module removal.
kmemleak reported backtrace:
[<79019739>] kmemdup+0x17/0x40
[] intel_bw_duplicate_state+0x1b/0x40 [i915]
[<7423ed0c>] drm_atomic_get_private_obj_state+0xca/0x140
[<000
On Thu, Nov 28, 2019 at 04:48:04PM +0100, Maarten Lankhorst wrote:
> Op 27-11-2019 om 21:12 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > The code assumes we can omit the cfb allocation once fbc
> > has been enabled once. That's nonsense. Let's try to
> > reallocate it if we need to.
> >
On Tue, 03 Dec 2019, Jani Nikula wrote:
> Now that the fbops member of struct fb_info is const, we can start
> making the ops const as well.
>
> Cc: Miguel Ojeda Sandonis
> Cc: Robin van der Gracht
> Reviewed-by: Daniel Vetter
> Reviewed-by: Miguel Ojeda
> Acked-by: Robin van der Gracht
> Sig
On Tue, 03 Dec 2019, Jani Nikula wrote:
> Now that the fbops member of struct fb_info is const, we can start
> making the ops const as well.
>
> v2: fix typo (Christophe de Dinechin)
>
> Cc: Kirti Wankhede
> Cc: k...@vger.kernel.org
> Reviewed-by: Daniel Vetter
> Signed-off-by: Jani Nikula
On Tue, 03 Dec 2019, Jani Nikula wrote:
> Now that the fbops member of struct fb_info is const, we can start
> making the ops const as well.
>
> v2: fix typo (Christophe de Dinechin)
>
> Cc: Bruno Prémont
> Cc: linux-in...@vger.kernel.org
> Reviewed-by: Daniel Vetter
> Acked-by: Bruno Prém
Quoting Tvrtko Ursulin (2019-12-09 13:17:38)
>
> On 09/12/2019 12:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-12-09 12:23:14)
> >> From: Tvrtko Ursulin
> >>
> >> Convert i915_gem_check_execbuffer to return the error code instead of
> >> a boolean so our neat EINVAL debugging trick wo
On 09/12/2019 12:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-12-09 12:23:14)
From: Tvrtko Ursulin
Convert i915_gem_check_execbuffer to return the error code instead of
a boolean so our neat EINVAL debugging trick works within this function.
Who would need it? :)
Hey I found it he
Quoting Tvrtko Ursulin (2019-12-09 12:23:14)
> From: Tvrtko Ursulin
>
> Convert i915_gem_check_execbuffer to return the error code instead of
> a boolean so our neat EINVAL debugging trick works within this function.
Who would need it? :)
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wil
From: Tvrtko Ursulin
Convert i915_gem_check_execbuffer to return the error code instead of
a boolean so our neat EINVAL debugging trick works within this function.
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 22 ++-
1 file changed, 12 inser
Quoting Ramalingam C (2019-12-09 11:57:01)
> On 2019-12-05 at 13:11:29 +, Chris Wilson wrote:
> > Quoting Ramalingam C (2019-12-05 13:02:40)
> > > On 2019-12-05 at 12:20:12 +, Chris Wilson wrote:
> > > > Quoting Matthew Auld (2019-12-05 12:12:19)
> > > > > We would still need to clear the o
On 2019-12-09 at 12:03:22 +, Chris Wilson wrote:
> Quoting Ramalingam C (2019-12-09 11:57:01)
> > On 2019-12-05 at 13:11:29 +, Chris Wilson wrote:
> > > Quoting Ramalingam C (2019-12-05 13:02:40)
> > > > On 2019-12-05 at 12:20:12 +, Chris Wilson wrote:
> > > > > Quoting Matthew Auld (20
On 2019-12-05 at 13:11:29 +, Chris Wilson wrote:
> Quoting Ramalingam C (2019-12-05 13:02:40)
> > On 2019-12-05 at 12:20:12 +, Chris Wilson wrote:
> > > Quoting Matthew Auld (2019-12-05 12:12:19)
> > > > We would still need to clear the object(maybe I915_BO_ALLOC_CLEARED?)
> > > > in order
On Thu, Dec 05, 2019 at 08:28:51PM +, Souza, Jose wrote:
> On Thu, 2019-12-05 at 12:38 +0200, Ville Syrjälä wrote:
> > On Wed, Dec 04, 2019 at 12:55:10PM -0800, José Roberto de Souza
> > wrote:
> > > Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
> > > reverted the order that
Quoting Janusz Krzysztofik (2019-12-09 11:07:52)
> On future hardware with missing GGTT BAR we won't be able to exercise
> dma-buf access via that path. However, access to the dma sg list
> feature exposed by dma-buf can still be tested through blitter.
> Unfortunately we don't have any equivalent
On future hardware with missing GGTT BAR we won't be able to exercise
dma-buf access via that path. However, access to the dma sg list
feature exposed by dma-buf can still be tested through blitter.
Unfortunately we don't have any equivalently simple tests that use
blitter. Provide them.
Suggest
On Sun, 8 Dec 2019 at 16:13, Chris Wilson wrote:
>
> If someone else acquires the i915_vma before we complete our wait and
> unbind it, we currently error out with -EBUSY. Use -EAGAIN instead so
> that if necessary the caller is prepared to try again.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew
On Sun, 8 Dec 2019 at 16:13, Chris Wilson wrote:
>
> As i915_gem_object_unbind() waits on an rcu_barrier() to flush vm
> releases (and destruction of their bound vma), we have to be careful not
> to invoke that barrier from beneath the shrinker:
>
> <4> [430.222671] WARNING: possible circular lock
On Fri, 06 Dec 2019, Lucas De Marchi wrote:
> Just like in 523e0cc89b83 ("drm/i915/tgl: allow DVI/HDMI on port A"),
> the port checks when reading the VBT can easily not match what the
> platform really exposes. However here we only have some additional debug
> messages that are not adding much va
On Thu, 05 Dec 2019, Tvrtko Ursulin wrote:
> On 05/12/2019 15:43, Jani Nikula wrote:
>> Add a debugfs subdirectory i915_params with all the i915 module
>> parameters. This is a first step, with lots of boilerplate, and not much
>> benefit yet.
>>
>> This will result in a new device specific debug
Quoting Chris Wilson (2019-12-08 00:26:44)
> Since we didn't check and insist that args.pad must be zero for MMAP_GTT
> historically, we cannot insert a check now as old userspace may be
> feeding in garbage. As such the lack of check is enshrined into the ABI,
> so add a comment to remind us we ca
Hi Chris,
On Sat, Dec 07, 2019 at 06:29:37PM +, Chris Wilson wrote:
> Include all the number fields for describing the GT, as well as the
> current boolean flags, primarily for inclusion in error states.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
Reviewed-by: Andi Shyti
Thanks,
And
On 07/12/2019 01:08, Chris Wilson wrote:
This reverts commit 343aae776a58a67fa153825385e6fe90e3185c5b.
__for_each_physical_engine() reprograms the context, invalidating the
use of e->flags to select engines, necessitating e->index instead.
Withot also fixing up the engine selection, the result
Thank you very much, well the patch series is here:
https://patchwork.freedesktop.org/series/70059/
The failures here were some gem related stuff:
WARNING: possible circular locking dependency detected
<4> [73.588465] 5.4.0-rc8-CI-Patchwork_15602+ #1 Tainted: G U
<4> [73.588467]
Stan,
I don't think retest is needed if the failure is not caused by your change.
Please send the patch series to me, I will address those failures.
I will soon address the below failures and re-report the results.
Lakshmi.
-Original Message-
From: Lisovskiy, Stanislav
Sent: Monday, D
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