As the default preempt-reset timeout has been increased from 100ms to
640ms, we need a corresponding increase in our own timeout so that we
allow enough time for the preempt-reset to occur and close the hung
contexts.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_persistence.c | 34
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle SDEISR according to PCH
rather than platform (rev3)
URL : https://patchwork.freedesktop.org/series/70073/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7428 -> Patchwork_15455
===
Hi Ville,
It's great to see Intel putting attention into this, thanks!
On Wed, Nov 27, 2019 at 1:09 AM Ville Syrjala
wrote:
> Implement the missing w/a for back to back FBC disable + plane
> update on glk+. The scariest part of this is that we now start
> to use flip nuke so that we can avoid th
+ Imre
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: tiistai 26. marraskuuta 2019 22.49
> To: Sripada, Radhakrishna
> Cc: Chery, Nanley G ; intel-
> g...@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville
> Subject: Re: [Intel-gfx] [PATCH v7 7/7] d
== Series Details ==
Series: i915/gem_ctx_persistence: Bump the reset timeout
URL : https://patchwork.freedesktop.org/series/70066/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426_full -> IGTPW_3762_full
Summary
---
== Series Details ==
Series: drm/i915/display: Suspend MST topology manager before destroy fbdev
URL : https://patchwork.freedesktop.org/series/70081/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7428 -> Patchwork_15454
Su
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev11)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7428 -> Patchwork_15453
Summary
-
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev11)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f5811af5d1c2 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
9773ae450
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle SDEISR according to PCH
rather than platform (rev2)
URL : https://patchwork.freedesktop.org/series/70073/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7428 -> Patchwork_15452
===
MST do topology probe in threads, so this running threads needs to be
flushed before fbdev is destroyed as when a new MST node is found it
calls drm_kms_helper_hotplug_event() that calls fbdev functions
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109964
Signed-off-by: José Roberto de So
== Series Details ==
Series: drm/i915/gt: Manual rc6 entry upon parking (rev3)
URL : https://patchwork.freedesktop.org/series/70026/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7428 -> Patchwork_15451
Summary
---
*
On Thu, Nov 21, 2019 at 12:14:55PM -0800, Clint Taylor wrote:
From: Clint Taylor
During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.
Bspe
On Tue, Nov 26, 2019 at 4:14 PM Patchwork
wrote:
>
> == Series Details ==
>
> Series: bios: dot not discard address space
> URL : https://patchwork.freedesktop.org/series/70075/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15449
> ===
== Series Details ==
Series: drm/i915/display/tgl: Do not program clockgating
URL : https://patchwork.freedesktop.org/series/70076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15450
Summary
---
**
Hey! Saw your comment on the RHBZ regarding this, figured I'd take a look
since I've got some DPCD backlight related fixes for one of your other laptops
on the list as well.
On Thu, 2019-10-10 at 00:13 +0800, Lee Shawn C wrote:
> This panel (manufacturer is SDC, product ID is 0x4141)
> used manufa
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse n
On Tue, Nov 26, 2019 at 02:03:08AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on
> gen12+
> URL : https://patchwork.freedesktop.org/series/69982/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes fro
== Series Details ==
Series: bios: dot not discard address space
URL : https://patchwork.freedesktop.org/series/70075/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15449
Summary
---
**FAILURE**
On Mon, Nov 25, 2019 at 02:53:12PM +0200, Kai Vehmanen wrote:
> Starting with gen12, PORT_A can be connected to a transcoder
> with audio support. Modify the existing logic that disabled
> audio on PORT_A unconditionally.
>
> Signed-off-by: Kai Vehmanen
Reviewed-by: Matt Roper
> ---
> drivers
I'm about to post some more review comments for the v2 version of this, but
some comments down below...
On Tue, 2019-10-08 at 12:19 +0300, Jani Nikula wrote:
> On Mon, 07 Oct 2019, Adam Jackson wrote:
> > On Mon, 2019-10-07 at 12:08 +0300, Jani Nikula wrote:
> >
> > > The problem with the EDID q
On Mon, Nov 25, 2019 at 02:53:13PM +0200, Kai Vehmanen wrote:
> Starting with gen12, PORT_A can be also connected to DP
> transcoder. Update code in intel_dp_init() to take this
> into account.
>
> Signed-off-by: Kai Vehmanen
I don't think this function gets called on gen12; this one is for
pre-
== Series Details ==
Series: drm/i915: Serialise i915_active_fence_set() with itself (rev2)
URL : https://patchwork.freedesktop.org/series/70068/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15448
Summary
On Tue, Nov 26, 2019 at 11:20:18PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915: Handle SDEISR according to PCH
> rather than platform
> URL : https://patchwork.freedesktop.org/series/70073/
> State : failure
>
> == Summary ==
>
> CI Bug Log -
Now that we rapidly park the GT when the GPU idles, we often find
ourselves idling faster than the RC6 promotion timer. Thus if we tell
the GPU to enter RC6 manually as we park, we can do so quicker (by
around 50ms, half an EI on average) and marginally increase our
powersaving across all execlists
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle SDEISR according to PCH
rather than platform
URL : https://patchwork.freedesktop.org/series/70073/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15447
==
Talked with HW team and this is a left over, driver should not
program clockgating, dekel firmware will be reponsible for any
clockgating programing.
BSpec issue: 20885
BSpec: 49292
Cc: Lucas De Marchi
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_
== Series Details ==
Series: drm/i915/gt: Manual rc6 entry upon parking (rev2)
URL : https://patchwork.freedesktop.org/series/70026/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15446
Summary
---
*
On Tue, 2019-11-26 at 14:49 -0800, Matt Roper wrote:
> On Tue, Nov 26, 2019 at 02:03:08PM -0800, Souza, Jose wrote:
> > On Tue, 2019-11-26 at 21:40 +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 22, 2019 at 04:54:53PM -0800, José Roberto de Souza
> > > wrote:
> > > > Commit 9c722e17c1b9 ("drm/i915:
We don't need to keep the pci rom mapped during the entire
intel_bios_init() anymore. Move it to the previous copy_vbt() function
and rename it to oprom_get_vbt() since now it's responsible to to all
operations related to get the vbt from the oprom.
v2: fix double __iomem attribute detected by spa
When we map the VBT through pci_map_rom() we may not be allowed
to simply discard the address space and go on reading the memory.
That doesn't work on my test system, but by dumping the rom via
sysfs I can can get the correct vbt. So change our find_vbt() to do
the same as done by pci_read_rom(), i
The unaligned ioread32() will make us read byte by byte looking for the
vbt. We could just as well have done a ioread8() + a shift and avoid the
extra confusion on how we are looking for "$VBT".
However when using ACPI it's guaranteed the VBT is 4-byte aligned
per spec, so we can probably assume i
v4 of https://patchwork.freedesktop.org/series/69790/
Add missing unmap in patch 2 and update 3rd patch to the bare minimum.
Lucas De Marchi (3):
drm/i915/bios: do not discard address space
drm/i915/bios: fold pci rom map/unmap into copy function
drm/i915/bios: assume vbt is 4-byte aligned
On Tue, Nov 26, 2019 at 02:03:08PM -0800, Souza, Jose wrote:
> On Tue, 2019-11-26 at 21:40 +0200, Ville Syrjälä wrote:
> > On Fri, Nov 22, 2019 at 04:54:53PM -0800, José Roberto de Souza
> > wrote:
> > > Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
> > > reverted the order that
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, November 26, 2019 2:00 PM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re: [PATCH v7 7/7]
On Tue, 2019-11-26 at 22:15 +0200, Ville Syrjälä wrote:
> On Fri, Nov 22, 2019 at 04:54:56PM -0800, José Roberto de Souza
> wrote:
> > Disabling pipe/transcoder clock before power down sink could cause
> > sink lost signal, causing it to trigger a hotplug to notify source
> > that link signal was l
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/psr: Add bits per pixel
limitation (rev2)
URL : https://patchwork.freedesktop.org/series/70002/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15445
==
On Tue, 2019-11-26 at 21:40 +0200, Ville Syrjälä wrote:
> On Fri, Nov 22, 2019 at 04:54:53PM -0800, José Roberto de Souza
> wrote:
> > Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
> > reverted the order that pipes gets disabled because of TGL
> > master/slave relationship betwee
On Tue, Nov 26, 2019 at 01:52:39PM -0800, Sripada, Radhakrishna wrote:
> Hi Matt,
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Tuesday, November 26, 2019 12:49 PM
> > To: Sripada, Radhakrishna
> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> > ; Syrjala, Vi
On Tue, 2019-11-26 at 13:50 -0800, Matt Roper wrote:
> On Tue, Nov 26, 2019 at 01:41:15PM -0800, Souza, Jose wrote:
> > On Tue, 2019-11-26 at 13:07 -0800, Matt Roper wrote:
> > > The bspec tells us 'Program SHPD_FILTER_CNT with the "500
> > > microseconds
> > > adjusted" value before enabling hotpl
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, November 26, 2019 12:49 PM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re: [PATC
On Tue, Nov 26, 2019 at 01:41:15PM -0800, Souza, Jose wrote:
> On Tue, 2019-11-26 at 13:07 -0800, Matt Roper wrote:
> > The bspec tells us 'Program SHPD_FILTER_CNT with the "500
> > microseconds
> > adjusted" value before enabling hotplug detection' on CNP+. We
> > haven't
> > been touching this r
On Tue, 2019-11-26 at 13:07 -0800, Matt Roper wrote:
> The bspec tells us 'Program SHPD_FILTER_CNT with the "500
> microseconds
> adjusted" value before enabling hotplug detection' on CNP+. We
> haven't
> been touching this register at all thus far, but we should probably
> follow the bspec's guid
On Tue, 2019-11-26 at 13:07 -0800, Matt Roper wrote:
> When looking at SDEISR to determine the connection status of combo
> outputs, we should use the phy index rather than the port index.
> Although they're usually the same thing, EHL's DDI-D (port D) is
> attached to PHY-A and SDEISR doesn't even
== Series Details ==
Series: drm/i915/display: Force the state compute phase once to enable PSR
(rev2)
URL : https://patchwork.freedesktop.org/series/7/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15444
=
On Tue, 2019-11-26 at 13:07 -0800, Matt Roper wrote:
> The South Display is part of the PCH so we should technically be
> basing
> our port detection logic off the PCH in use rather than the platform
> generation.
Reviewed-by: José Roberto de Souza
>
> Cc: Lucas De Marchi
> Signed-off-by: Matt
The expected downside to commit 58b4c1a07ada ("drm/i915: Reduce nested
prepare_remote_context() to a trylock") was that it would need to return
-EAGAIN to userspace in order to resolve potential mutex inversion. Such
an unsightly round trip is unnecessary if we could atomically insert a
barrier int
== Series Details ==
Series: drm/i915/fbc: Fix FBC for glk+
URL : https://patchwork.freedesktop.org/series/70062/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15442
Summary
---
**FAILURE**
Serio
The South Display is part of the PCH so we should technically be basing
our port detection logic off the PCH in use rather than the platform
generation.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
1 file changed, 4 insertions(+), 4 del
The bspec tells us 'Program SHPD_FILTER_CNT with the "500 microseconds
adjusted" value before enabling hotplug detection' on CNP+. We haven't
been touching this register at all thus far, but we should probably
follow the bspec's guidance.
The register also exists on LPT and SPT, but there isn't a
When looking at SDEISR to determine the connection status of combo
outputs, we should use the phy index rather than the port index.
Although they're usually the same thing, EHL's DDI-D (port D) is
attached to PHY-A and SDEISR doesn't even have bits for a "D" output.
It's also possible that future p
== Series Details ==
Series: drm/i915/selftest: If reconfigure_sseu is busy, try again (rev2)
URL : https://patchwork.freedesktop.org/series/70060/
State : failure
== Summary ==
Applying: drm/i915/selftest: If reconfigure_sseu is busy, try again
error: patch failed: drivers/gpu/drm/i915/i915_a
On Mon, Nov 25, 2019 at 04:26:35PM -0800, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-spa
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15441
Summary
---
**FAILURE*
On Tue, 2019-11-26 at 22:05 +0200, Ville Syrjälä wrote:
> On Fri, Nov 22, 2019 at 04:54:55PM -0800, José Roberto de Souza
> wrote:
> > On TGL the blending of all the streams have moved from DDI to
> > transcoder, so now every transcoder working over the same MST port
> > must
> > send its stream to
== Series Details ==
Series: drm/i915: Double check vma placement upon gaining the vm lock
URL : https://patchwork.freedesktop.org/series/70057/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15440
Summary
On Fri, Nov 22, 2019 at 04:54:56PM -0800, José Roberto de Souza wrote:
> Disabling pipe/transcoder clock before power down sink could cause
> sink lost signal, causing it to trigger a hotplug to notify source
> that link signal was lost.
>
> Cc: Lucas De Marchi
> Signed-off-by: José Roberto de So
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Remove skl_ddl_allocation struct
Okay!
___
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct
03280b410f87 drm/i915: Move dbuf slice update to pro
Now that we rapidly park the GT when the GPU idles, we often find
ourselves idling faster than the RC6 promotion timer. Thus if we tell
the GPU to enter RC6 manually as we park, we can do so quicker (by
around 50ms, half an EI on average) and marginally increase our
powersaving across all execlists
On Fri, Nov 22, 2019 at 04:54:55PM -0800, José Roberto de Souza wrote:
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port must
> send its stream to a master transcoder and master will send to DDI
> respecting the time
On Fri, Nov 22, 2019 at 04:54:54PM -0800, José Roberto de Souza wrote:
> If the CRTC is going from enabled to disabled and it is a port sync
> slave, it needs to check to the old state to be disabled before the
> port sync master.
>
> Cc: Manasi Navare
> Cc: Matt Roper
> Cc: Maarten Lankhorst
>
On Fri, Nov 22, 2019 at 04:54:53PM -0800, José Roberto de Souza wrote:
> Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
> reverted the order that pipes gets disabled because of TGL
> master/slave relationship between transcoders in MST mode.
>
> But as stated in a comment in skl_
== Series Details ==
Series: i915/gem_ctx_persistence: Bump the reset timeout
URL : https://patchwork.freedesktop.org/series/70066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> IGTPW_3762
Summary
---
**SUCCE
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev3)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15439
Summary
---
**FAILURE**
Seri
On Mon, Nov 25, 2019 at 08:32:58AM -0800, Niranjan Vishwanathapura wrote:
> > And putting the cpu PFN of a ZONE_DEVICE device page into
> > sg_dma_address still looks very wrong to me
>
> The below call in patch 7 does convert any cpu PFN to device address.
> So, it won't be CPU PFN.
> i915_dmem_c
The expected downside to commit 58b4c1a07ada ("drm/i915: Reduce nested
prepare_remote_context() to a trylock") was that it would need to return
-EAGAIN to userspace in order to resolve potential mutex inversion. Such
an unsightly round trip is unnecessary if we could atomically insert a
barrier int
On Mon, Nov 25, 2019 at 11:33:27AM -0500, Jerome Glisse wrote:
> On Fri, Nov 22, 2019 at 11:33:12PM +, Jason Gunthorpe wrote:
> > On Fri, Nov 22, 2019 at 12:57:27PM -0800, Niranjana Vishwanathapura wrote:
>
> [...]
>
> > > +static int
> > > +i915_range_fault(struct i915_svm *svm, struct hmm_r
As the default preempt-reset timeout has been increased from 100ms to
640ms, we need a corresponding increase in our own timeout so that we
allow enough time for the preempt-reset to occur and close the hung
contexts.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_persistence.c | 22
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev3)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4bb56f2cb8ef drm/i915/bios: pass devdata to parse_ddi_port
a8b033ae3755 drm/i915/bios: parse compression parameters b
Quoting Tvrtko Ursulin (2019-11-26 17:33:09)
>
> On 26/11/2019 17:25, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-11-26 17:22:23)
> >> Quoting Tvrtko Ursulin (2019-11-26 17:04:43)
> >>>
> >>> On 26/11/2019 15:26, Chris Wilson wrote:
> diff --git a/drivers/gpu/drm/i915/i915_vma.c
> >>>
From: Ville Syrjälä
Precompute the override cfb stride value so that we can check
it when determining if flip nuke can be used or not.
The hardware has 13 bits for this, so we can shrink the storage
to u16 while at it.
v2: Don't explode when crtc_state->enable_fbc lies to us
Signed-off-by: Vil
On 26/11/2019 17:25, Chris Wilson wrote:
Quoting Chris Wilson (2019-11-26 17:22:23)
Quoting Tvrtko Ursulin (2019-11-26 17:04:43)
On 26/11/2019 15:26, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index e5512f26e20a..f6e661428b02 100644
---
Quoting Chris Wilson (2019-11-26 17:22:23)
> Quoting Tvrtko Ursulin (2019-11-26 17:04:43)
> >
> > On 26/11/2019 15:26, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_vma.c
> > > b/drivers/gpu/drm/i915/i915_vma.c
> > > index e5512f26e20a..f6e661428b02 100644
> > > --- a/drivers/g
== Series Details ==
Series: drm/i915/gem: Excise the per-batch whitelist from the context
URL : https://patchwork.freedesktop.org/series/70040/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7425 -> Patchwork_15438
Summary
Quoting Tvrtko Ursulin (2019-11-26 17:04:43)
>
> On 26/11/2019 15:26, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_vma.c
> > b/drivers/gpu/drm/i915/i915_vma.c
> > index e5512f26e20a..f6e661428b02 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.c
> > +++ b/drivers/gpu/drm/i915/i91
Quoting Tvrtko Ursulin (2019-11-26 17:11:04)
>
> On 26/11/2019 17:08, Tvrtko Ursulin wrote:
> >
> > On 26/11/2019 17:05, Chris Wilson wrote:
> >> Quoting Tvrtko Ursulin (2019-11-26 17:00:53)
> >>>
> >>> On 26/11/2019 16:47, Chris Wilson wrote:
> Following 58b4c1a07ada ("drm/i915: Reduce nest
On 26/11/2019 17:08, Tvrtko Ursulin wrote:
On 26/11/2019 17:05, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-11-26 17:00:53)
On 26/11/2019 16:47, Chris Wilson wrote:
Following 58b4c1a07ada ("drm/i915: Reduce nested
prepare_remote_context()
to a trylock"), we punt to the caller if the l
From: Ville Syrjälä
Currently the code (ab)uses cache->vma to indicate the plane
visibility. I want to nuke that so let's add a dedicated boolean
for this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 21 ++---
drivers/gpu/drm/i915/i915_drv.h
From: Ville Syrjälä
Rather than playing around with vma+flags let's just grab
the fence id from within and stash that directly in the fbc
cache/params.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 33 +---
drivers/gpu/drm/i915/i915_drv.h
From: Ville Syrjälä
The hardware automagically nukes the cfb on flip. We can use
that whenever the plane/crtc configuration doesn't change too
much. Let's hook that up.
We'll need this for glk+ since we need to introduce an extra
vblank wait after FBC disable. As we're currently disabling
FBC ar
From: Ville Syrjälä
Replace the 'gen9 && !glk' with the slightly more obvious
'gen9_bc || bxt'.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/
From: Ville Syrjälä
fbc.enabled == (fbc.crtc != NULL), so let's just nuke fbc.enabled.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 23 +--
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 9 insertions(+), 15 deletions(-)
dif
From: Ville Syrjälä
We don't want to use the FBC hardware render tracking so let's not
enable it. To use the hw tracking properly we'd anyway need to
integrate this into the command submissing path as the register is
context saved, and if rendering happens via the ppgtt we'd have
to configure it
From: Ville Syrjälä
On glk+ the hardware gets confused if we disable FBC while
it's recompressing and we perform a plane update during the
same frame. The result is that top of the screen gets corrupted.
We can avoid that by giving the hardware enough time to finish
the FBC disable before we tou
From: Ville Syrjälä
Now that we have the glk+ w/a for back to back fbc disable + plane
update in place we can once more enable fbc on glk+ by default.
Cc: Daniel Drake
Cc: Paulo Zanoni
Cc: Jian-Hong Pan
Cc: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/int
From: Ville Syrjälä
Precompute the override cfb stride value so that we can check
it when determining if flip nuke can be used or not.
The hardware has 13 bits for this, so we can shrink the storage
to u16 while at it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c
From: Ville Syrjälä
i965gm no longer needs the fence for scanout so we should be
do what we do for ctg+ and only configure a fence for FBC
when we have one.
In theory this should do nothing atm on account of
intel_fbc_can_activate() requiring the fence, but since
we do this for g4x+ let's do it
From: Ville Syrjälä
Not sure where the single pipe only restriction came for fbc1.
Nothing I can see that would prevent this.
v2: Nuke no_fbc_on_multiple_pipes() too
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/display/intel_fbc.c
From: Ville Syrjälä
Move intel_crtc_active() next to its only remaining
user (pre-g4x wm code).
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 19 ---
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu
From: Ville Syrjälä
Implement the missing w/a for back to back FBC disable + plane
update on glk+. The scariest part of this is that we now start
to use flip nuke so that we can avoid the w/a (as it would cost
us one extra frame for every plane update). Hopefully my "can
we flip nuke safely?" che
From: Ville Syrjälä
We're missing a workaround in the fbc code for all glk+ platforms
which can cause corruption around the top of the screen. So
enabling fbc by default is a bad idea. I'm not keen to backport
the w/a so let's start by disabling fbc by default on all glk+.
We'll lift the restrict
On 26/11/2019 17:05, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-11-26 17:00:53)
On 26/11/2019 16:47, Chris Wilson wrote:
Following 58b4c1a07ada ("drm/i915: Reduce nested prepare_remote_context()
to a trylock"), we punt to the caller if the local intel_context
happens to be busy as we tr
Quoting Tvrtko Ursulin (2019-11-26 17:00:53)
>
> On 26/11/2019 16:47, Chris Wilson wrote:
> > Following 58b4c1a07ada ("drm/i915: Reduce nested prepare_remote_context()
> > to a trylock"), we punt to the caller if the local intel_context
> > happens to be busy as we try to rewrite the sseu (due to
On 26/11/2019 15:26, Chris Wilson wrote:
The current unbind + retry of i915_gem_object_ggtt_pin() allows for
someone else to sneak and claim the vma under a different placement
before the first GGTT bind is complete. Leading to confusion and
complaints all over.
Ideally we would pull the evict
On 26/11/2019 16:47, Chris Wilson wrote:
Following 58b4c1a07ada ("drm/i915: Reduce nested prepare_remote_context()
to a trylock"), we punt to the caller if the local intel_context
happens to be busy as we try to rewrite the sseu (due to retiring in
another thread). As the interlude should be sho
Following 58b4c1a07ada ("drm/i915: Reduce nested prepare_remote_context()
to a trylock"), we punt to the caller if the local intel_context
happens to be busy as we try to rewrite the sseu (due to retiring in
another thread). As the interlude should be short, spin until the lock
is available.
The r
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 250 ++--
1 file changed, 236 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/
Those patch series, do some initial preparation DBuf manipulating code
cleanups, i.e remove redundant structures/code, switch to mask
based DBuf manupulation, get into use DBuf assignment according to
BSpec rules.
Stanislav Lisovskiy (4):
drm/i915: Remove skl_ddl_allocation struct
drm/i915: Mo
On Mon, Nov 25, 2019 at 05:01:53PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Support more QGV points (rev4)
> URL : https://patchwork.freedesktop.org/series/69886/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> d993a329d475 drm/i915: Suppor
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match
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