[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev2)

== Series Details == Series: drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel (rev2) URL : https://patchwork.freedesktop.org/series/57989/ State : failure == Summary == Applying: drm/i915: Get active pending request for given context Using index info to reconstru

[Intel-gfx] [PATCH v5 1/3] drm/i915: Get active pending request for given context

This patch gives us the active pending request count which is yet to be submitted to the GPU. V2: * Change 64-bit to atomic for request count. (Tvrtko Ursulin) V3: * Remove mutex for request count. * Rebase. * Fixes hitting underflow for predictive request. (Tvrtko Ursulin) V4: * Rebase. V

[Intel-gfx] [PATCH v5 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type

This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration fro

[Intel-gfx] [PATCH v5 0/3] drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel

This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS. ---| App /KPI| % Power Benefit (mW) |

[Intel-gfx] [PATCH v5 3/3] drm/i915: Predictive governor to control slice/subslice/eu

High resolution timer is used for predictive governor to control eu/slice/subslice based on workloads. param is provided to enable/disable/update timer configuration V2: * Fix code style. * Move predictive_load_timer into a drm_i915_private structure. * Make generic function to set optimum

Re: [Intel-gfx] [kbuild-all] Re: [PATCH 15/15] dma-buf: Remove kernel map/unmap hooks

On 11/19/19 12:43 AM, Daniel Vetter wrote: On Mon, Nov 18, 2019 at 4:23 PM kbuild test robot wrote: Hi Daniel, I love your patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v5.4-rc8 next-20191115] [if your patch is applied to the

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access URL : https://patchwork.freedesktop.org/series/69949/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7411_full -> Patchwork_15413_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling

== Series Details == Series: drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling URL : https://patchwork.freedesktop.org/series/69948/ State : success == Summary == CI Bug Log - changes from CI_DRM_7411_full -> Patchwork_15412_full ===

Re: [Intel-gfx] [RFC 06/13] drm/i915/svm: Page table mirroring support

On Sat, Nov 23, 2019 at 11:53:52PM +, Jason Gunthorpe wrote: On Fri, Nov 22, 2019 at 08:44:18PM -0800, Niranjan Vishwanathapura wrote: On Fri, Nov 22, 2019 at 11:33:12PM +, Jason Gunthorpe wrote: > On Fri, Nov 22, 2019 at 12:57:27PM -0800, Niranjana Vishwanathapura wrote: > > > +static i

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access URL : https://patchwork.freedesktop.org/series/69949/ State : success == Summary == CI Bug Log - changes from CI_DRM_7411 -> Patchwork_15413 ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access URL : https://patchwork.freedesktop.org/series/69949/ State : warning == Summary == $ dim checkpatch origin/drm-tip 635aca2f93e1 drm/i915/gt: Mark the execlists->a

[Intel-gfx] [CI 2/4] drm/i915: Serialise with engine-pm around requests on the kernel_context

As the engine->kernel_context is used within the engine-pm barrier, we have to be careful when emitting requests outside of the barrier, as the strict timeline locking rules do not apply. Instead, we must ensure the engine_park() cannot be entered as we build the request, which is simplest by takin

[Intel-gfx] [CI 1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

Since we want to do a lockless read of the current active request, and that request is written to by process_csb also without serialisation, we need to instruct gcc to take care in reading the pointer itself. Otherwise, we have observed execlists_active() to report 0x40. [ 2400.760381] igt/para-4

[Intel-gfx] [CI 4/4] drm/i915/gt: Schedule request retirement when timeline idles

The major drawback of commit 7e34f4e4aad3 ("drm/i915/gen8+: Add RC6 CTX corruption WA") is that it disables RC6 while Skylake (and friends) is active, and we do not consider the GPU idle until all outstanding requests have been retired and the engine switched over to the kernel context. If userspac

[Intel-gfx] [CI 3/4] drm/i915/gt: Adapt engine_park synchronisation rules for engine_retire

In the next patch, we will introduce a new asynchronous retirement worker, fed by execlists CS events. Here we may queue a retirement as soon as a request is submitted to HW (and completes instantly), and we also want to process that retirement as early as possible and cannot afford to postpone (as

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling

== Series Details == Series: drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling URL : https://patchwork.freedesktop.org/series/69948/ State : success == Summary == CI Bug Log - changes from CI_DRM_7411 -> Patchwork_15412

[Intel-gfx] [PATCH] drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling

In case of CRC mismatch, panel generates IRQ_HD and PSR2 gets disabled by i915 driver. Due to this, PSR2 will only be enabled back only if system is rebooted or cold boot. So, in cases of suspend resume stress test and S0ix stress test, when we encounter this CRC issue on a particular iteration, on

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove tautological compare in eb_relocate_vma

== Series Details == Series: drm/i915: Remove tautological compare in eb_relocate_vma URL : https://patchwork.freedesktop.org/series/69934/ State : success == Summary == CI Bug Log - changes from CI_DRM_7410_full -> Patchwork_15410_full Sum

[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_param: Keep the engine active while peeking at vm layout

The implicit soft-pinning we use to probe the vm layout using execbuf, depends on the batch remaining active (not retired) between execbufs. Naturally, if the background retire worker runs the batch is retired and the implicit soft-pinning is free to use a fresh address. Signed-off-by: Chris Wilso

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Include the subsubtest for live_parallel_engines

== Series Details == Series: drm/i915/selftests: Include the subsubtest for live_parallel_engines URL : https://patchwork.freedesktop.org/series/69933/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7409_full -> Patchwork_15409_full =

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

== Series Details == Series: series starting with [1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access URL : https://patchwork.freedesktop.org/series/69944/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7411 -> Patchwork_15411 =

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

== Series Details == Series: series starting with [1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access URL : https://patchwork.freedesktop.org/series/69944/ State : warning == Summary == $ dim checkpatch origin/drm-tip d93945f76695 drm/i915/gt: Mark the execlists->acti

[Intel-gfx] [PATCH 2/4] drm/i915: Serialise with engine-pm around requests on the kernel_context

As the engine->kernel_context is used within the engine-pm barrier, we have to be careful when emitting requests outside of the barrier, as the strict timeline locking rules do not apply. Instead, we must ensure the engine_park() cannot be entered as we build the request, which is simplest by takin

[Intel-gfx] [PATCH 1/4] drm/i915/gt: Mark the execlists->active as the primary volatile access

Since we want to do a lockless read of the current active request, and that request is written to by process_csb also without serialisation, we need to instruct gcc to take care in reading the pointer itself. Otherwise, we have observed execlists_active() to report 0x40. [ 2400.760381] igt/para-4

[Intel-gfx] [PATCH 4/4] drm/i915/gt: Schedule request retirement when timeline idles

The major drawback of commit 7e34f4e4aad3 ("drm/i915/gen8+: Add RC6 CTX corruption WA") is that it disables RC6 while Skylake (and friends) is active, and we do not consider the GPU idle until all outstanding requests have been retired and the engine switched over to the kernel context. If userspac

[Intel-gfx] [PATCH 3/4] drm/i915/gt: Adapt engine_park synchronisation rules for engine_retire

In the next patch, we will introduce a new asynchronous retirement worker, fed by execlists CS events. Here we may queue a retirement as soon as a request is submitted to HW (and completes instantly), and we also want to process that retirement as early as possible and cannot afford to postpone (as

[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/fbdev: Fallback to non tiled mode if all tiles not present"

== Series Details == Series: Revert "drm/fbdev: Fallback to non tiled mode if all tiles not present" URL : https://patchwork.freedesktop.org/series/69924/ State : success == Summary == CI Bug Log - changes from CI_DRM_7409_full -> Patchwork_15405_full ==