== Series Details ==
Series: drm/i915: update rawclk also on resume (rev2)
URL : https://patchwork.freedesktop.org/series/68817/
State : failure
== Summary ==
Applying: drm/i915: update rawclk also on resume
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/in
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previo
On 2019-10-25 at 17:13:19 -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
>
> Cc: Ramalingam C
> Signed-off-by: José Roberto de Souza
>
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission (rev3)
URL : https://patchwork.freedesktop.org/series/68685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7227_full -> Patchwork_15079_full
=
On Thu, Oct 31, 2019, Ville Syrjala wrote:
>On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
>> Since CNP it's possible for rawclk to have two different values, 19.2
>> and 24 MHz. If the value indicated by SFUSE_STRAP register is
>> different from the power on default for PCH_RAWCLK
== Series Details ==
Series: series starting with [01/11] drm/i915: Split detaching and removing the
vma
URL : https://patchwork.freedesktop.org/series/68788/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15078_full
=
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: Share the computation of idle
frames
URL : https://patchwork.freedesktop.org/series/68844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15097
=
== Series Details ==
Series: drm/i915: Split detaching and removing the vma
URL : https://patchwork.freedesktop.org/series/68787/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15077_full
Summary
-
I plan to debug MST with this patches next week but I guess at least
the 4 first patches can be merged. The 5th too if someone else reviews
it, the selection of the master transcoder was tested by me and Lucas
and the problem in not in any of this patches.
On Tue, 2019-10-29 at 18:24 -0700, Lucas
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Just avoid the additional read in case DP_TP_CTL is enabled:
> read it once and save the value.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33 -
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> For MST on Tiger Lake there are different moments when we need to
> configure the transcoder clock select. For the first link this is in
> step
> 7.a of the spec, before training the link. For additional streams
> this
> should be done as
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Wrap drm_atomic_get_old_connector_state so we can get the
> intel_digital_connector_state and make it easier to migrate to intel
> types.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Lucas De Marchi
> ---
> .../gpu/drm/i915/
DC3C0 could have already exit so no need to always sleep, so lets
read the register with the state.
Cc: Imre Deak
Cc: Anshuman Gupta
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
A recent change in BSpec allow us to change EXTLINE while transcoder
is enabled so this allow us to change it even when doing the first
fastset after taking over previous hardware state set by BIOS.
BIOS don't enable PSR, so if sink supports PSR it will be enabled on
the first fastset, so moving th
Both activate functions and the dc3co disable function were doing the
same thing, so better move to a function and share.
Also while at it adding a WARN_ON to catch invalid values.
Cc: Anshuman Gupta
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.
== Series Details ==
Series: drm/i915/selftests: Spin on all engines simultaneously (rev3)
URL : https://patchwork.freedesktop.org/series/68836/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15096
Summary
== Series Details ==
Series: drm/fbdev: Fallback to non tiled mode if all tiles not present
URL : https://patchwork.freedesktop.org/series/68838/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15095
Summary
== Series Details ==
Series: drm/i915: Preload LUTs if the hw isn't currently using them
URL : https://patchwork.freedesktop.org/series/68785/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15076_full
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest
== Series Details ==
Series: drm/fbdev: Fallback to non tiled mode if all tiles not present
URL : https://patchwork.freedesktop.org/series/68838/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
64383a27c565 drm/fbdev: Fallback to non tiled mode if all tiles not present
-:62: ERRO
== Series Details ==
Series: drm/i915/selftests: Spin on all engines simultaneously (rev2)
URL : https://patchwork.freedesktop.org/series/68836/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15094
Summary
On Thu, Oct 31, 2019 at 09:23:36PM +, Chris Wilson wrote:
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine
In case of tiled displays, if we hotplug just one connector,
fbcon currently just selects the preferred mode and if it is
tiled mode then that becomes a problem if rest of the tiles are
not present.
So in the fbdev driver on hotplug when we probe the client modeset,
we we dont find all the connecto
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest
Whoops, replied to the wrong one
Reviewed-by: Lyude Paul
On Tue, 2019-10-29 at 15:03 +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> The current link status contains bytes 0x202 through 0x207, but we also
> want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> so tha
Quoting Arkadiusz Hiler (2019-10-31 12:40:35)
> On Wed, Oct 30, 2019 at 10:22:37PM +, Matthew Auld wrote:
> > On Tue, 29 Oct 2019 at 16:51, Matthew Auld wrote:
> > >
> > > Intended for upstream testing so that we can still exercise the LMEM
> > > plumbing and !i915_ggtt_has_aperture paths. Smo
== Series Details ==
Series: drm/i915/lmem: add the fake lmem region (rev2)
URL : https://patchwork.freedesktop.org/series/68733/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15075_full
Summary
-
Hi Dave & Daniel,
Here's the last -misc-next pull request for 5.5. Lots of refactoring going on
this week which results in a negative diffstat. Only thing to highlight is the
dma-buf heap introduction and revert, which you are already aware of, so
hopefully no other surprises here.
drm-misc-next-
== Series Details ==
Series: drm/i915: Replace rcu_swap_protected() with rcu_replace_pointer()
URL : https://patchwork.freedesktop.org/series/68833/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/gen
== Series Details ==
Series: drm/i915: Expose more formats
URL : https://patchwork.freedesktop.org/series/68832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7233 -> Patchwork_15092
Summary
---
**SUCCESS**
No reg
== Series Details ==
Series: drm/i915: Skip MCHBAR queries on dgfx
URL : https://patchwork.freedesktop.org/series/68829/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7233 -> Patchwork_15091
Summary
---
**SUCCESS**
On Thu, 2019-10-31 at 05:38 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
> (rev2)
> URL : https://patchwork.freedesktop.org/series/68691/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7221_full
On Tue, Oct 29, 2019 at 02:00:27AM -0600, Jonathan Corbet wrote:
> On Tue, 29 Oct 2019 08:31:22 +0800
> Changbin Du wrote:
>
> > Here python is different from C. Both empty string and None are False in
> > python.
> > Note such condition is common in python.
>
> Treating both as a False value i
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 1feace5d6a4a1acf44dde2bfb5c36cc0b1cf559c
Gitweb:
https://git.kernel.org/tip/1feace5d6a4a1acf44dde2bfb5c36cc0b1cf559c
Author:Paul E. McKenney
AuthorDate:Mon, 23 Sep 2019 15:22:15 -07:00
Committ
Hi Dave and Daniel,
Here goes drm-intel-fixes-2019-10-31:
- Fix PCH reference clock for FDI on HSW/BDW which was causing users blank
screen
- Small documentation fix for TGL display PLLs
Thanks,
Rodrigo.
The following changes since commit d6d5df1db6e9d7f8f76d2911707f7d5877251b02:
Linux 5.4-
On Thu, Oct 31, 2019 at 04:28:57PM +0100, Janusz Krzysztofik wrote:
exec-shared-gtt-* subtests use hardcoded values for object size and
softpin offset, based on 4kB GTT alignment assumption. That may result
in those subtests failing when run on future backing stores with
possibly larger minimum
May be this patch can just be merged with the other patch in this series
that changes gem_exec_reloc.
Vanshi
On Thu, Oct 31, 2019 at 04:28:54PM +0100, Janusz Krzysztofik wrote:
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addres
On Thu, Oct 31, 2019 at 04:28:55PM +0100, Janusz Krzysztofik wrote:
Some tests assume 4kB offset alignment while using softpin. That
assumption may be wrong on future GEM backends with possibly larger
minimum page sizes. As a result, those tests may either fail on
softpin at offsets which are i
== Series Details ==
Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
URL : https://patchwork.freedesktop.org/series/68824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7231 -> Patchwork_15090
From: Ville Syrjälä
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the primary
plane. Add the require bits to expose the new formats.
v2: Reorder the formats for consistency
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma
From: Ville Syrjälä
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_disp
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
v2: Add all the stuff I missed earlier!
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++-
From: Ville Syrjälä
Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 62 +++
From: Ville Syrjälä
Same series as before but fp16 caused a bunch of rebasing.
I also dropped the ckey stuff for now. It's probably time to
write actual tests for that stuff.
Everything here is reviewed already.
Ville Syrjälä (7):
drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
d
From: Ville Syrjälä
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff
From: Ville Syrjälä
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 60 +++
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file c
On Wed, Oct 30, 2019 at 06:30:40PM -0700, Daniele Ceraolo Spurio wrote:
Recent GuC doesn't require the shared area. We still have one user in
i915 (engine reset via guc) because we haven't updated the command to
match the current guc submission flow [1]. Since the flow in guc is
about to change a
== Series Details ==
Series: series starting with [CI,01/12] drm/i915: Handle a few more cases for
crtc hw/uapi split, v3.
URL : https://patchwork.freedesktop.org/series/68775/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7224_full -> Patchwork_15074_full
===
On Wed, Oct 30, 2019 at 06:30:39PM -0700, Daniele Ceraolo Spurio wrote:
Recent GuC binaries (including all the ones we're currently using)
don't require this shared area anymore, having moved the relevant
entries into the stage pool instead. i915 itself doesn't write
anything into it either, so w
On Thu, Oct 31, 2019 at 08:40:58AM +0100, Janusz Krzysztofik wrote:
On Wednesday, October 30, 2019 10:19:43 PM CET Vanshidhar Konda wrote:
On Wed, Oct 30, 2019 at 06:15:35PM +0100, Janusz Krzysztofik wrote:
>Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
>addresses for !ppgtt")
On Thu, Oct 31, 2019 at 08:11:24AM -0700, Stuart Summers wrote:
> dgfx does not map the MCHBAR MMIO into the GFX device BAR.
> Skip this sequence when running on dgfx.
>
> Signed-off-by: Stuart Summers
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> 1 file changed
Some tests assume 4kB page size while using softpin. That assumption
may be wrong on future GEM backends with possibly larger minimum page
sizes. As a result, those tests may either fail on softpin at offsets
which are incorrectly aligned, may silently skip such incorrectly
aligned addresses assu
Some tests assume 4kB offset alignment while using softpin. That
assumption may be wrong on future GEM backends with possibly larger
minimum page sizes. As a result, those tests may either fail on
softpin at offsets which are incorrectly aligned, may silently skip
such incorrectly aligned address
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addresses possibly
occupied by other users of shared GTT. Unfortunately, that filtering
doesn't distinguish between actually occupied addresses and otherwise
invalid softpin offsets. As
exec-shared-gtt-* subtests use hardcoded values for object size and
softpin offset, based on 4kB GTT alignment assumption. That may result
in those subtests failing when run on future backing stores with
possibly larger minimum page sizes.
Replace hardcoded constants with values calculated from m
The basic-range subtest assumes 4kB GTT alignment while calculating
softpin offsets. On future backends with possibly larger minimum page
sizes the test will fail as a half of calculated offsets to be tested
will be incorrectly aligned.
Replace hardcoded constants corresponding to the assumed 4kB
dgfx does not map the MCHBAR MMIO into the GFX device BAR.
Skip this sequence when running on dgfx.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_dr
On Thu, Oct 31, 2019 at 12:26:05PM +0100, Maarten Lankhorst wrote:
> Prepare to split up hw and uapi machinally, by adding a uapi and
> hw alias. We will remove the base in a bit. This is a split from the
> original uapi/hw patch, which did it all in one go.
>
> Signed-off-by: Maarten Lankhorst
>
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-10-31 14:32:05)
>> Chris Wilson writes:
>>
>> > Check that the context's ring register state still matches our
>> > expectations prior to execution.
>> >
>> > Signed-off-by: Chris Wilson
>> > Cc: Mika Kuoppala
>> > ---
>> > drivers/gpu/drm/i
On Thu, Oct 31, 2019 at 12:26:00PM +0100, Maarten Lankhorst wrote:
> Prepare to split up hw and uapi machinally, by adding a uapi and
> hw alias. We will remove the base in a bit. This is a split from the
> original uapi/hw patch, which did it all in one go.
>
> Signed-off-by: Maarten Lankhorst
On Thu, Oct 31, 2019 at 12:26:07PM +0100, Maarten Lankhorst wrote:
> Split up plane_state->base to hw. This is done using the following patch:
>
> @@
> struct intel_plane_state *T;
> identifier x =~
> "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
> @@
> -T->base.x
> +T
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson
Cc: Anna Karas
Cc: Tvrtko Ursulin
---
Having remember to ask for a fixed frequency!
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 339 +-
.../drm/i915/selftest
On Thu, Oct 31, 2019 at 12:26:04PM +0100, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> be
Quoting Mika Kuoppala (2019-10-31 14:32:05)
> Chris Wilson writes:
>
> > Check that the context's ring register state still matches our
> > expectations prior to execution.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 73 ++
Chris Wilson writes:
> If the idle_pulse fails to flush the i915_active, dump the tree to see
> if that has any clues.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> drivers/gpu/drm/i915/i915_active.h|
Quoting Chris Wilson (2019-10-31 14:18:56)
> My memory says, and my assumption in this code, is that the
> the iterator is safe against insertions -- we won't get horribly lost if
> the tree is rebalanced as we walk.
Actually, the iterator is not perfect across rebalances. It won't matter
here in
Chris Wilson writes:
> Check that the context's ring register state still matches our
> expectations prior to execution.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 73 -
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h
== Series Details ==
Series: series starting with [01/12] drm/i915: Handle a few more cases for crtc
hw/uapi split, v3.
URL : https://patchwork.freedesktop.org/series/68818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15089
Quoting Mika Kuoppala (2019-10-31 14:11:58)
> Chris Wilson writes:
>
> > If the idle_pulse fails to flush the i915_active, dump the tree to see
> > if that has any clues.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> > drivers/gpu/drm/i
Chris Wilson writes:
> If the idle_pulse fails to flush the i915_active, dump the tree to see
> if that has any clues.
>
> Signed-off-by: Chris Wilson
> ---
> .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> drivers/gpu/drm/i915/i915_active.h| 2 +
> drivers/gpu/drm/i915/se
== Series Details ==
Series: series starting with [01/12] drm/i915: Handle a few more cases for crtc
hw/uapi split, v3.
URL : https://patchwork.freedesktop.org/series/68818/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9b2cc20d8bdd drm/i915: Handle a few more cases for crtc h
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson
Cc: Anna Karas
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 324 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed,
On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between th
== Series Details ==
Series: drm/i915: update rawclk also on resume
URL : https://patchwork.freedesktop.org/series/68817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15088
Summary
---
**SUCCESS**
On Wed, 30 Oct 2019 at 19:22, Chris Wilson wrote:
>
> In order to keep the assert_bind_count() valid, we need to hold the vma
> page reference until after we drop the bind count. However, we must also
> keep the drm_mm_remove_node() as the last action of i915_vma_unbind() so
> that it serialises w
Minor nit.
s/Plump/Plumb/
M
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Thursday, October 31, 2019 6:59 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Plump dev_priv all the way to
>icl_{hdr, sdr_y}_plane_mask()
>
>From:
Chris Wilson writes:
> When checking the heartbeat pulse, we expect it to have been sent by the
> time we have slept. We can verify this by checking the engine serial
> number to see if that matches the predicted pulse serial. It will always
> be true if, and only if, the pulse was sent by itself
From this set patches 2,5,6 look all ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 2.10.2019 19.25, Ville Syrjala wrote:
From: Ville Syrjälä
We don't need to special case PCH vs. gen4 when setting up the LVDS
crtc_mask. Just claim pipes A|B|C work and
intel_encoder_possible_crtcs() will drop
On Wed, Oct 30, 2019 at 10:22:37PM +, Matthew Auld wrote:
> On Tue, 29 Oct 2019 at 16:51, Matthew Auld wrote:
> >
> > Intended for upstream testing so that we can still exercise the LMEM
> > plumbing and !i915_ggtt_has_aperture paths. Smoke tested on Skull Canyon
> > device. This works by allo
== Series Details ==
Series: series starting with [1/3] drm/i915: Drop GEM context as a direct link
from i915_request (rev2)
URL : https://patchwork.freedesktop.org/series/68769/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15073_full
=
== Series Details ==
Series: drm/i915: Drop inspection of execbuf flags during evict
URL : https://patchwork.freedesktop.org/series/68816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15087
Summary
--
== Series Details ==
Series: series starting with [1/5] drm/i915/gt: Always track callers to
intel_rps_mark_interactive()
URL : https://patchwork.freedesktop.org/series/68770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15072_full
== Series Details ==
Series: drm/i915/gt: Always track callers to intel_rps_mark_interactive() (rev2)
URL : https://patchwork.freedesktop.org/series/68764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15071_full
=
Op 31-10-2019 om 11:30 schreef Ville Syrjälä:
> On Thu, Oct 31, 2019 at 10:15:41AM +0100, Maarten Lankhorst wrote:
>> Op 30-10-2019 om 17:19 schreef Ville Syrjälä:
>>> On Wed, Oct 30, 2019 at 03:26:53PM +0100, Maarten Lankhorst wrote:
get_crtc_from_states() is called before plane_state is copi
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degam
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gp
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhors
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() defi
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
drivers/gpu/dr
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Changes since v1:
- set src/dst rectangles after copy_uap
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediate
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Changes since v2:
- Incorporate Ville's feedback.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity always look at the uapi state.
Changes since v1:
- Convert entirety of intel_legacy_cursor_update
== Series Details ==
Series: series starting with [1/4] drm/i915:
s/icl_is_nv12_y_plane/icl_is_sdr_y_plane/
URL : https://patchwork.freedesktop.org/series/68815/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previo
With the goal of removing the serialisation from around execbuf, we will
no longer have the privilege of there being a single execbuf in flight
at any time and so will only be able to inspect the user's flags within
the carefully controlled execbuf context. i915_gem_evict_for_node() is
the only use
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