Am 29.10.19 um 01:31 schrieb Changbin Du:
But is it, really? I agree with Jon about the distinction between None
and '' being confusing.
Here python is different from C. Both empty string and None are False in python.
Note such condition is common in python.
The one is a empty string str(''),
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream (rev2)
URL : https://patchwork.freedesktop.org/series/68671/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15041
Summary
---
This is the minimum change to support 1 (and only 1) DP-MST monitor
connected on Tiger Lake. This change was isolated from previous patch
from José. In order to support more streams we will need to create a
master-slave relation on the transcoders and that is not currently
working yet.
v2: remove
== Series Details ==
Series: drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
URL : https://patchwork.freedesktop.org/series/68691/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15040
Summary
--
== Series Details ==
Series: series starting with [1/5] drm/i915/selftests: Drop global engine
lookup for gt selftests
URL : https://patchwork.freedesktop.org/series/68623/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7196_full -> Patchwork_15016_full
===
== Series Details ==
Series: drm/i915/blt: fixup block_size rounding (rev3)
URL : https://patchwork.freedesktop.org/series/68670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15039
Summary
---
**SU
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2)
URL : https://patchwork.freedesktop.org/series/66770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15038
Summary
Non-TC ports always have tc_mode == TC_PORT_TBT_ALT so it was
switching aux to TC mode for all combo-phy ports, happily this did
not caused any issue but is better follow BSpec.
Also this is reserved bit before ICL.
Fixes: 6f211ed43438 ("drm/i915/icl: Set TBT IO in Aux transaction")
Cc: Imre Deak
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2)
URL : https://patchwork.freedesktop.org/series/66770/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d19968439852 drm/i915: Adding YUV444 packed format support for skl+ (V13)
-:9: WARNING:
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission
URL : https://patchwork.freedesktop.org/series/68685/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15037
==
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15035
Summary
--
== Series Details ==
Series: lib/color_encoding: Fix up support for XYUV format.
URL : https://patchwork.freedesktop.org/series/68684/
State : failure
== Summary ==
Applying: lib/color_encoding: Fix up support for XYUV format.
error: sha1 information is lacking or useless (lib/igt_color_encodi
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block (rev2)
URL : https://patchwork.freedesktop.org/series/67811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15033
Summary
---
**FAI
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
7d2dee12e3
== Series Details ==
Series: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
(rev2)
URL : https://patchwork.freedesktop.org/series/68584/
State : failure
== Summary ==
Applying: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
Using index info to r
Hi Chris, Lakshmi,
On Mon, Oct 28, 2019 at 10:01:13PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
> URL : https://patchwork.freedesktop.org/series/68644/
> State : failure
>
> == Summary ==
>
> CI Bug Log - ch
== Series Details ==
Series: drm/i915: Program LUT before intel_color_commit() if LUT was not
previously set (rev2)
URL : https://patchwork.freedesktop.org/series/68278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15032
From: Matthew Auld
There is nothing to say that the obj->base.size is actually a multiple
of the block_size.
v2: Use round_up() as block_size is a power-of-two
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
S
From: Matthew Auld
There is nothing to say that the obj->base.size is actually a multiple
of the block_size.
v2: Use round_up() as block_size is a power-of-two
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the GuC suspend/remove entirely as we do
not need to
> > From: Ceraolo Spurio, Daniele
> > Sent: Monday, October 28, 2019 11:30 AM
> > To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o
> GuC
> > submission but enabled
> >
> >
> >
> > On 10/28/19 11:17 AM, Hiatt, Don wrot
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib/igt_color_enc
== Series Details ==
Series: drm/i915/gt: Tidy up rps irq handler to use intel_gt
URL : https://patchwork.freedesktop.org/series/68616/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7195_full -> Patchwork_15014_full
Summary
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream
URL : https://patchwork.freedesktop.org/series/68671/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15030
Summary
---
**SU
Quoting Patchwork (2019-10-28 20:33:10)
> == Series Details ==
>
> Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
> URL : https://patchwork.freedesktop.org/series/68654/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7204 -> Patchwork_150
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 8 patches are
currently undergoing review/revision changes. The first 8 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/67078/
Expecting feedback for the 9th
From: Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_fourcc.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Dhinakaran Pandiyan
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++--
1 file changed, 16 insertion
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Nanley G Chery
Cc: Jason Ekstrand
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 11 +++
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse n
Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix tr
From: Dhinakaran Pandiyan
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery
Cc: Matt Roper
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Sig
From: Dhinakaran Pandiyan
intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file ch
From: Dhinakaran Pandiyan
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so m
From: Dhinakaran Pandiyan
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream
URL : https://patchwork.freedesktop.org/series/68671/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cce4d3a65919 drm/i915/tgl: add support to one DP-MST stream
-:29: CHECK:OPEN_ENDED_LINE: Lines should
== Series Details ==
Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
URL : https://patchwork.freedesktop.org/series/68654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15029
S
Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.
v2: Don't forget both fill/copy.
Signed-off-by: Chris Wilson
Cc: Ma
== Series Details ==
Series: drm/i915/blt: fixup block_size rounding
URL : https://patchwork.freedesktop.org/series/68670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15028
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/selftests: Drop global engine lookup for gt selftests
URL : https://patchwork.freedesktop.org/series/68615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7195_full -> Patchwork_15013_full
===
> From: Ceraolo Spurio, Daniele
> Sent: Monday, October 28, 2019 11:30 AM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
> submission but enabled
>
>
>
> On 10/28/19 11:17 AM, Hiatt, Don wrote:
> >> From: Cer
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
old LFP panel mode data in block 42. Let's start parsing this block to
fill in the panel fixed mode on devices with a >=229 VBT.
v2:
* Update according to the recent updates:
- DTD size is now 16 bits instead of 24
- p
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type
definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15027
=
== Series Details ==
Series: drm/print: cleanup and new drm_device based logging (rev3)
URL : https://patchwork.freedesktop.org/series/67795/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15026
Summary
---
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type
definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b48e99db722b drm/dsi: clean up DSI data type definitions
1e7022690364 drm/
Since commit 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after
vblank waits"), I am seeing an ugly colored flash of the first few display
lines on 2 Cherry Trail devices when the gamma table gets set for the first
time. A blue flash on a GPD win and a yellow flash on an Asus T100HA.
Th
Hi,
On 25-10-2019 21:45, Ville Syrjälä wrote:
On Fri, Oct 25, 2019 at 09:23:47PM +0200, Hans de Goede wrote:
Hi,
On 21-10-2019 16:39, Ville Syrjälä wrote:
On Sun, Oct 20, 2019 at 08:19:33PM +0200, Hans de Goede wrote:
Since commit 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse n
== Series Details ==
Series: drm/print: cleanup and new drm_device based logging (rev3)
URL : https://patchwork.freedesktop.org/series/67795/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40c33aad0053 drm/i915: use drm_debug_enabled() to check for debug categories
98a1b348acd0
On 10/28/19 11:17 AM, Hiatt, Don wrote:
From: Ceraolo Spurio, Daniele
Sent: Monday, October 28, 2019 9:44 AM
To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
submission but enabled
On 10/24/19 9:29 AM, don.hi...@
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Initialise ret
URL : https://patchwork.freedesktop.org/series/68662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203 -> Patchwork_15025
Summary
For the HPD interrupt functionality the HW depends on power wells in the
display core domain to be on. Accordingly when enabling these power
wells the HPD polling logic will force an HPD detection cycle to account
for hotplug events that may have happened when such a power well was
off.
Thus a det
> From: Ceraolo Spurio, Daniele
> Sent: Monday, October 28, 2019 9:44 AM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
> submission but enabled
>
>
>
> On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
> > From:
On Mon, Oct 28, 2019 at 07:45:09PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 28, 2019 at 01:00:31PM +0200, Imre Deak wrote:
> > For the HPD interrupt functionality the HW depends on power wells in the
> > display core domain to be on. Accordingly when enabling these power
> > wells the HPD polling
On Mon, Oct 28, 2019 at 10:04:57AM -0700, Lucas De Marchi wrote:
> This is the minimum change to support 1 (and only 1) DP-MST monitor
> connected on Tiger Lake. This change was isolated from previous patch
> from José. In order to support more streams we will need to create a
> master-slave relati
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Initialise ret
URL : https://patchwork.freedesktop.org/series/68662/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a204f00d5275 drm/i915/selftests: Initialise ret
-:8: WARNING:COMMIT_LOG_LONG_LINE: Poss
== Series Details ==
Series: drm/i915/execlists: Simply walk back along request timeline on reset
(rev6)
URL : https://patchwork.freedesktop.org/series/68601/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203 -> Patchwork_15023
===
== Series Details ==
Series: sna/video/overlay: Declare support for depth 8 and 30
URL : https://patchwork.freedesktop.org/series/68655/
State : failure
== Summary ==
Applying: sna/video/overlay: Declare support for depth 8 and 30
error: sha1 information is lacking or useless (src/sna/sna_vide
On Mon, Oct 28, 2019 at 01:00:31PM +0200, Imre Deak wrote:
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events
Quoting Ville Syrjälä (2019-10-28 16:46:46)
> On Mon, Oct 28, 2019 at 04:39:50PM +, Matthew Auld wrote:
> > There is nothing to say that the obj->base.size is actually a multiple
> > of the block_size.
> >
> > Reported-by: Chris Wilson
> > Signed-off-by: Matthew Auld
> > Cc: Chris Wilson
>
On Mon, 28 Oct 2019 at 07:02, Imre Deak wrote:
>
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events that may
On Mon, 2019-10-28 at 10:04 -0700, Lucas De Marchi wrote:
> This is the minimum change to support 1 (and only 1) DP-MST monitor
> connected on Tiger Lake. This change was isolated from previous patch
> from José. In order to support more streams we will need to create a
> master-slave relation on t
== Series Details ==
Series: drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
URL : https://patchwork.freedesktop.org/series/68612/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15012_full
===
On Mon, Oct 28, 2019 at 12:38:22PM +0200, Jani Nikula wrote:
> Add new struct drm_device based logging macros modeled after the core
> kernel device based logging macros. These would be preferred over the
> drm printk and struct device based macros in drm code, where possible.
>
> We have existing
This is the minimum change to support 1 (and only 1) DP-MST monitor
connected on Tiger Lake. This change was isolated from previous patch
from José. In order to support more streams we will need to create a
master-slave relation on the transcoders and that is currently not
working yet.
Cc: José Ro
On Mon, Oct 28, 2019 at 04:39:50PM +, Matthew Auld wrote:
> There is nothing to say that the obj->base.size is actually a multiple
> of the block_size.
>
> Reported-by: Chris Wilson
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4
While processing CSB there is no need to look at GuC submission
settings, just check if engine is configured for execlists mode.
While today GuC submission is disabled it's settings are still
based on modparam values that might not correctly reflect actual
submission status in case of any fallback
On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
From: Don Hiatt
Check to see if GuC submission is enabled before requesting the
EXIT_S_STATE action.
You're only skipping the resume, but does it make any sense to do the
suspend action if we're not going to call the resume one? Does guc do
On Fri, Oct 25, 2019 at 04:06:22PM -0700, Matt Roper wrote:
> We're seeing some failures where an aux transaction still shows as
> 'busy' well after the timeout limit that the hardware is supposed to
> enforce. Improve the error message so that we can see exactly which aux
> channel this error hap
On Fri, 25 Oct 2019 at 22:06, Chris Wilson wrote:
>
> Currently we insert a arbitration point every 128MiB during a blitter
> copy. At 8GiB/s, this is around 30ms. This is a little on the large side
> if we need to inject a high priority work, so reduced it down to 8MiB or
> roughly 1ms.
>
> Signe
There is nothing to say that the obj->base.size is actually a multiple
of the block_size.
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gp
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15011_full
===
Op 28-10-2019 om 16:05 schreef Ville Syrjälä:
> On Mon, Oct 28, 2019 at 03:20:34PM +0100, Maarten Lankhorst wrote:
>> Op 28-10-2019 om 12:30 schreef Ville Syrjala:
>>> From: Ville Syrjälä
>>>
>>> The change from the uapi coordinates to the internal coordinates
>>> broke the cursor on i845/i865 due
exec-shared-gtt-* subtests use hardcoded values for object size and
softpin offset, based on 4kB page size assumption. That may result in
those subtests failing when run on future backing stores with possibly
larger minimum page sizes.
Replace hardcoded constants with values derived from minimum
Two tests - gem_exec_reloc and gem_softpin - define local helpers for
calculation of softpin offset canonical addresses. As more users are
expected, replace those local instances with a single shared one under
lib/.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
---
lib/igt_x86.c
Some tests assume 4kB page size while using softpin. That assumption
may be wrong on future GEM backends with possibly larger minimum page
sizes. As a result, those tests may either fail on softpin at offsets
which are incorrectly aligned, may silently skip such incorrectly
aligned addresses assu
Some tests assume 4kB page size while using softpin. That assumption
may be wrong on future GEM backends with possibly larger minimum page
sizes. As a result, those tests may either fail on softpin at offsets
which are incorrectly aligned, may silently skip such incorrectly
aligned addresses assu
From: Janusz Krzysztofik
The basic-range subtest assumes 4kB page size while calculating softpin
offsets. On future backends with possibly larger minimum page sizes
a half of calculated offsets to be tested may be incorrectly detected
as occupied by other users and skiped, significantly distorin
Quoting Michal Wajdeczko (2019-10-28 14:22:29)
> On Mon, 28 Oct 2019 14:09:05 +0100, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2019-10-28 12:57:03)
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
> >> b/drivers/gpu/drm/i915/gt/intel_lrc.h
> >> index 99dc576a4e25..23dde908334
On Fri, Oct 25, 2019 at 4:36 AM Thierry Reding wrote:
>
> On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> > Hi,
> >
> > Thanks for your review and comments. Please see inline below.
> >
> > On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> > wrote:
> > >
> > > On Tue, Oct 22, 2019 a
On Mon, Oct 28, 2019 at 02:57:26PM +0200, Joonas Lahtinen wrote:
> Quoting paul...@kernel.org (2019-10-22 22:12:08)
> > From: "Paul E. McKenney"
> >
> > This commit replaces the use of rcu_swap_protected() with the more
> > intuitively appealing rcu_replace() as a step towards removing
> > rcu_sw
On Sat, Oct 26, 2019 at 08:01:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
> URL : https://patchwork.freedesktop.org/series/68528/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7176_full -> Pa
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image (rev2)
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201 -> Patchwork_15022
==
== Series Details ==
Series: drm/i915: Collect user engines at driver_register phase
URL : https://patchwork.freedesktop.org/series/68609/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15009_full
Summ
On Mon, Oct 28, 2019 at 03:20:34PM +0100, Maarten Lankhorst wrote:
> Op 28-10-2019 om 12:30 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > The change from the uapi coordinates to the internal coordinates
> > broke the cursor on i845/i865 due to src and dst getting swapped.
> > Fix it.
> >
== Series Details ==
Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width
URL : https://patchwork.freedesktop.org/series/68646/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201 -> Patchwork_15021
Summar
Update from the DCS specification.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
include/video/mipi_display.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 6b6390dfa203..928f8c4b6658 100644
--- a/include/v
Rename picture parameter set (it's a long packet, not a long write) and
compression mode (it's not a DCS command) enumerations according to the
DSI specification. Order the types according to the spec. Use tabs
instead of spaces for indentation. Use all lower case for hex.
Cc: Vandita Kulkarni
Re
The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
v1.02, for more than a decade. Rename the enumeration to match the spec.
v2: add comment about the rename (David Lechner)
Cc: David Lechner
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/tiny/st7586.c |
Add helper functions for sending the DSI compression mode and picture
parameter set data type packets. For the time being, limit the support
to using VESA DSC 1.1 and the default PPS. This may need updating if the
need arises for proprietary compression or non-default PPS, however keep
it simple fo
Add execute queue and compressed pixel stream packet data types for
completeness.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/dri
Chris Wilson writes:
> smatch complains about
> drivers/gpu/drm/i915//display/intel_display.c:14403
> intel_set_dp_tp_ctl_normal() error: uninitialized symbol 'conn'.
> because it has no way to determine that the loop must have an entry.
> Tell the static analysers to ignore the local, it will a
On Fri, Oct 25, 2019 at 04:13:40PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 25, 2019 at 04:06:21PM -0700, Matt Roper wrote:
> > TGL's extra ports also bring extra AUX channels.
> >
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 6
> > drivers/gpu
Chris Wilson writes:
> Keep smatch quiet,
>
> drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu()
> error: uninitialized symbol 'ret'.
> drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu()
> error: uninitialized symbol 'ret'.
>
> Signed-off-by:
== Series Details ==
Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width
URL : https://patchwork.freedesktop.org/series/68646/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4da018f49855 drm/i915: Fix i845/i865 cursor width
19cde21752fa drm/i915: Fix max curs
== Series Details ==
Series: drm/i915/selftests: Measure basic throughput of blit routines (rev2)
URL : https://patchwork.freedesktop.org/series/68610/
State : failure
== Summary ==
Applying: drm/i915/selftests: Measure basic throughput of blit routines
Using index info to reconstruct a base t
Keep smatch quiet,
drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu()
error: uninitialized symbol 'ret'.
drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu()
error: uninitialized symbol 'ret'.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i9
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