On 2019-10-24 at 00:24:00 +0530, Souza, Jose wrote:
> On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > > HDCP could be fused off, so not all GEN9+ platforms will support
> > > it.
> > Here HDCP stands for HDCP1.4, so please
On 2019-10-18 at 17:41:24 -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
>
> Cc: Manasi Navare
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
Looks good to me.
Reviewed-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/displa
On 2019-10-23 at 14:49:32 -0700, José Roberto de Souza wrote:
> Right now if sink reported any PSR error or if it fails to
> acknowledge the PSR wakeup it sets a flag and do not attempt to
> enable PSR anymore. That is the safest approach to avoid repetitive
> glitches and allowed us to have PSR en
Quoting Tapani Pälli (2019-10-24 07:39:50)
>
>
> On 10/24/19 12:49 AM, Chris Wilson wrote:
> > Quoting Patchwork (2019-10-23 22:20:49)
> >>* igt@i915_selftest@live_workarounds:
> >> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
> >> [3]:
> >> https://intel-gfx-ci.01.org/tree/dr
On 10/24/19 12:49 AM, Chris Wilson wrote:
Quoting Patchwork (2019-10-23 22:20:49)
* igt@i915_selftest@live_workarounds:
- {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
On 2019-10-24 at 07:14:56 +0100, Chris Wilson wrote:
> Quoting Ramalingam C (2019-10-24 02:32:01)
> > On 2019-10-23 at 14:31:04 +0100, Chris Wilson wrote:
> > > If we are doing a normal GPU reset triggered after detecting a long
> > > period of stalled work, we can take our time and allow the engin
Quoting Ramalingam C (2019-10-24 02:32:01)
> On 2019-10-23 at 14:31:04 +0100, Chris Wilson wrote:
> > If we are doing a normal GPU reset triggered after detecting a long
> > period of stalled work, we can take our time and allow the engines to
> > quiesce. Since we've stopped submission to the engi
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159_full -> Patchwork_14944_full
Summary
---
**SUC
== Series Details ==
Series: drm/i915/gt: Try to more gracefully quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159_full -> Patchwork_14943_full
=
== Series Details ==
Series: drm/dp: Add function to parse EDID descriptors for adaptive sync limits
URL : https://patchwork.freedesktop.org/series/68488/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14959
== Series Details ==
Series: drm/i915/selftests: Flush any i915_active callback work as well
URL : https://patchwork.freedesktop.org/series/68487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14958
Summar
On 2019/10/24 上午5:57, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:50 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
driver
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:48 +0800
Jason Wang wrote:
Add support to parse mdev class id table.
Reviewed-by: Parav Pandit
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scr
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:47 +0800
Jason Wang wrote:
Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we nee
== Series Details ==
Series: drm/i915/selftests: Flush interrupts before disabling tasklets
URL : https://patchwork.freedesktop.org/series/68486/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14957
Summary
== Series Details ==
Series: drm/i915/display/psr: Print in debugfs if PSR is not enabled because of
sink
URL : https://patchwork.freedesktop.org/series/68482/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14955
==
== Series Details ==
Series: drm/i915/selftests: Flush interrupts before disabling tasklets
URL : https://patchwork.freedesktop.org/series/68486/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d179199a3774 drm/i915/selftests: Flush interrupts before disabling tasklets
-:10: WARN
== Series Details ==
Series: string-choice: add yesno(), onoff(), enableddisabled(), plural()
helpers (rev2)
URL : https://patchwork.freedesktop.org/series/68461/
State : failure
== Summary ==
Applying: string-choice: add yesno(), onoff(), enableddisabled(), plural()
helpers
error: sha1 info
== Series Details ==
Series: drm/i915: Fix PCH reference clock for FDI on HSW/BDW (rev2)
URL : https://patchwork.freedesktop.org/series/68411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14953
Summary
--
== Series Details ==
Series: drm: Add support for integrated privacy screens
URL : https://patchwork.freedesktop.org/series/68472/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
K
On 2019-10-23 at 14:31:04 +0100, Chris Wilson wrote:
> If we are doing a normal GPU reset triggered after detecting a long
> period of stalled work, we can take our time and allow the engines to
> quiesce. Since we've stopped submission to the engine, and if we wait
> long enough an innocent contex
== Series Details ==
Series: series starting with [1/2] drm/property: Enforce more lifetime rules
URL : https://patchwork.freedesktop.org/series/68467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14952
S
== Series Details ==
Series: drm/i915: register vga switcheroo later, unregister earlier (rev2)
URL : https://patchwork.freedesktop.org/series/67644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14951
Sum
== Series Details ==
Series: series starting with [1/2] drm/property: Enforce more lifetime rules
URL : https://patchwork.freedesktop.org/series/68467/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
33ce34335c16 drm/property: Enforce more lifetime rules
-:40: CHECK:LINE_SPACING:
== Series Details ==
Series: drm/i915: Making loglevel of PSR2/SU logs same.
URL : https://patchwork.freedesktop.org/series/68439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14940_full
Summary
== Series Details ==
Series: mdev based hardware virtio offloading support (rev6)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14949
Summary
---
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/gt: Try to more gracefully
quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68463/
State : failure
== Summary ==
Applying: drm/i915/gt: Try to more gracefully quiesce the system before resets
Us
Hi RK,
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Tuesday, October 22, 2019 5:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna ; Ville Syrjala
> ; Pandiyan, Dhinakaran
> ; Kondapally, Kalyan
> ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject:
Adaptive Sync is a VESA feature so add a DRM core helper to parse
the EDID's detailed descritors to obtain the adaptive sync monitor range.
Store this info as part fo drm_display_info so it can be used
across all drivers.
This part of the code is stripped out of amdgpu's function
amdgpu_dm_update_f
Make trebly sure that all possible callbacks and their delayed brethren
are complete before asserting that the i915_active should be idle after
flushing all barriers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 1 +
1 file changed, 1 insertion(+)
diff -
On Wed, 2019-10-23 at 15:56 -0700, Andrew Morton wrote:
> And doing this will cause additional savings: calling a single-arg
> out-of-line function generates less .text than calling yesno().
I get no change in size at all with any of
extern
static __always_inline
with either of boo
== Series Details ==
Series: mdev based hardware virtio offloading support (rev6)
URL : https://patchwork.freedesktop.org/series/66989/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dbcc3602f990 mdev: class id support
cdfeed47be7f modpost: add support for mdev class id
d18fa8d0
== Series Details ==
Series: series starting with [1/3] drm/i915/dmabuf: Implement pwrite() callback
URL : https://patchwork.freedesktop.org/series/68428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14939_full
==
Quoting Kumar Valsan, Prathap (2019-10-24 00:26:06)
> On Wed, Oct 23, 2019 at 01:21:51PM +0100, Chris Wilson wrote:
> > +
> > + /*
> > + * If the user has disabled hangchecking, we can not be sure that
> > + * the batches will ever complete after the context is closed,
> > + * ke
When setting up the system to perform the atomic reset, we need to
serialise with any ongoing interrupt tasklet or else:
<0> [472.951428] i915_sel-44420d..1 466527056us : __i915_request_submit:
rcs0 fence 11659:2, current 0
<0> [472.951554] i915_sel-44420d..1 466527059us :
__execlists_su
On Wed, Oct 23, 2019 at 01:21:51PM +0100, Chris Wilson wrote:
> Normally, we rely on our hangcheck to prevent persistent batches from
> hogging the GPU. However, if the user disables hangcheck, this mechanism
> breaks down. Despite our insistence that this is unsafe, the users are
> equally insiste
We would like some freedom to break the user API/ABI for future HW but
yet still expose the driver for upstream development on that HW.
Currently, we have the i915.force_probe module parameter to avoid binding
to HW while the driver is under development, but that is still a little
too soft with res
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual physic
We monitor the health of the system via periodic heartbeat pulses. The
pulses also provide the opportunity to perform garbage collection.
However, we interpret an incomplete pulse (a missed heartbeat) as an
indication that the system is no longer responsive, i.e. hung, and
perform an engine or full
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspa
When we allow ourselves to sleep before a GPU reset after disabling
submission, even for a few milliseconds, gives an innocent context the
opportunity to clear the GPU before the reset occurs. However, how long
to sleep depends on the typical non-preemptible duration (a similar
problem to determini
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later
Our existing behaviour is to allow contexts and their GPU requests to
persist past the point of closure until the requests are complete. This
allows clients to operate in a 'fire-and-forget' manner where they can
setup a rendering pipeline and hand it over to the display server and
immediately exit
After initialising a preemption request, we give the current resident a
small amount of time to vacate the GPU. The preemption request is for a
higher priority context and should be immediate to maintain high
quality of service (and avoid priority inversion). However, the
preemption granularity of
On Wed, 23 Oct 2019 16:13:08 +0300 Jani Nikula wrote:
> The kernel has plenty of ternary operators to choose between constant
> strings, such as condition ? "yes" : "no", as well as value == 1 ? "" :
> "s":
>
> $ git grep '? "yes" : "no"' | wc -l
> 258
> $ git grep '? "on" : "off"' | wc -l
> 204
On 10/23/19 8:14 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchw
Hi,
Even though I tried to link this patch with it's first version by
specifying --in-reply-to=, it wasn't successful. So here is
the link to the first version of the patch and the discussion.
https://patchwork.freedesktop.org/patch/305153/?series=60697&rev=1
The first version of this patch has
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gt: Try to more gracefully
quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14948
On Wed, 23 Oct 2019 21:07:50 +0800
Jason Wang wrote:
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/mdev_core.c| 20
> drivers/vfio/mdev/mdev_private.h | 2 +
>
> -Original Message-
> From: Jason Wang
> Sent: Wednesday, October 23, 2019 8:08 AM
> To: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org;
> kwankh
Quoting Patchwork (2019-10-23 22:20:49)
> * igt@i915_selftest@live_workarounds:
> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>[4]:
> https://intel-gfx-ci.01.org/tree
Right now if sink reported any PSR error or if it fails to
acknowledge the PSR wakeup it sets a flag and do not attempt to
enable PSR anymore. That is the safest approach to avoid repetitive
glitches and allowed us to have PSR enabled by default.
But from time to time even good PSR panels have a P
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gt: Try to more gracefully
quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68457/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
139aa7679696 drm/i915/gt: Try to more gracefully
On Wed, 23 Oct 2019 21:07:48 +0800
Jason Wang wrote:
> Add support to parse mdev class id table.
>
> Reviewed-by: Parav Pandit
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/vfio_mdev.c | 2 ++
> scripts/mod/devicetable-offsets.c | 3 +++
> scripts/mod/file2alias.c | 10
On Wed, 23 Oct 2019 21:07:47 +0800
Jason Wang wrote:
> Mdev bus only supports vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> the first driver could be virtio-mdev. This means we need to add
> device class id support in bus m
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14947
Summary
---
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev6)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7128_full -> Patchwork_14880_full
Summary
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:9: ERROR:GIT_COMMIT_ID: Please
On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote:
> Probe the mocs registers for new contexts and across GPU resets. Similar
> to intel_workarounds, we have tables of what register values we expect
> to see, so verify that user contexts are affected by them. In the
> future, we should a
== Series Details ==
Series: drm/simple-kms: Standardize arguments for callbacks
URL : https://patchwork.freedesktop.org/series/68452/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7163 -> Patchwork_14946
Summary
---
On Wed, 2019-10-23 at 16:23 +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2019, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> > > If all pipes are fused off it means that display is disabled,
> > > similar
> > > like we handle for GEN 7 and 8 right above but
On 23/10/2019 19:12, Mika Kuoppala wrote:
Tapani Pälli writes:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli
---
drivers/gpu/
On Tue, Oct 22, 2019 at 07:09:47PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add new CNL PCH ID seen on a CML platform
> URL : https://patchwork.freedesktop.org/series/68375/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log
On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > HDCP could be fused off, so not all GEN9+ platforms will support
> > it.
> Here HDCP stands for HDCP1.4, so please call it so.
Okay, will update the commit description with th
== Series Details ==
Series: drm/simple-kms: Standardize arguments for callbacks
URL : https://patchwork.freedesktop.org/series/68452/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2d7d097edac5 drm/simple-kms: Standardize arguments for callbacks
-:15: WARNING:BAD_SIGN_OFF: 'Ack
On Tue, Oct 22, 2019 at 05:03:00PM +0300, Jani Nikula wrote:
> Add definition for block 56, the compression parameters.
>
Would this be used on DP connectors for DSC as well?
Manasi
> Cc: Vandita Kulkarni
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50
On Fri, Oct 18, 2019 at 05:41:24PM -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
>
> Cc: Manasi Navare
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/displ
== Series Details ==
Series: Extract rps and guc
URL : https://patchwork.freedesktop.org/series/68449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7162 -> Patchwork_14945
Summary
---
**SUCCESS**
No regressions f
== Series Details ==
Series: Extract rps and guc
URL : https://patchwork.freedesktop.org/series/68449/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0ebf20b3737a drm/i915: Extract GT render power state management
-:279: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s)
On Wed, 2019-10-23 at 13:55 +0530, kamal...@intel.com wrote:
> From: "Ap Kamal"
>
> 'Link CRC error' will now have same error level as
> other PSR2 errors like 'RFB storage error' and
> 'VSC SDP uncorrectable error'.
Yeah this should also be a debug message.
Will push it as soon as we get a shar
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14937_full
Summ
== Series Details ==
Series: drm/i915/selftests: Release ctx->engine_mutex after iteration
URL : https://patchwork.freedesktop.org/series/68420/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14936_full
Certain laptops now come with panels that have integrated privacy
screens on them. This patch adds support for such panels by adding
a privacy-screen property to the drm_connector for the panel, that
the userspace can then use to control and check the status. The idea
was discussed here:
https://l
On 2019-10-21 3:42 p.m., Bhawanpreet Lakha wrote:
> The content protection tests only start if this debugfs entry exists.
> Since the name is specific to intel driver these tests cannot be used with
> other drivers. So we should check generic debugfs name also
>
> v2: Check i915_* if device is i91
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14934_full
Summary
---
*
Tapani Pälli writes:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c |
Quoting Janusz Krzysztofik (2019-10-23 16:29:15)
> Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
> addresses for !ppgtt") introduced filtering of addresses possibly
> occupied by other users of shared GTT. Unfortunately, that filtering
> is unconditional, no matter if running on
On Wed, Oct 23, 2019 at 12:13 PM Daniel Vetter wrote:
> Passing the wrong type feels icky, everywhere else we use the pipe as
> the first parameter. Spotted while discussing patches with Thomas
> Zimmermann.
>
> v2: Make xen compile correctly
>
> Acked-By: Thomas Zimmermann (v1)
> Cc: Thomas Zim
Quoting Tvrtko Ursulin (2019-10-14 14:08:12)
>
> On 11/10/2019 16:11, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-11 15:56:35)
> >>
> >> On 10/10/2019 08:14, Chris Wilson wrote:
> >>> If we do find ourselves with an idle barrier inside our active while
> >>> waiting, attempt to flush i
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addresses possibly
occupied by other users of shared GTT. Unfortunately, that filtering
is unconditional, no matter if running on old shared GTT or not. When
running on full (non-aliasi
The basic-range subtest have been already taught to calculate softpin
offsets from minimum batch size, however it still uses a hardcoded
value of 4kB. On future backends with possibly bigger minimum batch
sizes this subtest will fail as buffer objects may overlap.
Detect minimum batch size instea
From: Janusz Krzysztofik
The basic-range subtest assumes 4kB minimum batch size. On future
backends with possibly bigger minimum batch sizes this subtest will
fail as buffer objects may overlap on softpin. To avoid object
overlapping, softpin offsets need to be calculated with actual minimum
ba
On 2019-10-21 at 15:42:59 -0400, Bhawanpreet Lakha wrote:
> The content protection tests only start if this debugfs entry exists.
> Since the name is specific to intel driver these tests cannot be used with
> other drivers. So we should check generic debugfs name also
>
> v2: Check i915_* if devic
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159 -> Patchwork_14944
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14932_full
===
Op 22-10-2019 om 20:32 schreef Ville Syrjälä:
> On Thu, Oct 17, 2019 at 03:20:59PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>> Color
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ffa7a93754dd drm/i915: Refactor intel_can_enable_sagv
-:94: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match o
They're midlayer, broken, and because of the old gunk, we can't fix
them. For examples see the various checks in drm_mode_object.c against
dev->registered, which cannot be enforced if the driver still uses the
load hook.
Unfortunately our biggest driver still uses load/unload, so this would
be rea
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:3754:6: warn
== Series Details ==
Series: drm/i915/gt: Try to more gracefully quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159 -> Patchwork_14943
S
Properties can't be attached after registering, userspace would get
confused (no one bothers to reprobe really).
- Add kerneldoc
- Enforce this with some checks. This needs a somewhat ugly check
since connectors can be added later on, but we still need to attach
all properties before they go p
== Series Details ==
Series: drm/i915/gt: Try to more gracefully quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68445/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2e59d4f9691e drm/i915/gt: Try to more gracefully quiesce the system before
rese
== Series Details ==
Series: drm/i915/bios: add compression parameter block definition
URL : https://patchwork.freedesktop.org/series/68396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14928_full
Su
On 2019-10-18 at 17:41:22 -0700, José Roberto de Souza wrote:
> Check if FBC is fused off and handle it.
>
> Cc: Ville Syrjälä
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>
On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and m
On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
Here HDCP stands for HDCP1.4, so please call it so.
>
> Cc: Ville Syrjälä
> Cc: Martin Peres
> Reviewed-by: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/hu
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely. Also
rather than do this for every backend, just limit to our two memory
types: system and
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Signed-off-by: Matthew
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/dr
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