== Series Details ==
Series: series starting with [1/5] drm/i915: Switch
intel_legacy_cursor_update() to intel_ types
URL : https://patchwork.freedesktop.org/series/67337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6969_full -> Patchwork_14566_full
== Series Details ==
Series: series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14577
===
== Series Details ==
Series: series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67359/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
be9b536ad361 drm/i915: Move SAGV block time to dev_priv
-:56: WARNING:UN
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev3)
URL : https://patchwork.freedesktop.org/series/66814/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14576
Summary
--
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev3)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fa405794ca6b drm/framebuffer: Format modifier for Intel Gen-12 render
compression
dc89777e03
== Series Details ==
Series: series starting with [1/3] drm/i915: Add microcontrollers documentation
section
URL : https://patchwork.freedesktop.org/series/67356/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14575
===
== Series Details ==
Series: drm/i915: Update references to previously renamed files (rev2)
URL : https://patchwork.freedesktop.org/series/67295/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6967_full -> Patchwork_14565_full
===
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Rev
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified ge
== Series Details ==
Series: drm/i915: Extract GT render sleep (rc6) management (rev2)
URL : https://patchwork.freedesktop.org/series/66937/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6967_full -> Patchwork_14564_full
Su
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse n
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified ge
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Rev
== Series Details ==
Series: series starting with [1/3] drm/i915: Pass intel_gt to has-reset?
URL : https://patchwork.freedesktop.org/series/67355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14574
Summa
== Series Details ==
Series: drm/i915/selftests: Do not try to sanitize mock HW
URL : https://patchwork.freedesktop.org/series/67354/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14573
Summary
---
On Fri, Sep 27, 2019 at 10:17:49PM +0100, Chris Wilson wrote:
> For those mock tests that may wish to pretend triggering a GPU reset and
> processing the cleanup.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
looks better! Thanks!
Reviewed-by: Andi Shyti
Andi
_
On Fri, Sep 27, 2019 at 10:17:48PM +0100, Chris Wilson wrote:
> On systems that have no runtime-pm, we mark the wakeref as being -1. We
> therefore cannot use that value for the mock-gt indicator, so opt for
> -ENODEV instead. The wakeref should never be an error value -- one
> hopes!
-1 (EPERM) i
Hi Chris,
On Fri, Sep 27, 2019 at 10:17:47PM +0100, Chris Wilson wrote:
> As we execute GPU results on a gt/ basis, and use the intel_gt as the
> primary for all other reset functions, also use it for the has-reset?
> predicated. Gradually simplifying the churn of pointers.
>
> Signed-off-by: Chr
To better organize the information, add a microcontrollers section and
move/link the GuC, HuC and DMC documentation under it. Also add a small
intro.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Documentation/gpu/i915.rst | 18 ++
1 file changed, 18 insertions(
Add a short description of what we expect from GuC and some minor
improvements to existing documentation. Also remove a comment about a
difference between GuC and HuC that is not true anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Matthew Brost
---
Documentation/gpu/i9
Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Documentation/gpu/i915.rst| 10
On 9/27/19 11:04 AM, Robert M. Fosha wrote:
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert
As we execute GPU results on a gt/ basis, and use the intel_gt as the
primary for all other reset functions, also use it for the has-reset?
predicated. Gradually simplifying the churn of pointers.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_display.c | 2
On systems that have no runtime-pm, we mark the wakeref as being -1. We
therefore cannot use that value for the mock-gt indicator, so opt for
-ENODEV instead. The wakeref should never be an error value -- one
hopes!
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt
For those mock tests that may wish to pretend triggering a GPU reset and
processing the cleanup.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_reset.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_res
Quoting Chris Wilson (2019-09-27 20:14:42)
> -static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
> +static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> {
> - if (INTEL_GEN(i915) >= 8)
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if (is_mo
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/dri
Ville, Maarten
In this patch, I added a WARN ON for the case where the same trans could be
configured as master and slave.
Does this look good?
Manasi
On Thu, Sep 26, 2019 at 05:11:10PM -0700, Manasi Navare wrote:
> After the state is committed, we readout the HW registers and compare
> the H
Quoting Andi Shyti (2019-09-27 21:41:19)
> Hi Chris,
>
> On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote:
> > For those mock tests that may wish to pretend triggering a GPU reset and
> > processing the cleanup.
>
> The patch is OK, per se, but I think it should be split in two
> part
Quoting Matthew Auld (2019-09-27 18:34:05)
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
> b/drivers/gpu/drm/i915/selftests/i915_gem.c
> index 37593831b539..4951957a4d8d 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
> @@ -42,6
Quoting Matthew Auld (2019-09-27 18:34:04)
> From: Daniele Ceraolo Spurio
>
> We can't fence anything without aperture.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
> 1 file changed,
On Wed, Sep 25, 2019 at 11:01:24AM +0100, Chris Wilson wrote:
> Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> that we can expose properties on each engine to the sysadmin.
>
> To start with we have basic analogues of the i915_query ioctl so that we
> can pretty print engin
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:43PM +0100, Chris Wilson wrote:
> If we are mocking the device, skip trying to sanitize the pm HW state.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion
Quoting Matthew Auld (2019-09-27 18:33:59)
> + mem->id = intel_region_map[i];
> + mem->type = type;
> + mem->instance =
> MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
So why 3xu32 for a single u32 of information? Either one or two u32
would do, depen
Quoting Matthew Auld (2019-09-27 18:33:57)
> + i = 0;
> + engines = i915_gem_context_lock_engines(ctx);
> + do {
> + u32 rng = prandom_u32_state(&prng);
> + u32 dword = offset_in_page(rng) / 4;
> +
> + ce = engines->engines[order[i] % engi
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote:
> For those mock tests that may wish to pretend triggering a GPU reset and
> processing the cleanup.
The patch is OK, per se, but I think it should be split in two
parts:
- the i915 to gt conversion (that is the biggest par
Quoting Matthew Auld (2019-09-27 18:33:56)
> +static int igt_lmem_write_cpu(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> + struct drm_i915_gem_object *obj;
> + struct rnd_state prng;
> + u
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev4)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +__intel_memory_region_put_block_buddy(struct i915_buddy_block *block)
> +{
> + struct list_head blocks;
LIST_HEAD(blocks); (and no INIT_LIST_HEAD required)
> +
> + INIT_LIST_HEAD(&blocks);
> + list_add(&block->link, &blocks);
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Provide a mock GPU reset
routine
URL : https://patchwork.freedesktop.org/series/67353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14571
===
Hi Dave and Daniel,
This should've gone out yesterday, but apparently I had some issue with my mutt
here.
Anyway, nothing that couldn't wait for rc2
Here goes drm-intel-next-fixes-2019-09-26:
- Fix concurrence on cases where requests where getting retired at same time as
resubmitted to HW
- Fix
Quoting Ville Syrjala (2019-09-19 17:30:52)
> From: Ville Syrjälä
>
> Random smattering of patches to eliminate compiler warnings.
> Some I just suppressed out of lazyness, others I tried to
> silence by adjusting the code a bit.
Some of the aliasing pointer avoidance looked silly, but silly com
Quoting Matthew Auld (2019-09-27 18:34:01)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> index 0aeaebb41050..77e89fabbddf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> @@ -
Quoting Matthew Auld (2019-09-27 18:33:57)
> +static int igt_gpu_write_dw(struct intel_context *ce,
> + struct i915_vma *vma,
> + u32 dword,
> + u32 value)
> +{
> + int err;
> +
> + i915_gem_object_lock(vma->o
Quoting Matthew Auld (2019-09-27 18:33:56)
> static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
> .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> -I915_GEM_OBJECT_IS_SHRINKABLE,
> +I915_GEM_OBJECT_IS_SHRINKABLE |
> +I91
== Series Details ==
Series: drm/i915/guc: Update H2G enable logging action definition
URL : https://patchwork.freedesktop.org/series/67351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14570
Summary
For those mock tests that may wish to pretend triggering a GPU reset and
processing the cleanup.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 32 +--
drivers/gpu/drm/i915/gt/
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/inte
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev3)
URL : https://patchwork.freedesktop.org/series/67043/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6966_full -> Patch
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14569
Summary
---
**SUCCESS**
No regressions found.
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Matthew Auld
>Sent: Friday, September 27, 2019 1:34 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: daniel.vet...@ffwll.ch
>Subject: [Intel-gfx] [PATCH 04/22] drm/i915/region: support continuous
Quoting Matthew Auld (2019-09-27 18:33:54)
> +const u32 intel_region_map[] = {
> + [INTEL_MEMORY_SMEM] = BIT(INTEL_SMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_LMEM] = BIT(INTEL_LMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_STOLEN] = BIT(INTEL_ST
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: check for kernel_context
Okay!
Commit: drm/i915: simplify i915_gem_init_early
Okay!
Commit: drm/i9
Quoting Matthew Auld (2019-09-27 18:33:51)
> struct drm_i915_gem_object *
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 4e1805aaeb99..f9fbf2865782 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/dr
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ccc51e3ac24e drm/i915: check for kernel_context
dbbfe24cafca drm/i915: simplify i915_gem_init_early
f52b9b0685d8 drm/i915: introduce inte
Quoting Chris Wilson (2019-09-27 19:24:43)
> Quoting Matthew Auld (2019-09-27 18:33:50)
> > +static void close_objects(struct list_head *objects)
> > +{
> > + struct drm_i915_private *i915 = NULL;
> > + struct drm_i915_gem_object *obj, *on;
> > +
> > + list_for_each_entry_safe(obj
Quoting Matthew Auld (2019-09-27 18:33:50)
> +static void close_objects(struct list_head *objects)
> +{
> + struct drm_i915_private *i915 = NULL;
> + struct drm_i915_gem_object *obj, *on;
> +
> + list_for_each_entry_safe(obj, on, objects, st_link) {
> + i915 = to_i91
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +intel_memory_region_destroy(struct intel_memory_region *mem)
> +{
> + if (mem->ops->release)
> + mem->ops->release(mem);
> +
mutex_destroy(&mem->mm_lock);
> + kfree(mem);
> +}
__
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
Wrong address. I ignore all patches going there, so it's not doing you
any
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Aus
And pushed.
Daniele
On 9/26/19 8:30 AM, Patchwork wrote:
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full
Quoting Matthew Auld (2019-09-27 18:34:08)
> From: CQ Tang
>
> drm_mm_insert_node_in_range() treats range_start > range_end as a
> programmer error, such that we explode in insert_mappable_node. For now
> simply check for missing aperture on such paths.
range_start is 0.
range_end is 0.
drm_mm_
On 9/26/19 12:37 AM, Michal Wajdeczko wrote:
On Thu, 26 Sep 2019 01:03:20 +0200, Summers, Stuart
wrote:
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
The HuC FW has silently switched to encoding the version the same way
as
the GuC FW does, i.e. major.minor.patch instead
Quoting Matthew Auld (2019-09-27 18:34:06)
> @@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
> if (ret)
> return ret;
>
> - /* Reserve a mappable slot for our lockless error capture */
> - ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &gg
On Wed, Sep 25, 2019 at 01:33:50PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, extract the setting to a separate function. While
> we're at it, update the if ladder to follow the new gen -> old gen order
> preference, and
On Fri, 2019-09-27 at 17:24 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE
> programming
> URL : https://patchwork.freedesktop.org/series/67312/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6966_f
Hi Alex,
> -Original Message-
> From: Alex Williamson
> Sent: Tuesday, September 24, 2019 6:07 PM
> To: Jason Wang
> Cc: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel-gvt-...
Quoting Matthew Auld (2019-09-27 18:33:49)
> i915_gem_init_early doesn't need to return anything.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/
Quoting Matthew Auld (2019-09-27 18:33:48)
> Explosions during early driver init on the error path. Make sure we fail
> gracefully.
Joonas would complain about the clearly not onion unwind here, but we
have thrown it in as a catch-all cleanup for what is quite a complicated
setup.
> [ 9547.67225
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile
From: CQ Tang
drm_mm_insert_node_in_range() treats range_start > range_end as a
programmer error, such that we explode in insert_mappable_node. For now
simply check for missing aperture on such paths.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 6 +
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_g
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the apertu
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++---
1 file changed, 21 insertions(
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.h
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drive
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangc
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
dr
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 7
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index b6dc90030156..434c1fc57ad
i915_gem_init_early doesn't need to return anything.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 4 +---
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i9
Some kernel internal objects may need to be allocated as a continuous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtine
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_intern
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 inserti
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support
basic LMEM object creation within the kernel. From there we can start with the
dumb buffer support, and then the other display related bits.
We still have a few patches that deal with lack of MAPPABLE_APERTURE support,
thoug
Explosions during early driver init on the error path. Make sure we fail
gracefully.
[ 9547.672258] BUG: kernel NULL pointer dereference, address: 007c
[ 9547.672288] #PF: supervisor read access in kernel mode
[ 9547.672292] #PF: error_code(0x) - not-present page
[ 9547.672296] PGD
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
URL : https://patchwork.freedesktop.org/series/67312/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full
On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> > active. Update intel_can_enable_sagv to allow this, and loop through all
> > active planes on a
== Series Details ==
Series: drm/i915/userptr: Never allow userptr into the mappable GGTT
URL : https://patchwork.freedesktop.org/series/67349/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6969 -> Patchwork_14568
Summary
-
On 2019-09-27 at 19:38:49 +0300, Imre Deak wrote:
> On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> > Adding DC3CO counter in i915_dmc_info debugfs will be
> > useful for DC3CO validation.
> > DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> > register on TGL, as per B.Spe
Quoting Tvrtko Ursulin (2019-09-25 16:59:26)
>
> On 25/09/2019 09:23, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-23 09:10:26)
> >>
> >> On 20/09/2019 17:35, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
>
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